CN102194875A - 装置与半导体元件的形成方法 - Google Patents

装置与半导体元件的形成方法 Download PDF

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CN102194875A
CN102194875A CN2010102356718A CN201010235671A CN102194875A CN 102194875 A CN102194875 A CN 102194875A CN 2010102356718 A CN2010102356718 A CN 2010102356718A CN 201010235671 A CN201010235671 A CN 201010235671A CN 102194875 A CN102194875 A CN 102194875A
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CN102194875B (zh
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庄学理
张立伟
周汉源
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种装置，包括半导体元件，且半导体元件包括：半导体基板，有沟道区；高介电常数的介电层，位于至少部分沟道区上；栅极，位于至少分沟道区上与介电层上，其中栅极实质上为金属；以及栅极接点，接合栅极位于沟道区上。本发明也提供一种形成半导体元件的方法，包括：提供具有道区的半导体基板；形成高介电常数的介电层于至少部分沟道区上；形成栅于介电层上与至少部分沟道区上，且栅极实质上为金属；以及形成栅极接点沟道区上并接合栅极。本发明中，栅极结构不需要额外层，可降低有效栅电阻。

Description

装置与半导体元件的形成方法
技术领域
本发明涉及半导体元件，更特别涉及其栅极接点、源极接点、及/或漏极接点的相对位置。
背景技术
半导体集成电路产业已快速成长一段时日。随着IC材料与设计的进步，每一代的IC均比前一代的IC更小更复杂。工艺尺寸缩小有益于提高工艺效率及相关成本。然而上述进步也会增加集成电路工艺及生产的复杂性，集成电路工艺也需要同样的进展以实现新世代的IC。在集成电路进步的过程中，其功能密度(每单位面积的芯片具有的内连线元件数目)越来越大，而其尺寸(工艺所能形成的最小元件或连线)则越来越小。上述尺寸缩减也会造成高功率消耗，这可通过采用低功率消耗的元件如互补式金属氧化物半导体(CMOS)元件来改善。
在这股尺寸缩小的趋势中，有多种材料被采用为CMOS元件的栅极或栅极介电层，其中一种组合为金属栅极搭配高介电常数的栅极介电层。然而高介电常数金属栅极(HKMG)元件的栅极结构通常需要额外层。举例来说，为了调整金属栅极的功函数，需要额外的功函数层。此外，阻挡层(或盖层)常用以辅助HKMG的工艺。虽然这些方法已达成部分目的，但未达成所有的目的。举例来说，HKMG栅极堆叠的额外层会增加其有效电阻值。特别是模拟的HKMG元件中，电阻增加可能会降低元件效能。
发明内容
为克服现有技术的上述缺陷，本发明提供一种装置，包括半导体元件，且半导体元件包括：半导体基板，具有沟道区；高介电常数的介电层，位于至少部分沟道区上；栅极，位于至少部分沟道区上与介电层上，其中栅极实质上为金属；以及栅极接点，接合栅极并位于沟道区上。
本发明也提供一种装置，包括一集成电路，且该集成电路包括：半导体基板，具有绝缘区及分开的第一沟道区与第二沟道区；高介电常数的介电层，位于至少部分第一沟道区上；第二介电层，位于至少部分该第二沟道区上与至少部分该绝缘区上；第一栅极，位于至少部分该第一沟道区上的第一介电层上，其中第一栅极实质上为金属；第二栅极，位于第二介电层上，第二栅极的第一部分位于第二沟道区上，且该第二栅极的第二部分位于绝缘区上；第一栅极接点，接合第一栅极，且第一栅极接点位于第一沟道区上；以及第二栅极接点，接合第二栅极并位于绝缘区上，且第二沟道区上不含第二接点与第二栅极接合。
本发明还提供一种形成半导体元件的方法，包括：提供具有沟道区的半导体基板；形成高介电常数的介电层于至少部分沟道区上；形成栅极于介电层与至少部分沟道区上，且栅极实质上为金属；以及形成栅极接点于沟道区上并接合栅极。
本发明中，栅极结构不需要额外层，可降低有效栅极电阻。
附图说明
图1是本发明一实施例中，半导体元件的俯视图；
图2是图1中，沿着2-2切线的半导体元件剖视图；
图3-图8是图1-图2的半导体元件的工艺剖视图；以及
图9是图3-图8的工艺的高阶流程图。
其中，附图标记说明如下：
D1、D2～方向；2-2～切线；10～半导体元件；12～模拟元件；14～数字元件；16～半导体基板；18、20～绝缘区；22、26～源极区；24、28～漏极区；30、32～沟道区；34、34A、36～界面层；38、38A、40～介电层；42、44～阻挡层；46、48～栅极；50、52～功函数层；51、53～金属层；54、58～栅极结构；56、60～栅极长度；62、64～侧壁间隔物；66～层间介电层；68、70～源极接点；72、74～漏极接点；76、78～栅极接点；100、100A～虚置栅极层；102、102A～硬掩模层；104～暂时的栅极堆叠；106～开口；110～工艺；112、113、114、116、、118、120、122、124、126～步骤。
具体实施方式
可以理解的是，下述内容提供多种实施例以说明本发明的多种特征。为了简化说明，将采用特定的实施例、单元、及组合方式说明。然而这些特例仅用以说明而非限制本发明。此外为了简化说明，本发明在不同附图中采用相同符号标示不同实施例的类似元件，但上述重复的符号并不代表不同实施例中的元件具有相同的对应关系。举例来说，形成某一元件于另一元件上包含了两元件为直接接触，或者两者间隔有其他元件这两种情况。
图1是半导体元件10的俯视图，而图2是沿着图1中2-2切线的剖视图。半导体元件10是具有模拟元件12与数字元件14的集成电路。在图1-图2的实施例中，模拟元件12与数字元件14为金属氧化物半导体场效应晶体管(MOSFET)。更进一步来说，这些元件属于采用HKMG技术的p型MOSFET。在其他实施例中，模拟元件可为其他已知的模拟半导体元件如射频(RF)元件、输入/输出(I/O)元件、或放大器。在其他实施例中，数字元件可为其他已知的数字半导体元件如记忆存储元件(例如静态随机存取存储器(SRAM))。半导体元件10中的模拟元件12与数字元件14彼此分开，但两者可能彼此邻接或以其他相对位置配置。
半导体元件10形成于硅组成的半导体基板16上。除了硅以外，半导体基板16也可为其他半导体元素如锗，半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟，半导体合金如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP，或上述的组合。
绝缘区18与20的形成方式为蚀刻半导体基板16形成沟槽后，再将介电材料填入沟槽。在图1-图2的实施例中，绝缘区18与20为环状并分别围绕模拟元件12与数字元件14，以避免上述元件与其他形成于半导体基板16上的元件之间产生电子干扰或串音。用以电性绝缘模拟元件12与数字元件14的绝缘区18与20的定义方法为浅沟槽绝缘(STI)。绝缘区18与20由氧化硅组成。然而在其他实施例中，绝缘区18与20可为氮化硅、氮氧化硅、其他合适材料、及/或上述的组合。绝缘区18与20也可为多层结构，比如将氮化硅或氧化硅填入热氧化衬垫层中。
半导体基板16的模拟元件12包含源极区22与漏极区24，而数字元件14包含源极区26与漏极区28。绝缘区18定义每一源极区22与每一漏极区24的外侧范围，而绝缘区20定义每一源极区26与每一漏极区28的外侧范围。上述源极区与漏极区均为掺杂阱区，其掺质型态将视最后完成的元件而定。在此实施例中，由于上述元件属pMOS晶体管，因此源极区22及26与漏极区24及28为p型掺杂，其p型掺质可为硼、BF2、或上述的组合。在其他实施例中，若上述元件属nMOS晶体管，则源极区与漏极区可为n型掺杂，其n型掺质可为磷、砷、或上述的组合。
半导体基板16中的沟道区30定义于源极区22与漏极区24之间。源极区22与漏极区24沿着D1方向相隔一段距离，两者之间的沟道区30沿着D2方向延伸，且D1方向垂直于D2方向。类似地，数字元件14中的沟道区32定义于源极区26与漏极区28之间。源极区26与漏极区28沿着D1方向相隔一段距离，两者之间的沟道区32沿着D2方向延伸，且D1方向垂直于D2方向。当模拟元件12与数字元件14导通时，半导体基板16中的沟道区30与32是主要载子如空穴在源极与漏极之间流动的地方。
半导体基板16上的界面层34与36，分别位于沟道区30与32上。界面层34与36由氧化硅如热氧化层或化学氧化层所组成，其厚度约为5埃至20埃之间。在其他实施例中，界面层34与36也可为氮氧化硅或其他氧化物材料。
高介电常数的介电层38与40分别位于界面层34与36上，并分别位于沟道区30与32上。介电层38与40由高介电常数材料所组成。在图1-图2的实施例中，介电层38与40为HfO2。除此之外，介电层38与40可为HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfLaO、LaSiO、AlSiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物、其他合适的高介电常数材料、及/或上述的组合。在其他实施例中，数字元件14中的介电层40可为一般的介电材料如SiO2，其具有中等的介电常数如3.9。介电层38与40的厚度约为10埃至30埃之间。
阻挡层42与44分别位于高介电常数的介电层38与40上，且分别位于沟道区30与32上。阻挡层42与44也称作盖层、扩散阻挡层、或蚀刻停止层(ESL)。阻挡层42与44由氮化钽组成。在其他实施例中，阻挡层42与44也包含钛、氮化钛、钽、钨、铝、TaCN、TiAlN、TaSiN、WN、其他合适材料、及/或上述的组合。在此实施例中，阻挡层42与44的厚度约介于10埃至200埃之间。
栅极46与48分别位于阻挡层42与44上，且分别位于沟道区30与32上。栅极46与48各自具有两个部分，如功函数层50与52及金属层51与53。进一步来说，功函数层50与52属于栅极46与48中最接近阻挡层42与44的部分。金属层51与53属于栅极46与48中较上层的部分。栅极46与48中被定义为功函数层50与52的部分具有适当的功函数。功函数的定义将某一材料中的电子移至材料表面外所需的最小能量。在此实施例中，功函数层50与52由氮化钛所组成，属于p型功函数材料，其厚度约介于10埃至200埃之间。其他适用于pMOS元件的p型功函数材料包括钨、氮化钨、或上述的组合。在其他实施例中，适用于nMOS元件的n型功函数材料包括氮化钽、铝化钛、氮化钛铝、或上述的组合。栅极46与48的上层部分分别定义为金属层51与53，由导电金属如铝所组成。除了铝之外，金属层51与53也可为铜、钨、钛、其他合适材料、及/或上述的组合。
在另一实施例中，模拟元件12与数字元件14的栅极可省略功函数层，而由一整层金属所构成，但可以其他已知方法调整栅极结构使其具有适当的功函数。
模拟元件12的栅极结构54含有界面层34、高介电常数的介电层38、阻挡层42、与栅极42。栅极结构54的层数可更多或更少。栅极结构54与其层状结构位于沟道区30上，并沿着D2方向延伸直到绝缘区18的内侧为止。在其他实施例中，为了让模拟元件适当操作或其他考虑，栅极结构54可为任何形状。举例来说，栅极结构54在D2方向的尺寸可大于沟道区，并可能延伸出绝缘区18。如图1所示，栅极结构54的栅极长度56与沟道区30的宽度实质上相同。模拟元件12的栅极长度56约介于80nm至90nm之间，但可大于或小于上述范围。
数字元件14的栅极结构58含有界面层36、高介电常数的介电层40、阻挡层44、与栅极48。在其他实施例中，栅极结构58的层数可更多或更少，或为非HKMG栅极。在非HKMG栅极的例子中，栅极结构58可以只含有栅极介电层(如SiO2)与栅极(如适当掺杂的整层多晶硅)。栅极结构58与其层状结构位于沟道区32上，并沿着D2方向延伸到至少部分的绝缘区20上。在其他实施例中，栅极结构58位于绝缘区20上的宽度，大于位于沟道区32上的宽度。如此一来，可提供较大的表面积给内连线结构如半导体元件的第一金属层、第二金属层、或通孔。如图1所示，栅极结构58的栅极长度60近似于沟道区32的宽度。一般来说，模拟元件的栅极长度实质上大于数字元件(或核心元件)的栅极长度，因为模拟元件的线性要求较严格。在此实施例中，栅极结构54的栅极长度56近似于栅极结构58的栅极长度60的三倍。在其他实施例中，为了使集成电路适当操作，可根据数字元件的栅极长度，采用不同栅极长度的模拟元件。
栅极结构54中的界面层34、高介电常数的介电层38、阻挡层42、及栅极46的两侧分别具有侧壁间隔物62，且侧壁间隔物62与栅极结构54一样沿着D2方向延伸。同样地，栅极结构58中的界面层36、高介电常数的介电层40、阻挡层44、及栅极48的两侧分别具有侧壁间隔物64，且侧壁间隔物64与栅极结构58一样沿着D2方向延伸。侧壁间隔物62与64由介电材料组成。在此实施例中，侧壁间隔物62与64可为氮化硅。除了氮化硅之外，侧壁间隔物62与64也可为碳化硅、氮氧化硅、其他合适材料，及/或上述的组合。
层间介电层(ILD)66形成于半导体基板16与栅极结构54及58上。层间介电层66由氧化硅组成。在其他实施例中，层间介电层66可包含其他介电材料如氮化硅、氮氧化硅、四乙氧硅烷形成的氧化物、磷掺杂硅酸盐玻璃(PSG)、硼磷掺杂硅酸盐玻璃(BPSG)、低介电常数的介电材料、其他合适的介电材料、及/或上述的组合。低介电常数的介电材料包含氟掺杂硅酸盐玻璃(FSG)、碳掺杂氧化硅、Black(购自美国加州的Santa Clara公司)、干凝胶、气胶、非晶氟化碳、聚对二甲苯、双苯并环丁烷(BCB)、SiLK(购自美国密西根州的密德兰的Dow Chemical)、聚酰亚胺、其他合适材料、及/或上述的组合。层间介电材料66也可为多种介电材料组成的多层结构。
两个分开的源极接点68与两个分开的漏极接点72往下延伸穿过层间介电层66，并分别接合源极区22与漏极区24。所述多个接点将模拟元件12电性耦合至半导体元件10的内连线结构(未图示)。在图1-图2的实施例中，源极接点68与漏极接点72的俯视图均为正方形。在其他实施例中，接合源极区与漏极区的接点数目可大于或小于图示的数目，且接点可为任何形状。如图1所示，每一源极接点68在D2方向大抵各自对准漏极接点72之一。在其他实施例中，为了使模拟元件更好操作，源极接点68与漏极接点72可位于源极区与漏极区上的任何位置。在此实施例中，源极接点68与漏极接点72由铜组成，但上述接点也可由其他合适导电材料如钨所组成。
三个分开的源极接点70与三个分开的漏极接点74往下延伸穿过层间介电层66，并分别接合源极区26与漏极区28。所述多个接点将数字元件14电性耦合至半导体元件10的内连线结构(未图示)。虽然图1-图2的实施例已图示接点的数目及形状，但接合源极区26与漏极区28的接点数目可大于或小于图示的数目。与源极接点68及漏极接点72相较，源极接点70与漏极接点74可具有类似的尺寸、形状、及材料。但在其他实施例中，源极接点70与漏极接点的尺寸、形状、及材料可不同于源极接点68及漏极接点72。
两个分开的栅极接点76往下延伸穿过层间介电层66，并在沟道区30上不同的位置分别接合栅极46。栅极接点76将模拟元件12电性耦合至半导体元件10的内连线结构。栅极接点76的俯视形状近似于矩形，其长边大抵平行于D2方向与栅极结构54的长边。栅极接点76在D1方向的宽度小于栅极结构54的栅极长度56。此外如图1所示，栅极接点76在D2方向与源极接点68及漏极接点72交错。上述交错的设计可增加栅极接点与源极接点/漏极接点之间的最小距离，可避免栅极接点与源极接点/漏极接点之间发生短路(桥接)等现象。在图1-图2的实施例中，有一对栅极接点76接合至栅极46，但接合至栅极的栅极接点数目可大于或小于图示数目，且栅极接点可为任何形状。在此实施例中，栅极接点76由铜组成，但也可为其他合适导电材料如钨。
栅极接点78往下延伸穿过层间介电层66，并在绝缘区20上接合栅极48。栅极接点78将数字元件14电性耦合至半导体元件10的内连线结构。栅极接点78的宽度大于栅极长度60，因此有部分的栅极接点78接合侧壁间隔物64与绝缘区20。在其他实施例中，栅极接点78的宽度可等于或小于数字元件的栅极长度60，此时栅极接点78的所有底部将只接合栅极。在此实施例中，栅极接点78由铜组成，但也可为其他合适导电材料如钨。
如前所述，图1-图2所示的集成电路包含模拟元件与数字元件。在此实施例中，模拟元件的栅极长度56约比数字元件的栅极长度60大三倍以上。此差异将允许其他结构的差异。模拟元件12其较大的栅极长度可使位于栅极46上的栅极接触76直接位于沟道区30上，这是因为即使栅极接点偏离预定的接合位置，较宽的栅极长度可避免栅极接点桥接至源极或漏极。如此一来，模拟元件12中的栅极接点76接合至位于沟道区30上的栅极46，而数字元件14的栅极接点78接合至位于绝缘区20上的栅极48。
以HKMG技术制造模拟元件的副作用为提高栅极电阻。在HKMG元件如模拟元件12中，栅极结构54中的多层结构会比非HKMG元件具有更高的栅极电阻。不幸的是，高栅极电阻对模拟元件的伤害高于其对数字元件的伤害，这是因为模拟元件的线性要求更高。然而将栅极接点76置于栅极46与沟道区30上的作法可减少电阻。在模拟元件12中，栅极接点直接位于沟道区上，这可减少栅极接点至栅极介电层的距离，并降低有效栅极电阻。此外，增加沟道区上栅极接点的数目也可降低有效栅极电阻，这是因为栅极与栅极接点之间的接合面积提高，且栅极接点与栅极介电层的间的平均距离缩短。
半导体元件10并不限于应用上述的集成电路。在特定实施例中，半导体元件10中的集成电路可还包含无源元件如电阻、电容、电感、及/或熔断器；有源元件如MOSFET(包含p型MOSFET与n型MOSFET)、互补式MOS晶体管(CMOS)、高压晶体管、及/或高频晶体管；其他合适元件；及/或上述的组合。
如图3-图8所示，是图1-图2的模拟元件12的工艺剖示图。
如图3所示，提供硅材质的半导体基板16。绝缘区18形成于半导体基板16中，用以围绕并绝缘之后形成的模拟元件12。绝缘区18的形成方法为公知的浅沟槽绝缘(STI)技术，先在基板中蚀刻出沟槽，接着填入氧化硅。上述步骤可由适当工艺完成，如干蚀刻、湿蚀刻、与化学气相沉积法。此外，在半导体基板16中定义沟道区30。在后续工艺中，沟道区30可作为模拟元件12其他单元的参考区。
接着形成厚度约介于5埃至20埃之间的界面层34A，于含有沟道区30的半导体基板16上。界面层34A为氧化硅，可由化学气相沉积法(CVD)沉积而成。接着以CVD法形成介电常数的介电层38A如HfO2于界面层34A上。介电层38A的沉积厚度约介于10埃至30埃之间。接着以CVD形成阻挡层42A如氮化钽于介电层38A上。阻挡层42A的沉积厚度约介于10埃至200埃之间。
接着以CVD形成虚置栅极层100A于阻挡层42上。在此实施例中，虚置栅极层100A为多晶硅，但也可为多种材料层。接着以CVD形成硬掩模层102A于虚置栅极层100A上。在此实施例中，硬掩模层102A为氮化硅，但也可为氮氧化硅、碳化硅、或其他合适材料。上述层状结构34A、38A、42A、100A、及102A的形成方法可为任何合适工艺如物理气相沉积法(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDCVD)、金属有机CVD(MOCVD)、远端等离子体CVD(RPCVD)、等离子体增强CVD(PECVD)、电镀、其他合适方法、及/或上述的组合。
接着进行光刻工艺移除不在沟道区30上的部分层状结构34A、38A、42A、100A、及102A。进一步来说，先以标准工艺形成光致抗蚀剂层(未图示)于硬掩模层102A上，接着图案化光致抗蚀剂层以保护位于沟道区30上的部分层状结构34A、38A、42A、100A、及102A。接着蚀刻移除部分硬掩模层102A，保留部分硬掩模层102A以保护沟道区30上的层状结构。在剥除残留的光致抗蚀剂层后，进行后续蚀刻步骤以形成暂时的栅极堆叠104如图4所示。暂时的栅极堆叠包含硬掩模层102、虚置栅极层100、阻挡层42、高介电常数的介电层38、及界面层34。光刻图案化工艺可包含多个适当步骤如光致抗蚀剂涂布(例如旋涂法)、软烘烤、光掩模对准、曝光、曝光后烘烤、显影光致抗蚀剂、润湿、干燥(例如硬烘烤)、其他合适步骤、及/或上述的组合。在其他实施例中，光刻的曝光工艺可完全由其他合适方法取代，如无光掩模光刻工艺、电子束直写、或离子束直写。上述蚀刻步骤包含干蚀刻、湿蚀刻、及/或其他蚀刻工艺。必需理解的是，上述实例并非用以限制形成暂时的栅极堆叠的工艺技术。更需要理解的是，暂时的栅极堆叠可包含额外层。
如图5所示，后续工艺包括形成源极区22与漏极区24于半导体基板16中。在特定实施例中，在暂时的栅极堆叠104与绝缘区18之间的半导体基板16中，进行p型掺质的离子注入以形成源极区22与漏极区24。除了离子注入以外，还进行光刻工艺、扩散工艺、及回火工艺(例如快速热回火及/或激光回火)以形成源极区22与漏极区24。在其他实施例中，源极区22与漏极区24可进一步为隆起的源极区/漏极区，其形成方法可为外延工艺如CVD沉积技术(例如气相外延(VPE)及/或超高真空CVD(UHV-CVD)、分子束外延、及/或其他合适工艺。
接着以已知方法沿着暂时的栅极堆叠104的所有侧壁形成侧壁间隔物62，其材质可为介电材料如氮化硅。
接着形成层间介电层66于半导体基板16、侧壁间隔物62、与暂时的栅极堆叠104上。层间介电层66由氧化硅组成。在沉积层间介电层66后，进行化学机械研磨(CMP)直到露出暂时的栅极堆叠104的顶部。在特定实施例中，CMP将露出硬掩模层102如图5所示。
如图6及图7所示，进行栅极置换工艺，将暂时的栅极堆叠104最上面的两层移除并置换为栅极46。如图6所示的特定实施例中，移除暂时的栅极堆叠104中的虚置栅极层100与硬掩模层102。为了进行上述移除步骤，可沉积并图案化光致抗蚀剂层(未图示)。在移除层状结构100与102并剥除光致抗蚀剂层后，阻挡层42与侧壁间隔物62分别定义了开口106的底部与侧部。将硬掩模层102与虚置栅极层100自暂时的栅极堆叠104移除的步骤可为单一或分开的合适步骤，如干蚀刻及/或湿蚀刻。接着如图7所示，形成栅极46于阻挡层42上的开口106中。在特定实施例中，形成栅极46的步骤包含形成功函数层50于阻挡层42上，接着形成金属层51于功函数层50上。在此实施例中，功函数层50是由沉积法形成的氮化钛层，其厚度约介于10埃至200埃之间。金属层51是由沉积法形成的铝层，直到填满开口106。在其他实施例中，栅极可由金属层51单独构成，但需以已知方法将栅极调整至适当的功函数。在形成栅极46后，可进行CMP以平坦化栅极46与层间介电层66的顶部。
如图8所示，再沉积额外的氧化硅层于栅极54与先前沉积的层间介电材料上，以增加层间介电层66的厚度。接着形成源极接点68与漏极接点72穿过层间介电层66，分别接合至源极区22与漏极区24。在特定实施例中，先形成方形开口穿过层间介电层66，露出部分源极区22与漏极区24。接着在方形开口中填入铜。接着在沟道区30上形成栅极接点76，其穿过层间介电层66以接合栅极46。在特定实施例中，先形成矩形开口穿过沟道区30上与栅极46上的层间介电层66，露出部分栅极46。接着在矩形开口中填入铜。上述接点的形成步骤可包含光刻工艺、蚀刻、剥除、沉积、及任何其他适当步骤。最后，进行CMP以平坦化源极接点68、漏极接点72、栅极接点76、与层间介电层66的顶部。
图9为图3-图8的工艺110的高阶流程图。首先，工艺110的步骤112定义沟道区30于半导体基板16中。后续的步骤113形成界面层34A于至少部分沟道区30上。接着在步骤114中，形成高介电常数的介电层38A于界面层34A上。接着在步骤116中，形成阻挡层42A于高介电常数的介电层上与至少部分沟道区上。后续的步骤118沉积虚置栅极层100A于阻挡层42A上。接着在步骤120中，采用光刻工艺形成暂时的栅极堆叠104于沟道区上，其包含部分高介电常数的介电层38、阻挡层42、与虚置栅极层100。此外，层间介电层66形成于半导体基板16与暂时的栅极堆叠104上。后续步骤122与124为栅极置换工艺。在特定实施例中，步骤122移除暂时的栅极堆叠中的虚置栅极层，并形成开口于阻挡层上。接着步骤124将功函数层50与金属层51填入开口，以形成栅极46。此外，增加层间介电层66的厚度。最后进行步骤126，分别形成源极接点68与漏极接点于源极区与漏极区上。此外，形成栅极接点76于沟道区上以接合栅极。
虽然本发明已以多个优选实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种装置，包括一半导体元件，且该半导体元件包括：
一半导体基板，具有一沟道区；
一高介电常数的介电层，位于至少部分该沟道区上；
一栅极，位于至少部分该沟道区上与该介电层上，其中该栅极实质上为金属；以及
一栅极接点，接合该栅极并位于该沟道区上。
2.如权利要求1所述的装置，其中该半导体元件还包括多个其他分开的栅极接点，接合该栅极并位于该沟道区上。
3.如权利要求2所述的装置，
其中该半导体装置包括一源极区与一漏极区于该半导体基板中，且分别位于该沟道区两侧，其中该源极区与该漏极区沿着一第一方向水平相隔；
其中该栅极在该沟道区上沿着一第二方向延伸，且该第一方向与该第二方向大抵垂直；
其中该半导体元件包括多个分开的源极接点接合该源极区，与多个分开的漏极接点接合该漏极区，其中每一源极接点均在第二方向大抵各自对准所述多个漏极接点之一；以及
其中该栅极接点在第二方向与所述多个源极接点及所述多个漏极接点交错。
4.如权利要求3所述的装置，其中该栅极接点的俯视图近似于矩形，且该矩形的长边平行该第二方向。
5.如权利要求1所述的装置，其中所述半导体元件是一模拟元件。
6.一种装置，包括一集成电路，且该集成电路包括：
一半导体基板，具有一绝缘区及分开的第一沟道区与第二沟道区；
一高介电常数的介电层，位于至少部分该第一沟道区上；
一第二介电层，位于至少部分该第二沟道区上与至少部分该绝缘区上；
一第一栅极，位于至少部分该第一沟道区上的该第一介电层上，其中该第一栅极实质上为金属；
一第二栅极，位于该第二介电层上，该第二栅极的第一部分位于该第二沟道区上，且该第二栅极的第二部分位于该绝缘区上；
一第一栅极接点，于该第一沟道区上接合该第一栅极；以及
一第二栅极接点，于该绝缘区上接合该第二栅极，且第二沟道区上不含第二栅极的接合。
7.如权利要求6所述的装置，其中该第一栅极的栅极长度大于该第二栅极的栅极长度；
其中该集成电路具有一模拟元件，且该模拟元件包括该第一沟道区、该第一介电层、与该第一栅极；以及
该集成电路具有一数字元件，且该数字元件包括该第二沟道区、该第二介电层、与该第二栅极。
8.如权利要求6所述的装置，其中该集成电路包含多个其他栅极接点位于该第一沟道区上并接合该第一栅极，且所述多个其他栅极接点彼此分隔；
其中该集成电路包括一源极区与一漏极区于该半导体基板中，且分别位于该第一沟道区两侧，其中该源极区与该漏极区沿着一第一方向隔有一段距离；
其中该第一栅极在该第一沟道区上沿着一第二方向延伸，且该第一方向与该第二方向大抵垂直；
其中该集成电路包括多个分开的源极接点接合该源极区，与多个分开的漏极接点接合该漏极区，其中每一源极接点均在第二方向大抵各自对准所述多个漏极接点之一；以及
其中该第一栅极接点在第二方向与所述多个源极接点及所述多个漏极接点交错。
9.一种形成半导体元件的方法，包括：
提供具有一沟道区的一半导体基板；
形成一高介电常数的介电层于至少部分该沟道区上；
形成一栅极于该介电层与至少部分该沟道区上，且该栅极实质上为金属；以及
形成一栅极接点于该沟道区上并接合该栅极。
10.如权利要求9所述的半导体元件的方法，还包括形成一源极区与一漏极区于该半导体基板中，且该源极区与该漏极区分别位于该沟道区两侧，其中该源极区与该漏极区沿着一第一方向隔有一段距离；
其中形成该栅极的步骤包括使该栅极在该沟道区上沿着一第二方向延伸，且该第一方向与该第二方向大抵垂直；
形成多个分开的源极接点接合该源极区，与形成多个分开的漏极接点接合该漏极区，其中每一源极接点均在第二方向大抵各自对准所述多个漏极接点之一；以及
形成多个分开的其他栅极接点于该沟道区上以接合该栅极，该栅极接点与所述多个其他栅极接点在第二方向与所述多个源极接点及所述多个漏极接点交错。
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