CN102184870B - Umos transistor and forming method thereof - Google Patents
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- CN102184870B CN102184870B CN201110117357.4A CN201110117357A CN102184870B CN 102184870 B CN102184870 B CN 102184870B CN 201110117357 A CN201110117357 A CN 201110117357A CN 102184870 B CN102184870 B CN 102184870B
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Abstract
A kind of UMOS Transistor forming method, described UMOS Transistor forming method forms doped region in dopant well, described doped region is positioned at the bottom in tagma and source region, and across the boundary in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well, thus form potential barrier in tagma and doped region intersection, due to the barrier effect of formed potential barrier, Doped ions in tagma cannot be crossed over described potential barrier and enter channel region, thus avoid because the Doped ions in tagma enters channel region, and the cut-in voltage of transistor is had an impact.Correspondingly, the present invention also provides the UMOS formed by said method transistor.UMOS transistor provided by the present invention and forming method thereof can improve the performance of UMOS transistor.
Description
Technical field
The present invention relates to semiconductor applications, particularly UMOS transistor and forming method thereof.
Background technology
Along with the development of semiconductor technology, power device (PowerDevice), as a kind of new device, is widely used in as the field such as disk drive, automotive electronics.Power device needs to bear larger voltage, electric current and power termination, and such as output rectifier requires to export about 3.3V voltage at input 20V voltage and input 10V voltage and export about 1.5V voltage; And requirement can have the exhaustion voltage of 10V to 50V scope.And the devices such as existing MOS transistor cannot meet the demand, such as the exhaustion voltage range of Schottky diode (Schottkydiodes) is greatly about 0.5V, and therefore, in order to the needs of satisfied application, various power device becomes the focus of concern.
U-shaped trench metal-Oxide-Semiconductor Field effect transistor (UMOS, U-groove-metal-oxide-silicontransistors) be a kind of conventional power device, the direction of its raceway groove is perpendicular to substrate, not only can provide excellent power-performance, with the MOS transistor of routine than the area can also saving about 40%.
Fig. 1 shows the cross-sectional view of UMOS transistor.As shown in Figure 1, comprising: N
+the semiconductor base 10 of doping; Be formed in the epitaxial loayer 11 on semiconductor base 10, described epitaxial loayer 11 is N
-doping; Be formed in the dopant well 12 on described epitaxial loayer 11 surface, described dopant well 12 is the doping of P type; Run through the groove of described dopant well 12; Gate dielectric layer 13, covers bottom and the sidewall of described groove; Gate electrode 14, is formed on described gate dielectric layer 13, fills up described groove; Source region 15 and source region 17, be formed in the dopant well 12 of described groove both sides, adjacent with described gate dielectric layer 13, is N
+doping; Tagma 16 and tagma 18, be formed in described dopant well 12, is P
+doping; The conductive plunger 32 be electrically connected with source region 15, tagma 16; The conductive plunger 31 be electrically connected with source region 17, tagma 18.
2 symmetrical UMOS transistors are included in Fig. 1, concrete, epitaxial loayer 11, dopant well 12, source region 15, gate dielectric layer 13 and gate electrode 14 constitute one of them UMOS transistor, its epitaxial layers 11 is as drain electrode, source region 15 is as source electrode, and the part of dopant well 12 adjacent with gate dielectric layer 13 between epitaxial loayer 11 and source region 15 is as channel region, and tagma 16 is identical with the doping type of dopant well 12, as body electrode, conductive plunger 32 is electrically connected with tagma 16 and source region 15; Epitaxial loayer 11, dopant well 12, source region 17, gate dielectric layer 13 and gate electrode 14 constitute another UMOS transistor, its epitaxial layers 11 is as drain electrode, source region 17 is as source electrode, the part of dopant well 12 adjacent with gate dielectric layer 13 between epitaxial loayer 11 and source region 17 is as channel region, tagma 18 is identical with the doping type of dopant well 12, as body electrode, conductive plunger 31 is electrically connected with tagma 18 and source region 17.Because the shape of epitaxial loayer 11 and gate dielectric layer 13 is " U " shape, therefore called after UMOS transistor.The gate dielectric layer 13 of UMOS transistor and the structures shape of gate electrode 14 its than the MOS transistor of routine, there is higher input impedance, thus can be used as power device.
The formation method of the UMOS transistor of prior art, comprising:
With reference to figure 2, provide semiconductor base 10, described semiconductor base 10 is formed with epitaxial loayer 11, the surface of described epitaxial loayer 11 is formed with dopant well 12, and the doping type of described dopant well 12 and described epitaxial loayer 11 is contrary;
With reference to figure 3, form groove 12a, described groove 12a runs through described dopant well 12, and bottom and sidewall expose described epitaxial loayer 11;
With reference to figure 4, form the gate dielectric layer 13 covering described groove 12a and the gate electrode layer 14 of filling full described shallow trench 12a;
With reference to figure 5, adulterate to described dopant well 12, form source region 15 and source region 17, described source region 15 and source region 17 are positioned at the both sides of gate electrode layer 13, and doping type is contrary with the doping type of dopant well 12;
With reference to figure 6, adulterate to described dopant well 12, form tagma 16 and tagma 18, described tagma 16 is identical with the doping type of described dopant well 12 with the doping type in tagma 18;
With reference to figure 7, form the conductive plunger 32 be electrically connected with source region 15, tagma 16 respectively; The conductive plunger 31 be electrically connected with source region 17, tagma 18.
In the above-mentioned methods, in order to reduce the contact resistance between conductive plunger and dopant well, bottom conductive plunger, form highly doped tagma, but the Doped ions in tagma can spread, these Doped ions are diffused into channel region and can have an impact to the cut-in voltage of UMOS transistor.About more detailed contents of UMOS transistor, please refer to the United States Patent (USP) that the patent No. is 6551881.
Summary of the invention
The problem that embodiments of the invention solve is to provide a kind of UMOS transistor and forming method thereof, has an impact because of the diffusion of tagma Doped ions to avoid to the cut-in voltage of UMOS transistor.
For solving the problem, embodiments of the invention provide a kind of UMOS transistor and forming method thereof, comprising:
There is provided semiconductor base, described semiconductor substrate surface is formed with epitaxial loayer, and the surface of described epitaxial loayer is formed with dopant well, and the doping type of described dopant well and described epitaxial loayer is contrary;
Form groove, described groove runs through described dopant well, and part is positioned at described epitaxial loayer;
Form the gate dielectric layer covering described channel bottom and sidewall and the gate electrode layer of filling full described groove;
In the dopant well of described gate electrode layer both sides, form source region, the doping type in described source region is contrary with dopant well doping type;
In the dopant well of side, described source region, form tagma, described tagma and source region adjoin, and the doping type in described tagma is identical with the doping type of dopant well; Also comprise:
In described dopant well, form doped region, described doped region is positioned at the bottom in tagma and source region, and across the boundary in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well.
Alternatively, described doped region is across the whole boundary in tagma and source region.
Alternatively, also comprise, form conductive plunger, described conductive plunger bottom electrical connects tagma, and sidewall electrical connection is positioned at the source region of gate electrode layer homonymy.
Alternatively, the doping type of described semiconductor base and epitaxial loayer is N-type, and the doping type of described dopant well is P type, and the doping type in described source region is N-type.
Alternatively, the doped chemical in described source region is arsenic.
Alternatively, the material of described gate dielectric layer is silicon dioxide.
Alternatively, the doping type of described doped region is N-type.
Alternatively, the doped chemical of described doped region is arsenic or phosphorus.
Correspondingly, the present invention also provides the UMOS formed by said method transistor, comprises, semiconductor base, described semiconductor substrate surface is formed with epitaxial loayer, and the surface of described epitaxial loayer is formed with dopant well, and the doping type of described dopant well and described epitaxial loayer is contrary;
Groove, described groove runs through described dopant well, and part is positioned at described epitaxial loayer;
Gate dielectric layer, covers bottom and the sidewall of described groove;
Gate electrode, is formed at the surface of described gate dielectric layer and fills up described groove; Source region, be positioned at the dopant well of described gate electrode layer both sides, doping type is contrary with dopant well doping type;
Tagma, is positioned at the dopant well of side, source region, and adjoins with source region, and doping type is identical with dopant well doping type;
Also comprise:
Doped region, described doped region is positioned at described dopant well, and is positioned at the bottom in tagma and source region, and across the interface in tagma and source region, doping type is contrary with the doping type of described dopant well.
Alternatively, the doping type of described semiconductor base and epitaxial loayer is N-type, and the doping type of described dopant well is P type, and the doping type in described source region is N-type.
Compared with prior art, embodiments of the invention have the following advantages:
Embodiments of the invention form doped region in dopant well, described doped region is positioned at the bottom in tagma and source region, and across the interface in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well, thus form potential barrier in tagma and doped region intersection, due to the barrier effect of formed potential barrier, Doped ions in tagma cannot be crossed over described potential barrier and enter channel region, thus avoid because the Doped ions in tagma enters channel region, and the cut-in voltage of transistor is had an impact.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing UMOS transistor;
Fig. 2 to Fig. 7 is the generalized section of the formation method of existing UMOS transistor;
Fig. 8 is the schematic flow sheet of the formation method of the UMOS transistor that embodiments of the invention provide;
Fig. 9 to Figure 14 is the generalized section of the formation method of the UMOS transistor that embodiments of the invention provide.
Embodiment
From background technology, existing UMOS transistor is in order to reduce the contact resistance between conductive plunger and dopant well, highly doped tagma can be formed in dopant well, but the Doped ions in tagma can spread, these Doped ions are diffused into channel region and can have an impact to the cut-in voltage of UMOS transistor.
Inventor studies for the problems referred to above, a kind of UMOS transistor and forming method thereof is provided in an embodiment of the present invention, the UMOS transistor that embodiments of the invention provide forms doped region in dopant well, described doped region is positioned at the bottom in tagma and source region, and across the interface in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well, thus form potential barrier in tagma and doped region intersection, due to the barrier effect of formed potential barrier, Doped ions in tagma cannot be crossed over described potential barrier and enter channel region, thus the Doped ions avoided in tagma enters channel region, can not have an impact to the cut-in voltage of transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
Fig. 8 is the schematic flow sheet of the formation method of the UMOS transistor that embodiments of the invention provide, and comprising:
Step S101, provides semiconductor base, and described semiconductor substrate surface is formed with epitaxial loayer, and the surface of described epitaxial loayer is formed with dopant well, and the doping type of described dopant well and described epitaxial loayer is contrary;
Step S102, form groove, described groove runs through described dopant well, and part is positioned at described epitaxial loayer;
Step S103, forms the gate dielectric layer covering described channel bottom and sidewall and the gate electrode layer of filling full described groove;
Step S104, forms source region in the dopant well of described gate electrode layer both sides, and the doping type in described source region is contrary with dopant well doping type;
Step S105, forms tagma in the dopant well of side, described source region, and described tagma and source region adjoin, and the doping type in described tagma is identical with the doping type of dopant well;
Step S106, forms doped region in described dopant well, and described doped region is positioned at the bottom in tagma and source region, and across the boundary in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well.
Perform step S101, with reference to figure 9, provide semiconductor base 20, described semiconductor base 20 surface is formed with epitaxial loayer 21, and the surface of described epitaxial loayer 21 is formed with dopant well 22, and the doping type of described dopant well 22 and described epitaxial loayer 21 is contrary.
Concrete, semiconductor base 20 is provided, the material of described semiconductor base 20 is semi-conducting material, can be monocrystalline silicon, also can be also can be silicon, germanium, GaAs or silicon Germanium compound, can also be silicon-on-insulator (SOI, SiliconOnInsulator) structure or silicon upper epitaxial layer structure, semiconductor base 20 described in the present embodiment be N
+type adulterates.Described semiconductor base 20 is formed with epitaxial loayer 21, and described epitaxial loayer 21 can adopt epitaxial growth technology to be formed, and in the present embodiment, its doping type is identical with described semiconductor base 20, is specially N-type doping.The surface of described epitaxial loayer 21 is formed with dopant well 22, the doping type of described dopant well 22 is contrary with the doping type of described epitaxial loayer 21, the doping of P type is specially in the present embodiment, its formation method for carry out ion implantation to described epitaxial loayer 21, thus can form dopant well 22 on the surface of epitaxial loayer 21.Those skilled in the art can select the doping content of described epitaxial loayer 21 and dopant well 22 as required.
Perform step S102, with reference to Figure 10, form groove 22a, described groove 22a runs through described dopant well 22, and part is positioned at described epitaxial loayer 21.
The formation method of described groove 22a comprises: form photoresist on the surface of described dopant well 22 and graphically, define the figure of described groove 22a; With described photoetching offset plate figure for mask etches, carve and wear described dopant well 22, and etch a part for described epitaxial loayer 21, make the groove 22a part formed be positioned at described epitaxial loayer 21.In the present embodiment, the degree of depth of described groove 22a is 1.2-1.5 micron.Those skilled in the art can determine concrete etching depth according to the parameter of the UMOS transistor that need prepare.
Perform step S103, with reference to Figure 11, with the gate dielectric layer 24 of sidewall and the gate electrode layer 25 of filling full described groove bottom the described groove 22a of formation covering.
In the present embodiment, the formation method of described gate dielectric layer 24 and gate electrode 25 can comprise: in the bottom of described groove 22a, the surface of sidewall and dopant well 22 forms gate dielectric membrane; Described gate dielectric membrane is formed gate electrode film, described gate electrode film fills up described groove 22a, afterwards, carries out planarization to described gate dielectric membrane and gate electrode film, to the surface exposing described dopant well 22, thus form described gate dielectric layer 24 and gate electrode 25.
In the present embodiment, the material of described gate dielectric layer 24 is silicon dioxide, and the material of described gate electrode layer 25 is polysilicons.
Perform step S104, with reference to Figure 12, in the dopant well 22 of described gate electrode layer 25 both sides, form source region, the doping type in described source region is contrary with dopant well 22 doping type.
Concrete, the doping type in described source region 26 and 27 is contrary with described dopant well 22, is specially N in the present embodiment
+type adulterates.In the present embodiment, the doped chemical in described source region 26 and 27 is arsenic.
Perform step S105, with reference to Figure 13, in the dopant well 22 of side, described source region, form tagma, described tagma and source region adjoin, and the doping type in described tagma is identical with the doping type of dopant well 22.
Particularly, in the present embodiment, described tagma 28 adjoins with source region 26, and described tagma 29 adjoins with source region 27.
In the present embodiment, described tagma 28 is identical with the doping type of dopant well 22 with the doping type of 29, is specially P
+type adulterates, and described heavily doped tagma 28 and 29 can reduce the contact resistance between the conductive plunger of follow-up formation and dopant well 22.But the Doped ions in described heavily doped tagma 28 and 29 easily spreads, described Doped ions diffuses into channel region and can have an impact to the cut-in voltage of formed UMOS transistor.Described dopant well 22 is between epitaxial loayer 21 and source region, and the part adjacent with gate dielectric layer 24 is channel region.
Perform step S106, with reference to Figure 14, in described dopant well 22, form doped region 30 and 40, described doped region 30 and 40 is positioned at the bottom in tagma and source region, across the boundary in tagma and source region, the doping type of described doped region 30 and 40 is contrary with the doping type of dopant well 22.
In the present embodiment, the doping type of described doped region 30 and 40 is N-type, and Doped ions is arsenic or phosphorus.Form the doping process of doped region 30 and 40 for doping of tilting.The dosage of described doping process and energy can set according to the requirement of concrete technology.
Particularly, in this enforcement, described doped region 30 is positioned at the bottom in tagma 29 and source region 27, and across the boundary of tagma 29 with source region 27, described doped region 40 is positioned at the bottom in tagma 28 and source region 26, across the boundary of tagma 28 with source region 26.In optional embodiment of the present invention, described doped region 30 is positioned at the bottom in tagma 29 and source region 27, and across the whole boundary of tagma 29 with source region 27, described doped region 40 is positioned at the bottom in tagma 28 and source region 26, across the whole boundary of tagma 28 with source region 26.Form potential barrier between described doped region 30 and tagma 29, under the barrier effect of described potential barrier, the Doped ions in tagma 29 cannot cross over potential barrier, diffuses into channel region; Similarly, form potential barrier between described doped region 40 and tagma 28, under the barrier effect of described potential barrier, the Doped ions in tagma 28 cannot cross over potential barrier, diffuses into channel region.The cut-in voltage of UMOS transistor is affected in being that of avoiding because the Doped ions in tagma enters channel region.
In optional embodiment of the present invention, also comprise formation conductive plunger, described conductive plunger electrical connection is positioned at tagma and the source region of gate electrode layer 25 homonymy.Particularly, described conductive plunger bottom electrical connects tagma, and sidewall electrical connection is positioned at the source region of gate electrode layer homonymy.
Correspondingly, the present invention also provides and forms UMOS transistor by said method, please refer to Figure 14, and UMOS transistor provided by the present invention, comprising:
Semiconductor base 20, described semiconductor substrate surface is formed with epitaxial loayer 21, and the surface of described epitaxial loayer 21 is formed with dopant well 22, and the doping type of described dopant well 22 and described epitaxial loayer 21 is contrary;
Groove, described groove runs through described dopant well 22, and part is positioned at described epitaxial loayer 21;
Gate dielectric layer 24, covers bottom and the sidewall of described groove;
Gate electrode 25, is formed at the surface of described gate dielectric layer 24 and fills up described groove; Source region 26 and 27, be positioned at the dopant well 22 of described gate electrode layer 25 both sides, doping type is contrary with dopant well 22 doping type;
Tagma 28 and 29, is positioned at the dopant well 22 of side, source region, and adjoins with source region, and doping type is identical with dopant well 22 doping type;
Also comprise:
Doped region 30 and 40, described doped region 30 and 40 is positioned at described dopant well 22, doped region 30 is positioned at the bottom in tagma 29 and source region 27, and across the boundary of tagma 29 with source region 27, doping type is contrary with the doping type of described dopant well 22, doped region 40 is positioned at the bottom in tagma 28 and source region 26, and across the boundary of tagma 28 with source region 26, doping type is contrary with the doping type of described dopant well 22.
Specifically in the present embodiment, the doping type of described semiconductor base 20 and epitaxial loayer 21 is N-type, and the doping type of described dopant well 22 is P type, and the doping type in described source region is N-type.
It should be noted that, what formed in the present embodiment is the UMOS transistor of N-type, and according to actual needs, in above steps, each rete can also adopt contrary doping type, thus forms the UMOS transistor of P type, repeats no more here.
To sum up, embodiments of the invention form doped region in dopant well, described doped region is positioned at the bottom in tagma and source region, and across the boundary in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well, thus form potential barrier in tagma and doped region intersection, due to the barrier effect of formed potential barrier, Doped ions in tagma cannot be crossed over described potential barrier and enter channel region, thus avoid because the Doped ions in tagma enters channel region, and the cut-in voltage of transistor is had an impact.
Although embodiments of the invention with preferred embodiment openly as above, but it is not for limiting embodiments of the invention, any those skilled in the art are not departing from the spirit and scope of embodiments of the invention, the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to embodiments of the invention technical scheme, therefore, every content not departing from embodiments of the invention technical scheme, according to any simple modification that the technical spirit of embodiments of the invention is done above embodiment, equivalent variations and modification, all belong to the protection range of embodiments of the invention technical scheme.
Claims (10)
1. a UMOS Transistor forming method, comprising:
There is provided semiconductor base, described semiconductor substrate surface is formed with epitaxial loayer, and the surface of described epitaxial loayer is formed with dopant well, and the doping type of described dopant well and described epitaxial loayer is contrary;
Form groove, described groove runs through described dopant well, and part is positioned at described epitaxial loayer;
Form the gate dielectric layer covering described channel bottom and sidewall and the gate electrode layer of filling full described groove;
In the dopant well of described gate electrode layer both sides, form source region, the doping type in described source region is contrary with dopant well doping type;
In the dopant well of side, described source region, form tagma, described tagma and source region adjoin, and the doping type in described tagma is identical with the doping type of dopant well; It is characterized in that, also comprise:
Doped region is formed in described dopant well, described doped region is positioned at the bottom in tagma and source region, across the boundary in tagma and source region, the doping type of described doped region is contrary with the doping type of dopant well, and described doped region is for stopping that the Doped ions in described tagma enters channel region.
2. according to UMOS Transistor forming method according to claim 1, it is characterized in that, described doped region is across the whole boundary in tagma and source region.
3. according to UMOS Transistor forming method according to claim 1, it is characterized in that, also comprise, form conductive plunger, described conductive plunger bottom electrical connects tagma, and sidewall electrical connection is positioned at the source region of gate electrode layer homonymy.
4. according to UMOS Transistor forming method according to claim 1, it is characterized in that, the doping type of described semiconductor base and epitaxial loayer is N-type, and the doping type of described dopant well is P type, and the doping type in described source region is N-type.
5. according to UMOS Transistor forming method according to claim 4, it is characterized in that, the doping type of described doped region is N-type.
6. according to UMOS Transistor forming method according to claim 4, it is characterized in that, the doped chemical of described doped region is arsenic or phosphorus.
7. according to UMOS Transistor forming method according to claim 4, it is characterized in that, the doped chemical in described source region is arsenic.
8. according to UMOS Transistor forming method according to claim 1, it is characterized in that, the material of described gate dielectric layer is silicon dioxide.
9. the UMOS transistor that formed of the UMOS Transistor forming method provided according to any one in above-mentioned every claim, comprise, semiconductor base, described semiconductor substrate surface is formed with epitaxial loayer, the surface of described epitaxial loayer is formed with dopant well, and the doping type of described dopant well and described epitaxial loayer is contrary;
Groove, described groove runs through described dopant well, and part is positioned at described epitaxial loayer;
Gate dielectric layer, covers bottom and the sidewall of described groove;
Gate electrode layer, is formed at the surface of described gate dielectric layer and fills up described groove;
Source region, be positioned at the dopant well of described gate electrode layer both sides, doping type is contrary with dopant well doping type;
Tagma, is positioned at the dopant well of side, source region, and adjoins with source region, and doping type is identical with dopant well doping type;
It is characterized in that, also comprise:
Doped region, described doped region is positioned at described dopant well, and is positioned at the bottom in tagma and source region, and across the interface in tagma and source region, doping type is contrary with the doping type of described dopant well, and described doped region is for stopping that the Doped ions in described tagma enters channel region.
10. according to UMOS transistor according to claim 9, it is characterized in that: the doping type of described semiconductor base and epitaxial loayer is N-type, the doping type of described dopant well is P type, and the doping type in described source region is N-type.
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| CN1890813A (en) * | 2003-12-24 | 2007-01-03 | 丰田自动车株式会社 | Trench gate field effect devices |
| CN101138093A (en) * | 2005-06-08 | 2008-03-05 | 夏普株式会社 | Trench type MOSFET and its fabrication process |
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| DE102007020657B4 (en) * | 2007-04-30 | 2012-10-04 | Infineon Technologies Austria Ag | Semiconductor device with a semiconductor body and method for producing the same |
| US8278702B2 (en) * | 2008-09-16 | 2012-10-02 | Fairchild Semiconductor Corporation | High density trench field effect transistor |
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| CN1890813A (en) * | 2003-12-24 | 2007-01-03 | 丰田自动车株式会社 | Trench gate field effect devices |
| CN101138093A (en) * | 2005-06-08 | 2008-03-05 | 夏普株式会社 | Trench type MOSFET and its fabrication process |
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Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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