CN102171803B - 对无铅焊料合金进行掺杂以及由此形成的结构 - Google Patents
对无铅焊料合金进行掺杂以及由此形成的结构 Download PDFInfo
- Publication number
- CN102171803B CN102171803B CN200980139227.1A CN200980139227A CN102171803B CN 102171803 B CN102171803 B CN 102171803B CN 200980139227 A CN200980139227 A CN 200980139227A CN 102171803 B CN102171803 B CN 102171803B
- Authority
- CN
- China
- Prior art keywords
- nickel
- interconnection
- lead
- solder
- welding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 40
- 239000000956 alloy Substances 0.000 title description 10
- 229910045601 alloy Inorganic materials 0.000 title description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 108
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000004377 microelectronic Methods 0.000 claims abstract description 11
- 238000003466 welding Methods 0.000 claims description 60
- 229910000765 intermetallic Inorganic materials 0.000 claims description 23
- 238000004806 packaging method and process Methods 0.000 claims description 13
- 229910018082 Cu3Sn Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000010992 reflux Methods 0.000 claims description 8
- 229910007637 SnAg Inorganic materials 0.000 claims description 5
- 229910008433 SnCU Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 2
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 claims 1
- 229910052720 vanadium Inorganic materials 0.000 claims 1
- 238000003860 storage Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 230000036039 immunity Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000168096 Glareolidae Species 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- -1 SnAgCu Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000007115 recruitment Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/3033—Ni as the principal constituent
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
- C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明描述了形成微电子结构的方法。这些方法包括用镍对无铅焊接材料进行掺杂,其中镍构成焊接材料的最大为大约0.2重量%,并且然后将焊接材料施加至包括铜焊盘的基板。
Description
背景技术
随着用于更高器件性能的微电子封装技术的进步,焊料接合的可靠性正成为重要的关注点。在某些情况下可能涉及到焊料互连接合部(即,互连结构和另一表面之间的界面,另一表面例如为一基板或接触焊盘)的故障的封装可靠性的问题,已经在很多类型的封装组件中被观察到,例如在球栅阵列(BGA)组件中。
附图说明
虽然本说明书以权利要求特别指出并且清楚地要求保护本发明的某些实施例作为结束,但结合附图从本发明的以下的描述中能够更加容易地确定本发明的优点,其中:
图1a-1c示出根据本发明的实施例形成结构的方法。
图2示出根据本发明实施例的结构。
图3示出根据本发明实施例的流程图。
图4示出根据本发明实施例的系统。
图5示出现有技术的一个结构。
具体实施方式
在以下的详细描述中,通过举例说明引用示出了可以实施本发明的特定实施例的附图。这些实施例被描述的充分详细,以使本领域技术人员能够实施本发明。应该理解,本发明的各种各样的实施例,虽然不同,但未必是互相排斥的。例如,在此描述的与一个实施例相关的一个特定特征、结构或特性可以在不脱离本发明的精神和范围的情况下在其他实施例中实施。此外,应该理解,在不脱离本发明的精神和范围的情况下,可以对每个公开的实施例中的单独元件的位置或布置进行修改。因此,以下详细的描述不应理解为是限制性的,并且本发明的范围仅通过适当解释的所附的权利要求以及权利要求享有权利的全部等价物来限定。在附图中,相同的参考标记在多个视图中指代相同或相似的功能件。
描述了形成微电子结构的方法以及与其相关的结构,例如接合部结构。这些方法可以包括使用镍对无铅焊接材料进行掺杂,其中镍构成(comprise)焊接材料的最高大约0.2重量%,并且然后将焊接材料应用到包括铜焊盘的基板。本发明的方法可以极大地提高微电子封装中的焊料接合部的强度和电迁移耐力。
图1a-1c示出形成微电子结构,例如封装和接合部结构的方法的实施例。图1a示出了基板100的一部分。例如,该基板100可包括受控熔塌芯片连接(C4)结构的一部分。该基板100可进一步包括一器件部分102。该器件部分102可包括可形成集成电路的例如晶体管、电阻器或导体的器件。在另一个实施例中,该器件部分102可包括在单个管芯上一起形成多个微处理器核的器件。
在一个实施例中,该基板100的器件部分102可进一步包括例如但不限制于硅、绝缘体上硅、锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓或其组合的材料。
器件部分102可进一步包括可为器件部分102的各器件提供电互连的互连区域(未示出)。该互连区域可包括金属化层的叠层,该金属化层的叠层可包括可通过介电材料分隔和/或绝缘的金属线。
基板100可包括球限制金属化(BLM)106以及钝化材料108。该BLM106可设置于键合焊盘104上。在一个实施例中,该BLM106可包括一多层BLM,例如但不限制于包括钛/铝/钛/镍钒的叠层,其中底层的钛可设置于键合焊盘104上。在一个实施例中,该键合焊盘104可包括铜键合焊盘104。
焊接材料110可形成在/施加至该基板100的BLM以及因此键合焊盘106上。该焊接材料110可包括一无铅焊接材料110,并且可为SnAg、SnAgCu、SnCu以及其他这样的无铅焊料合成物。在一实施例中,该焊接材料110可包括/掺杂有镍。在一实施例中,镍可构成焊接材料110的1-2ppm至大约0.2重量%。对焊接材料110的镍掺杂可用来抑制在随后的处理过程中可能发生在焊料/铜界面的金属间的生长,并且因此提高了使用根据本发明的实施例的焊接材料110的器件的这种铜/焊料界面处的电迁移耐力。
例如,在无铅焊料合金材料中掺杂镍阻碍了第二级互连BGA结构中的Cu3Sn金属间生长。例如,此IMC的减少用来提高焊接材料110在与铜表面,例如与封装基板铜表面和/或管芯焊盘铜表面结合时的可靠性。
例如,焊接材料110中的锡与镍掺杂剂的强的化学亲和力与可越过焊料接合部发生的镍浓度梯度一起,将驱使镍在铜/焊料界面反应并分离。
该掺杂的焊接材料110可进一步被暴露至一回流工艺112(图1c)。在一个实施例中,该回流工艺112可包括一大约270摄氏度以下的温度,例如,可包括用于焊接材料110的回流温度。该回流温度参数可根据在焊料/铜界面所采用的具体回流工艺而变化。在经历了回流工艺112后,该掺杂的焊接材料110可形成一镍掺杂互连结构/焊球114。
图2描述了根据一实施例的微电子封装结构200。该封装结构200包括封装基板216,以及管芯202(与图1a中的管芯102相似),其中多个接合部结构207被设置并且连接/电耦合在管芯202和封装基板214之间。在一个实施例中,封装基板216可包括至少一个母板,印刷电路板(PCB)、插入结构、试验板以及平面栅格阵列插槽。
仍参考图2,该接合部结构207包括设置于管芯202上的BLM(与图1a中的BLM106相似)206,以及设置于封装基板216上的封装基板表面终饰215。在一实施例中,该表面终饰215可包括这样的表面终饰,例如本领域所公知的ENIG、ENIG-EG、NiPdAu表面终饰。众所周知的,位于管芯202上的BLM206以及该表面终饰215允许管芯202和封装基板216分别与外部电路电键合。键合焊盘204,例如铜键合焊盘204可设置于管芯202上、BLM206和管芯202之间。
进一步如图2所示,接合部结构207进一步包括将管芯202和封装基板216互相键合的互连结构214。与图1c中的互连结构114相似的该互连结构214可包括具有镍掺杂的无铅焊接材料。在一实施例中,互连结构214可包括C4互连结构。在一实施例中,互连结构214可包括介于大约1-2ppm以及互连结构214的大约0.2重量%之间的镍。例如,在一个实施例中,镍可贯穿每个互连结构214基本上均匀地分布,并且可具有足以减少铜锡金属间化合物(IMC)的形成的量,铜锡金属间化合物例如为Cu3Sn以及Cu5Sn6金属间化合物。在一个实施例中,Cu5Sn6 IMC的厚度可包括小于大约5微米的厚度。
在一实施例中,通过掺杂翻4倍的镍可降低IMC(包括包含锡和铜Cu的化合物的IMC)的生长。添加至焊接材料的有效镍量可根据具体应用而被最优化。现有技术的不包括本发明的各个实施例中的镍掺杂互连结构的封装结构,可包括形成在铜/焊料界面的增加量/密度的IMC(图5)。
例如,现有技术的封装结构的现有技术的焊料/铜界面可包括Cu3Sn 502内层IMC以及Cu5Sn6 504外层IMC,其中内层IMC是多孔的,具有由在例如回流和/或烘烤处理过程中可发生的不平衡的铜和锡扩散引起的柯肯特尔孔隙(Kirkendallvoid)506。过量的电迁移失效可因铜/焊料界面的这种IMC的形成而发生,并且可极大地降低组装成品率。
然而,本发明的多个实施例中的包括焊接材料的互连结构阻止了铜锡IMC,例如Cu3Sn IMC和Cu5Sn6 IMC的生长率,并且通过该方法使得基于锡的无铅焊料接合部的电迁移失效降低。在一实施例中,在回流处理后,根据本发明的实施例形成在掺杂镍的无铅焊料合金中的Cu5Sn6 IMC的颗粒尺寸可包括大约5微米。相反,在回流处理后,现有技术中形成在未掺杂镍的无铅焊料合金中的Cu5Sn6IMC可包括大约20微米的颗粒尺寸。因此,掺杂镍的无铅焊料合金包括比无镍掺杂的无铅焊料合金所具有的正常(courser)的颗粒尺寸更精细的颗粒尺寸。此外,通过减少IMC的形成和尺寸导致的孔隙的减少以及改善的铜/焊料界面增加了整体强度、优化了凸块的形态并且提高了整体BLM可靠性和管芯产率。
参考图3,其示出了根据一实施例的掺杂焊接材料的工艺的流程图。在步骤302中,用镍对无铅焊接材料进行掺杂,其中镍构成焊接材料的最大为大约0.2重量%。例如,在一个实施例中,掺杂可通过传统的焊料合金过程实现,例如通过混合根据指定合成物的纯的相应金属元素,并且然后加热混合物以将其熔化,不断地搅动以确保合金分布的均匀性。在冷却后,例如在无铅焊料合金的液相线以下的温度下实现均质化过程。
在步骤304中,该掺杂的无铅焊接材料可被应用于包括铜焊盘的基板。在一实施例中,如本领域技术人员所公认的,这样制备的掺杂的焊接材料用于传统的C4凸块形成和键合工艺中。虽然以上描述了用于形成镍掺杂无铅焊料的方法实施例,但是以任何形式,例如以微焊球形式制备掺杂的无铅焊料合成物的实施例包括在它们的范围内。
例如,图4是示出了能够利用本发明的微电子结构(例如包括图2的互连结构216的接合部结构207)操作的典型系统400的示图。应当理解,本实施例仅仅是其中可以使用本发明的导电互联结构的许多可能的系统中的一个。
在系统400中,该接合部结构424可通过I/O总线408通信地耦合至印刷电路板(PCB)418。该接合部结构424的通信的耦合可通过物理的方式实现,例如通过使用封装和/或插槽连接来将接合部结构424安装到PCB 418(例如通过使用芯片封装、插入结构和/或平面栅格阵列插槽)。该接合部结构424也可通过各种本领域公知的无线手段(例如不使用与PCB的物理连接)通信地耦合到PCB 418。
该系统400可包括计算装置402,例如处理器和通过处理器总线405相互通信地耦合的高速缓冲存储器404。处理器总线405和I/O总线408可通过主桥406桥接。主存储器412可通信地耦合至I/O总线408以及接合部结构424。主存储器412的例子可包括但不限于静态随机存取存储器(SRAM)和/或动态随机存取存储器(DRAM),和/或一些其他形态的保存介质。系统400也可包括图形协处理器413,然而在系统400中结合该图形协处理器413对于该系统400的操作而言不是必需的。例如,耦合至I/O总线408的也可以是显示装置414、大容量存储装置420以及键盘和指向装置422。
这些元件执行它们本领域公知的传统功能。具体地,大容量存储器420可被用于为用于根据本发明的实施例形成接合部结构的方法的可执行指令提供长期的存储,而主存储器412可被用于在通过计算装置402执行期间,短期存储用于根据本发明的实施例形成接合部结构的方法的可执行指令。此外,例如,该指令可被存储在,或者与通信地耦合至系统的机器可存取介质相关联,例如压缩盘只读存储器(CD-ROM)、数字多功能盘(DVD)以及软盘、载波和/或其他的传播信号。在一个实施例中,主存储器412可向计算装置202(例如,其可为处理器)提供用于执行的可执行指令。
本发明的益处包括降低了因焊料接合部故障引起的组装成品率损失。将镍掺杂至无铅焊料BGA合金中抑制了Cu3Sn内层和Cu5Sn6外层两者的生长,因此导致了BGA焊料接合部界面强度的提高。归因于镍掺杂的界面IMC生长的抑制能帮助延长第一级互连(FLI)焊料接合部的电迁移的寿命。
本发明实施例使得能够结合包括缩短的管芯铜凸块以及增加的焊料凸块高度的短粗的焊料凸块。关键的思想是增加用于这样的焊料接合部几何形状的适应性(compliant)C4焊料体积且降低用于这样的焊料接合部几何形状的硬铜凸块体积,以促进管芯ILD应力的吸收。此外,通过降低在铜/焊料界面的IMC的生长而加强了该电迁移耐力的新FLI几何形状设计规则。根据本发明实施例的镍掺杂的无铅焊料BGA合金实现了用于下一代封装结构的管芯至封装的集成方案,因此允许越来越易碎的管芯ILD构架的组装和集成。
虽然以上的描述具体说明了能够用于本发明的方法的特定步骤以及材料,但是本领域技术人员应理解,可以进行许多的修改和替换。因此,意图是使所有的这种修改、变化、替换以及增加均被视为落入所附权利要求所限定的本发明的精神和范围之内。此外,应理解各种微电子结构,例如接合部和封装结构是本领域公知的。因此,此处提供的附图仅示出了涉及本发明的实施的典型的微电子装置的一部分。因此本发明不限于此处描述的结构。
Claims (25)
1.一种用于对无铅焊接材料进行掺杂的方法,包括:
仅使用镍对所述无铅焊接材料进行掺杂;以及
将镍掺杂的无铅焊接材料施加至基板的铜焊盘,
其中镍掺杂包括介于0.1ppm至2ppm之间的重量百分比,
其中所述无铅焊接材料是SnAg、SnAgCu或SnCu。
2.根据权利要求1所述的方法,进一步包括:减少锡和铜之间的IMC的形成,并且其中所述IMC包括Cu3Sn和Cu5Sn6中的至少一种。
3.根据权利要求1所述的方法,进一步包括对所述焊接材料进行回流,以形成镍掺杂的互连结构。
4.根据权利要求3所述的方法,其中所述互连结构包括焊料接合部结构的一部分。
5.根据权利要求3所述的方法,其中降低所述互连结构中的电迁移失效。
6.根据权利要求1所述的方法,其中所述基板包括微电子器件的一部分,并且其中所述微电子器件进一步附接至封装基板。
7.一种用于对无铅焊接材料进行掺杂的方法,包括:
仅使用镍对所述无铅焊接材料进行掺杂;
将掺杂的无铅焊接材料施加至基板的键合焊盘部分;
对掺杂的无铅焊接材料进行回流,以形成焊料互连结构,
其中镍掺杂包括介于0.1ppm至2ppm之间的重量百分比,并且
其中所述无铅焊接材料是SnAg、SnAgCu或SnCu。
8.根据权利要求7所述的方法,其中所述键合焊盘部分进一步包括BLM,该BLM包括镍、钒和钛中的至少一种。
9.根据权利要求7所述的方法,其中所述焊料互连结构包括接合部结构的一部分。
10.根据权利要求9所述的方法,进一步包括:减少所述接合部结构中的金属间化合物的形成。
11.根据权利要求10所述的方法,其中所述金属间化合物包括Cu3Sn和Cu5Sn6中的至少一种。
12.一种镍掺杂的互连结构,包括:
设置于基板上的键合焊盘;以及
设置于所述键合焊盘上的无铅焊料互连,所述无铅焊料互连包括仅使用镍掺杂的无铅焊接材料,
其中所述无铅焊料互连包括介于0.1ppm至2ppm之间的重量百分比的镍,并且
其中仅使用镍掺杂的所述无铅焊接材料是仅使用镍掺杂的SnAg、仅使用镍掺杂的SnCu或仅使用镍掺杂的SnAgCu。
13.根据权利要求12所述的镍掺杂的互连结构,其中所述键合焊盘包括铜,并且进一步包括BLM。
14.根据权利要求12所述的镍掺杂的互连结构,其中所述无铅焊料互连包括短粗的焊料接合部结构的一部分。
15.根据权利要求12所述的镍掺杂的互连结构,其中所述无铅焊料互连包括FLI的一部分。
16.根据权利要求12所述的镍掺杂的互连结构,其中所述基板包括微电子器件的一部分,并且其中所述无铅焊料互连包括焊料接合部的一部分。
17.根据权利要求12所述的镍掺杂的互连结构,其中形成在所述无铅焊料互连中的铜锡金属间化合物包括精细的颗粒尺寸。
18.一种镍掺杂的互连结构,包括:
设置于器件基板上的键合焊盘;
设置在所述键合焊盘上的至少一个无铅焊料互连,所述无铅焊料互连包括仅使用镍掺杂的无铅焊接材料,其中所述至少一个无铅焊料互连包括介于0.1ppm至2ppm之间的重量百分比的镍;以及
附接至所述至少一个无铅焊料互连的封装基板,并且
其中所述无铅焊接材料是SnAg、SnAgCu或SnCu。
19.根据权利要求18所述的镍掺杂的互连结构,其中所述封装基板包括BGA封装的一部分。
20.根据权利要求18所述的镍掺杂的互连结构,其中所述无铅焊料互连包括焊料接合部结构的一部分。
21.根据权利要求20所述的镍掺杂的互连结构,其中设置在所述焊料接合部结构的铜-焊料界面的IMC包括小于5微米的厚度。
22.根据权利要求20所述的镍掺杂的互连结构,其中所述焊料接合部结构在铜锡界面上基本上无孔隙。
23.根据权利要求21所述的镍掺杂的互连结构,其中所述IMC包括Cu3Sn和Cu5Sn6中的至少一种。
24.根据权利要求18所述的镍掺杂的互连结构,进一步包括一系统,其中总线通信地耦合到所述结构,并且
DRAM通信地耦合到所述总线。
25.根据权利要求23所述的镍掺杂的互连结构,其中附接至所述封装基板的所述至少一个无铅焊料互连包括第一级互连的一部分。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/317,598 | 2008-12-23 | ||
US12/317,598 US8395051B2 (en) | 2008-12-23 | 2008-12-23 | Doping of lead-free solder alloys and structures formed thereby |
PCT/US2009/067113 WO2010074956A2 (en) | 2008-12-23 | 2009-12-08 | Doping of lead-free solder alloys and structures formed thereby |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102171803A CN102171803A (zh) | 2011-08-31 |
CN102171803B true CN102171803B (zh) | 2015-03-18 |
Family
ID=42264408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200980139227.1A Active CN102171803B (zh) | 2008-12-23 | 2009-12-08 | 对无铅焊料合金进行掺杂以及由此形成的结构 |
Country Status (11)
Country | Link |
---|---|
US (1) | US8395051B2 (zh) |
JP (1) | JP2012510184A (zh) |
KR (1) | KR20110063813A (zh) |
CN (1) | CN102171803B (zh) |
BR (1) | BRPI0923647A2 (zh) |
DE (1) | DE112009004935T5 (zh) |
GB (1) | GB2478892B (zh) |
RU (1) | RU2492547C2 (zh) |
SG (1) | SG172368A1 (zh) |
TW (1) | TWI515809B (zh) |
WO (1) | WO2010074956A2 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8395051B2 (en) | 2008-12-23 | 2013-03-12 | Intel Corporation | Doping of lead-free solder alloys and structures formed thereby |
US8013444B2 (en) | 2008-12-24 | 2011-09-06 | Intel Corporation | Solder joints with enhanced electromigration resistance |
US9620469B2 (en) | 2013-11-18 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming post-passivation interconnect structure |
US9916763B2 (en) | 2010-06-30 | 2018-03-13 | Primal Space Systems, Inc. | Visibility event navigation method and system |
US8227334B2 (en) * | 2010-07-26 | 2012-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping minor elements into metal bumps |
US8127979B1 (en) | 2010-09-25 | 2012-03-06 | Intel Corporation | Electrolytic depositon and via filling in coreless substrate processing |
US8698308B2 (en) * | 2012-01-31 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structural designs to minimize package defects |
US20130249066A1 (en) | 2012-03-23 | 2013-09-26 | International Business Machines Corporation | Electromigration-resistant lead-free solder interconnect structures |
JP5893528B2 (ja) * | 2012-07-27 | 2016-03-23 | 新日鉄住金マテリアルズ株式会社 | 無鉛はんだバンプ接合構造 |
US9394619B2 (en) * | 2013-03-12 | 2016-07-19 | Intel Corporation | Methods of adding dopants to conductive interconnect structures in substrate technologies and structures formed thereby |
CN104716056B (zh) * | 2013-12-17 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | 一种晶圆键合方法 |
US9396991B2 (en) | 2014-08-25 | 2016-07-19 | Globalfoundries Inc. | Multilayered contact structure having nickel, copper, and nickel-iron layers |
TWI688447B (zh) * | 2015-04-03 | 2020-03-21 | 美商英特爾公司 | 半導體裝置及形成焊料互連體之方法 |
US20190067176A1 (en) * | 2016-03-22 | 2019-02-28 | Intel Corporation | Void reduction in solder joints using off-eutectic solder |
WO2023070551A1 (zh) * | 2021-10-29 | 2023-05-04 | 京东方科技集团股份有限公司 | 发光器件、发光模组及其制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6231691B1 (en) * | 1997-02-10 | 2001-05-15 | Iowa State University Research Foundation, Inc. | Lead-free solder |
US6610595B2 (en) * | 2000-06-30 | 2003-08-26 | Intel Corporation | Ball limiting metallurgy for input/outputs and methods of fabrication |
TW200740549A (en) * | 2006-03-09 | 2007-11-01 | Nippon Steel Materials Co Ltd | Lead-free solder alloy, solder ball and electronic member, and lead-free solder alloy, solder ball and electronic member for automobile-mounted electronic member |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09172019A (ja) * | 1995-12-19 | 1997-06-30 | Hitachi Ltd | 下地電極の形成方法 |
JP2000197988A (ja) * | 1998-03-26 | 2000-07-18 | Nihon Superior Co Ltd | 無鉛はんだ合金 |
US6139979A (en) * | 1999-01-28 | 2000-10-31 | Murata Manufacturing Co., Ltd. | Lead-free solder and soldered article |
CN1240515C (zh) * | 2001-02-27 | 2006-02-08 | 日商·胜美达股份有限公司 | 无铅焊锡合金及使用该合金的电子部件 |
DE10147378A1 (de) * | 2001-09-26 | 2003-02-20 | Infineon Technologies Ag | Bleifreies Weichlot, insbesondere Elektroniklot |
EP1453636B1 (de) * | 2001-12-15 | 2006-08-02 | Pfarr Stanztechnik Gmbh | Bleifreies weichlot |
JP2004017093A (ja) * | 2002-06-17 | 2004-01-22 | Toshiba Corp | 鉛フリーはんだ合金、及びこれを用いた鉛フリーはんだペースト |
US6995084B2 (en) * | 2004-03-17 | 2006-02-07 | International Business Machines Corporation | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching |
US7325716B2 (en) * | 2004-08-24 | 2008-02-05 | Intel Corporation | Dense intermetallic compound layer |
RU2278444C1 (ru) * | 2005-01-11 | 2006-06-20 | Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" | Способ бессвинцовистой пайки полупроводникового кристалла к корпусу |
WO2006122240A2 (en) * | 2005-05-11 | 2006-11-16 | American Iron & Metal Company, Inc. | Tin alloy solder compositions |
US7314819B2 (en) | 2005-06-30 | 2008-01-01 | Intel Corporation | Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same |
JP2006100844A (ja) * | 2005-11-02 | 2006-04-13 | Fujitsu Ltd | バンプ電極付き電子部品 |
US7765691B2 (en) * | 2005-12-28 | 2010-08-03 | Intel Corporation | Method and apparatus for a printed circuit board using laser assisted metallization and patterning of a substrate |
US20070172381A1 (en) * | 2006-01-23 | 2007-07-26 | Deram Brian T | Lead-free solder with low copper dissolution |
JP5030442B2 (ja) | 2006-03-09 | 2012-09-19 | 新日鉄マテリアルズ株式会社 | 鉛フリーハンダ合金、ハンダボール及び電子部材 |
JP4722751B2 (ja) | 2006-03-31 | 2011-07-13 | 富士電機株式会社 | 粉末はんだ材料および接合材料 |
JP5023583B2 (ja) * | 2006-07-07 | 2012-09-12 | 富士電機株式会社 | ソルダーペースト組成物及びそれを用いたプリント配線基板への電子部品実装方法 |
JP4146509B1 (ja) * | 2008-03-27 | 2008-09-10 | 俊道 西澤 | 射出成形機及びそれを用いた射出成形方法 |
US8395051B2 (en) | 2008-12-23 | 2013-03-12 | Intel Corporation | Doping of lead-free solder alloys and structures formed thereby |
-
2008
- 2008-12-23 US US12/317,598 patent/US8395051B2/en active Active
-
2009
- 2009-12-08 DE DE112009004935T patent/DE112009004935T5/de active Pending
- 2009-12-08 SG SG2011046422A patent/SG172368A1/en unknown
- 2009-12-08 JP JP2011538737A patent/JP2012510184A/ja active Pending
- 2009-12-08 BR BRPI0923647A patent/BRPI0923647A2/pt active Search and Examination
- 2009-12-08 CN CN200980139227.1A patent/CN102171803B/zh active Active
- 2009-12-08 GB GB1112621.6A patent/GB2478892B/en active Active
- 2009-12-08 RU RU2011130867/28A patent/RU2492547C2/ru not_active IP Right Cessation
- 2009-12-08 WO PCT/US2009/067113 patent/WO2010074956A2/en active Application Filing
- 2009-12-08 KR KR1020117007723A patent/KR20110063813A/ko not_active Application Discontinuation
- 2009-12-10 TW TW098142293A patent/TWI515809B/zh active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6231691B1 (en) * | 1997-02-10 | 2001-05-15 | Iowa State University Research Foundation, Inc. | Lead-free solder |
US6610595B2 (en) * | 2000-06-30 | 2003-08-26 | Intel Corporation | Ball limiting metallurgy for input/outputs and methods of fabrication |
TW200740549A (en) * | 2006-03-09 | 2007-11-01 | Nippon Steel Materials Co Ltd | Lead-free solder alloy, solder ball and electronic member, and lead-free solder alloy, solder ball and electronic member for automobile-mounted electronic member |
Also Published As
Publication number | Publication date |
---|---|
GB201112621D0 (en) | 2011-09-07 |
TW201039395A (en) | 2010-11-01 |
DE112009004935T5 (de) | 2012-12-27 |
SG172368A1 (en) | 2011-07-28 |
GB2478892A (en) | 2011-09-21 |
BRPI0923647A2 (pt) | 2016-01-19 |
RU2011130867A (ru) | 2013-01-27 |
RU2492547C2 (ru) | 2013-09-10 |
WO2010074956A2 (en) | 2010-07-01 |
US20100155115A1 (en) | 2010-06-24 |
GB2478892B (en) | 2013-07-31 |
KR20110063813A (ko) | 2011-06-14 |
JP2012510184A (ja) | 2012-04-26 |
TWI515809B (zh) | 2016-01-01 |
CN102171803A (zh) | 2011-08-31 |
US8395051B2 (en) | 2013-03-12 |
WO2010074956A3 (en) | 2010-08-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102171803B (zh) | 对无铅焊料合金进行掺杂以及由此形成的结构 | |
EP1897137B1 (en) | Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages | |
US7939939B1 (en) | Stable gold bump solder connections | |
US8101514B2 (en) | Semiconductor device having elastic solder bump to prevent disconnection | |
EP1755820B1 (en) | Composition of a solder, and method of manufacturing a solder connection | |
JPH1174415A (ja) | 電子モジュールの相互接続を形成する方法 | |
KR20150069492A (ko) | 반도체 구조 및 그 제조 방법 | |
US9679875B2 (en) | Reduced volume interconnect for three-dimensional chip stack | |
US8461695B2 (en) | Grain refinement by precipitate formation in Pb-free alloys of tin | |
JP2018093001A (ja) | 電子装置及び電子装置の製造方法 | |
JP3700598B2 (ja) | 半導体チップ及び半導体装置、回路基板並びに電子機器 | |
US20110281136A1 (en) | Copper-manganese bonding structure for electronic packages | |
US20190393186A1 (en) | Semiconductor structure and manufacturing method for the same | |
US11239190B2 (en) | Solder-metal-solder stack for electronic interconnect | |
JP2004289135A (ja) | 金バンプ構造およびその製造方法 | |
CN115136300A (zh) | 电子设备、芯片封装结构及其制作方法 | |
KR20070027485A (ko) | 전기적 상호접속부용 도핑된 합금 및 이들의 제조 방법 | |
JP2001332641A (ja) | 半導体装置の製造方法および半導体装置 | |
TW202142338A (zh) | 焊料、基板組件及其裝配方法 | |
CN117546285A (zh) | 用于细间距异构应用的第一级互连凸块下金属化部 | |
Orii et al. | Microstructure observation of electromigration behavior in peripheral C2 flip chip interconnection with solder capped Cu pillar Bump |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |