CN102169863B - 窗口球栅阵列半导体封装体 - Google Patents

窗口球栅阵列半导体封装体 Download PDF

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Publication number
CN102169863B
CN102169863B CN201010606152.8A CN201010606152A CN102169863B CN 102169863 B CN102169863 B CN 102169863B CN 201010606152 A CN201010606152 A CN 201010606152A CN 102169863 B CN102169863 B CN 102169863B
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substrate
semiconductor die
electrically insulated
package body
insulated structures
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CN102169863A (zh
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S·苏塔德雅
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Abstract

本公开的实施例提供窗口球栅阵列半导体封装体。半导体封装体包括基底，该基底具有(i)第一表面、(ii)与第一表面相对的第二表面以及(iii)形成在基底的第一表面与基底的第二表面之间的开口。该半导体封装体还包括：半导体裸片，其具有(i)第一表面以及(ii)与第一表面相对的第二表面，半导体裸片的第一表面通过一个或多个互连凸块电耦合到基底的第二表面；一根或多根键合线，其通过基底的开口将半导体裸片的第一表面与基底的第一表面电耦合；以及第一电绝缘结构，其布置成实质上填充在半导体裸片的第一表面、基底的第二表面和一个或多个互连凸块之间的区域。该第一电绝缘结构实质上包封一根或多根键合线并且实质上填充基底的开口。

Description

窗口球栅阵列半导体封装体
相关申请的交叉引用
本公开要求2009年12月23日提交的申请号为61/289,943的美国临时专利申请以及2010年4月8日提交的申请号为No.61/322,262的美国临时专利申请的优先权，为了所有目的，除了与本说明书不一致的那些部分(如果有的话)之外，在此通过参考整体引入其全部说明书。
技术领域
本公开的实施例涉及集成电路领域，并且更具体地涉及用于窗口球栅阵列(BGA)半导体封装体的封装技术、结构和配置。
背景技术
在此提供的背景技术的描述是用于一般性地呈现本公开的背景环境的目的。既不明确地也不隐含地承认，当前所称发明人的工作(就本背景技术部分所描述的程度而言)、以及说明书中无法被另外证明是在提交时的现有技术的各方面，是与本公开相对照的现有技术。
当前，窗口BGA封装是通过使用粘合剂直接将半导体裸片附着到基底上形成，而不使用例如互连凸块或类似结构。然而，这种常规的封装可能无法提供足够小的半导体封装体来适应诸如电话、计算机或使用半导体裸片的其它电子装配之类的新兴电子设备的逐渐缩小的形状系数。
发明内容
在一个实施例中，一种半导体封装体包括基底，该基底具有(i)第一表面、(ii)与第一表面相对的第二表面以及(iii)形成在基底的第一表面与基底的第二表面之间的开口。该半导体封装体还包括：半导体裸片，其具有(i)第一表面以及(ii)与第一表面相对的第二表面，半导体裸片的第一表面通过一个或多个互连凸块电耦合到基底的第二表面；一根或多根键合线，其通过基底的开口将半导体裸片的第一表面电耦合到基底的第一表面；以及第一电绝缘结构，其布置成实质上填充在半导体裸片的第一表面、基底的第二表面和一个或多个互连凸块之间的区域。该第一电绝缘结构实质上包封一根或多根键合线并且实质上填充基底的开口。
在另一实施例中，一种方法包括：提供基底，该基底具有(i)第一表面、(ii)与第一表面相对的第二表面以及(iii)形成在基底的第一表面与基底的第二表面之间的开口；将半导体裸片电耦合到基底以形成半导体封装体，该半导体裸片具有(i)第一表面以及(ii)与第一表面相对的第二表面，该半导体裸片的第一表面通过一个或多个互连凸块电耦合到基底的第二表面；形成一根或多根键合线，以通过基底的开口将半导体裸片的第一表面电耦合到基底的第一表面；以及形成电绝缘结构，使得实质上填充在半导体裸片的第一表面、基底的第二表面和一个或多个互连凸块之间的区域，其中该电绝缘结构实质上包封一根或多根键合线并且实质上填充基底的开口。
附图说明
结合附图，通过以下详细描述将容易理解本公开的实施例。为了便于本描述，相同的附图标记指代相同的结构元件。在附图中通过示例的方式而不是限制的方式示出这里的实施例。
图1示意性地示出根据各种实施例的第一半导体封装体。
图2示意性地示出根据各种实施例的第二半导体封装体。
图3示意性地示出根据各种实施例的第三半导体封装体。
图4示意性地示出根据各种实施例的第四半导体封装体。
图5示意性地示出根据各种实施例的第五半导体封装体。
图6示意性地示出根据各种实施例的图1至图5中所示类型的半导体封装体的仰视图。
图7示意性地示出根据各种实施例的图1至图5中所示类型的另一半导体封装体的仰视图。
图8示意性地示出根据各种实施例的第六半导体封装体。
图9示意性地示出根据各种实施例的图8中所示类型的半导体封装体的仰视图。
图10是用于制造根据各种实施例的半导体封装体的方法的工艺流程图。
具体实施方式
本公开的实施例描述用于窗口球栅阵列(BGA)半导体封装体的半导体封装技术、结构和配置。在以下详细描述中，参照构成本说明书一部分的附图，在全部附图中相同标记指代相同部件。在不脱离本公开的范围的情况下，可以利用其它实施例并且可以进行结构或逻辑的改变。因此，并非在限制的意义上进行以下详细描述，实施例的范围是由所附权利要求及其等同方案限定。
本说明书可能使用基于透视图的描述，诸如上/下、前/后以及顶部\底部。使用这种描述仅为了便于讨论，而不旨在于将这里描述的实施例的应用限制为任何特定取向。
为了本公开的目的，措词“A/B”是指A或B。为了本公开的目的，措词“A和/或B”是指“(A)、(B)或(A和B)”。为了本公开的目的，措词“A、B和C中的至少一个”是指“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)”。为了本公开的目的，措词“(A)B”是指“(B)或(AB)”，也就是说，A是可选元素。
按照最有助于理解所要求保护的主题的方式，将各种操作依次描述为多个分立操作。然而，描述的顺序不应解释为暗示这些操作一定是与顺序有关的。具体而言，这些操作可以不按照呈现的顺序执行。可以按照与所描述的实施例不同的顺序执行所描述的操作。可以执行各种附加操作以及/或者可以在附加实施例中省略所描述的操作。
本说明书使用措词“在一个实施例中”、“在实施例中”或类似语言，其均可以指代相同或不同实施例中的一个或多个实施例。此外，关于本公开的实施例所用的术语“包括”、“包含”、“具有”等是同义的。
图1示意性地示出根据各种实施例的第一半导体封装体100。第一半导体封装体100和这里描述的其它半导体封装体通常布置成窗口BGA配置。第一半导体封装体100包括如所示那样耦合的基底102和半导体裸片104。基底102具有第一表面A1和与第一表面A1相对的第二表面A2。开口106，也称为“窗口”，形成在基底102的第一表面A1和第二表面A2之间，以便于在半导体裸片104与基底102之间经由一根或多根键合线110来对诸如输入/输出(I/O)信号或电源/接地之类的电信号进行布线。
如所示的那样，半导体裸片104具有第一表面B1和与第一表面B1相对的第二表面B2。根据各种实施例，第一表面B1为半导体裸片104的有源表面，其上形成有多个集成电路(IC)器件(未示出)，诸如用于处理器和/或存储器的晶体管。半导体裸片104的第一表面B1使用一个或多个互连凸块108电耦合到基底102的第二表面A2。如所示的那样，该一个或多个互连凸块108耦合到半导体裸片104的外围部分。该一个或多个互连凸块108可以包括各种适当的柱、球、桩或其他类似结构中的任何一种结构来对半导体裸片104和基底102进行电耦合。在一个实施例中，使用该一个或多个互连凸块108来对半导体裸片104和基底102之间的大部分或者所有电源和/或接地连接进行布线，以提供比键合线更稳健的电源供给。
如所示的那样，使用穿过开口106的一根或多根键合线110，将半导体裸片104的第一表面B1进一步电耦合到基底102的第一表面A1。如所示的那样，该一根或多根键合线110直接耦合到半导体裸片104的中心部分，并且进一步直接耦合到基底102的第一表面A1。一个或多个导电结构，诸如线键合焊盘(为了避免附图由于具有太多细节而不清楚，所以未示出)，可以布置在基底102和半导体裸片104的表面上，以便于该一根或多根键合线110的附着。在一个实施例中，使用该一根或多根键合线110来对半导体裸片104和基底102之间的大部分或所有I/O信号进行布线。在其中第一半导体封装体100用于实现诸如动态随机访问存储器(DRAM)或片上系统(SoC)之类的器件的另一实施例中，分别使用一个或多个互连凸块108和键合线110来对具有不同速度的信号进行布线。例如，可以使用一个或多个互连凸块108来对高速数据进行布线，同时可以使用键合线110来对具有相对较低速的信号进行布线。
可以在基底102的第一表面A1和第二表面A2上形成例如迹线114的附加导电结构，以助于在半导体裸片104和基底102之间的电连接的布线。例如，可以使用形成在基底102的第一表面A1上的迹线114来对一根或多根键合线110与一个或多个封装互连结构(诸如一个或多个焊料球116)之间的电连接进行布线。在一个实施例中，迹线114扇出以将一根或多根键合线110电耦合到一个或多个焊料球116中的对应焊料球。该一个或多个焊料球116耦合到基底102的第一表面A1，以提供在第一半导体封装体100与在第一半导体封装体100外部的另一电子器件(未示出)之间的电路径，该另一电子器件诸如母板或其它电路板。还应注意，基底102可以包括多层基底。
形成在基底102的第二表面A2上的迹线114，例如可以使用在基底102的第一表面A1和第二表面A2之间形成的通孔结构(未示出)或任何其它适当的重新分布方案，电耦合到一个或多个封装互连结构(例如，一个或多个焊料球116)。因而，使用该一个或多个互连凸块108、一根或多根键合线110以及迹线114，可以将包括半导体裸片104的电源和/或I/O信号的电信号布线到一个或多个焊料球116。一个或多个互连凸块108、一根或多根键合线110以及迹线114可以包括多种导电材料中的任何一种，该多种导电材料例如包括诸如金(Au)、铜(Cu)、铝(Al)之类的金属、金属合金和/或可焊接材料。在其它实施例中，可以使用其它导电材料来形成一个或多个互连凸块108、一根或多根键合线110以及迹线114。
可以在基底102的第一表面A1和第二表面A2上形成焊料掩膜115或类似结构，以为迹线114提供电隔离和/或物理保护。焊料掩膜115一般包括诸如聚合物之类的电绝缘材料。
如所示的那样，形成包括模塑材料、包封材料或底部填充材料的电绝缘结构112，从而实质上填充在半导体裸片104的第一表面B1、基底102的第二表面A2以及一个或多个互连凸块108之间的区域。如所示的那样，该电绝缘结构112还实质上包封一根或多根键合线110并且实质上填充基底102的开口106。
在一个实施例中，电绝缘结构112是包括热固性树脂的模塑材料，该热固性树脂以固体形式(例如，粉末)沉积并经受热和/或压力以实质上填充所述和所示的区域。在另一实施例中，电绝缘结构112是通过液体配送(dispense；也可译为“点胶”)或注入工艺按液体形式沉积的底部填充材料。电绝缘结构112可以包括例如环氧树脂或任何其它适当的电绝缘材料。
根据各种实施例，第一半导体封装体100是具有暴露的半导体裸片104的最终产品半导体封装体。在其它实施例中，第一半导体封装体100是在半导体封装体制造工艺期间的中间半导体封装体。例如，第一半导体封装体100可以是用于图2的第二半导体封装体200和/或图5的第五半导体封装体500的半导体封装体制造工艺期间的中间半导体封装体。
图2示意性地示出根据各种实施例的第二半导体封装体200。该第二半导体封装体200包括结合第一半导体封装体100描述的基底102、半导体裸片104、一个或多个互连凸块108、一根或多根键合线110、迹线114、焊料掩膜115和焊料球116，其中基底102具有形成在基底102的第一表面A1和第二表面A2之间的开口106。
第二半导体封装体200还包括如所示那样配置的第一绝缘结构212和第二绝缘结构214。根据各种实施例，第一绝缘结构212包括底部填充材料(例如，通过液体配送技术形成)，而第二绝缘结构214包括模塑材料(例如，通过以固体形式沉积热固性树脂并施加热和/或压力形成)。在一些实施例中，模塑材料是与底部填充材料不相同的材料。
如所示的那样，第一绝缘结构212布置成实质上填充在半导体裸片104的第一表面B1、基底102的第二表面A2和一个或多个互连凸块108之间的区域。第一绝缘结构212还布置成实质上包封一个和更多个键合线110并且实质上填充基底102的开口106。如所示的那样，第二绝缘结构214耦合到基底102的第二表面A2和半导体裸片104的第二表面B2，以实质上包封半导体裸片104。第二半导体封装体200例如可以通过将第二绝缘结构214沉积到图1的第一半导体封装体100上来形成。
根据各种实施例，第二半导体封装体200是最终产品半导体封装体，其具有用于为半导体裸片104提供底部填充的第一绝缘结构212和用于为半导体裸片104提供包封模塑料的第二绝缘结构214。在其它实施例中，第二半导体封装体200是半导体封装体制造工艺期间的中间半导体封装体。例如，第二半导体封装体200可以是在用于图5的第五半导体封装体500的半导体封装体制造工艺期间的中间半导体封装体。
图3示意性地示出根据各种实施例的第三半导体封装体300。该第三半导体封装体300包括结合第一半导体封装体100描述的基底102、半导体裸片104、一个或多个互连凸块108、一根或多根键合线110、迹线114、焊料掩膜115和焊料球116，其中基底102具有形成在基底102的第一表面A1和第二表面A2之间的开口106。
第三半导体封装体300还包括绝缘结构312，该绝缘结构312包括模塑料。如所示的那样，该绝缘结构312是通过以下步骤形成的：将固体形式(例如，粉末)的模塑材料沉积到预先形成的图案或模具中，以及施加热和/或压力使模塑材料流动并形成绝缘结构312。如所示的那样，绝缘结构312的模塑材料实质上填充在半导体裸片104的第一表面B1、基底102的第二表面A2和一个或多个互连凸块108之间的区域。绝缘结构312的模塑材料还布置成实质上包封一个和更多个键合线110并且实质上填充基底102的开口106。绝缘结构312的模塑材料还耦合到基底102的第二表面A2和半导体裸片104的第二表面B2，以实质上包封半导体裸片104。使用模塑材料包封半导体裸片104并填充底部填充区域可以减少工艺操作数目并降低与制造第三半导体封装体300关联的成本。
根据各种实施例，第三半导体封装体300是具有绝缘结构312的最终产品半导体封装体，该绝缘结构312仅包括模塑材料，其包封半导体裸片104并填充在半导体裸片104和基底102之间的底部填充区域。在其它实施例中，第三半导体封装体300是半导体封装体制造工艺期间的中间半导体封装体。例如，第三半导体封装体300可以是在用于图4的第四半导体封装体400的半导体封装体制造工艺期间的中间半导体封装体。
图4示意性地示出根据各种实施例的第四半导体封装体400。该第四半导体封装体400包括结合第一半导体封装体100描述的基底102、半导体裸片104、一个或多个互连凸块108、一根或多根键合线110、迹线114、焊料掩膜115和焊料球116，其中基底102具有形成在基底102的第一表面A1和第二表面A2之间的开口106。
第四半导体封装体400还包括电绝缘结构412。该电绝缘结构412可以包括模塑料、包封材料或底部填充材料。在一个实施例中，该电绝缘结构412包括模塑料。
如所示的那样，该电绝缘结构412实质上填充在半导体裸片104的第一表面B1、基底102的第二表面A2和一个或多个互连凸块108之间的区域。该绝缘结构412还布置成实质上包封一个和更多个键合线110并且实质上填充基底102的开口106。如所示的那样，该绝缘结构412还耦合到基底102的第二表面A2以及与半导体裸片的第二表面B2实质上垂直的半导体裸片104的表面B3。
电绝缘结构412与半导体裸片104的第二表面B2实质上成一平面。半导体裸片104的第二表面B2被暴露。也就是说，电绝缘结构412不布置在半导体裸片104的第二表面B2上。第四半导体封装体400例如可以通过以下步骤来形成：使用抛光工艺去除图3的第三半导体封装体300的电绝缘结构312的材料，以暴露半导体裸片104的第二表面B2并且提供平面表面，如图4所示。作为选择，可以使用暴露裸片模塑系统来暴露半导体裸片104的第二表面B2。
根据各种实施例，第四半导体封装体400是具有绝缘结构412的最终产品半导体封装体，该绝缘结构412仅包括模塑材料，其与半导体裸片104的背面(例如，第二表面B2)成一平面，从而暴露该背面。在其它实施例中，第四半导体封装体400是半导体封装体制造工艺期间的中间半导体封装体。例如，可以将诸如热沉(heatsink)之类的另一组件(未示出)耦合到暴露的半导体裸片104的第二表面B2，以助于将热量从第四半导体封装体400去除。
图5示意性地示出根据各种实施例的第五半导体封装体500。该第五半导体封装体500包括结合第一半导体封装体100描述的基底102、半导体裸片104、一个或多个互连凸块108、一根或多根键合线110、迹线114、焊料掩膜115和焊料球116，其中基底102具有形成在基底102的第一表面A1和第二表面A2之间的开口106。
第五半导体封装体500还包括包含底部填充材料的第一电绝缘结构512和包含模塑材料的第二电绝缘结构514。如所示的那样，第一电绝缘结构512实质上填充在半导体裸片104的第一表面B1、基底102的第二表面A2和一个或多个互连凸块108之间的区域。第一绝缘结构512还布置成实质上包封一个和更多个键合线110并且实质上填充基底102的开口106。
如所示的那样，第二电绝缘结构514耦合到基底102的第二表面A2以及与半导体裸片的第二表面B2实质上垂直的半导体裸片104的表面B3。第二电绝缘结构514与半导体裸片104的第二表面B2实质上成一平面。第二电绝缘结构514不布置在半导体裸片104的第二表面B2上。第五半导体封装体500例如可以通过以下步骤来形成：使用抛光工艺去除图2的第二半导体封装体200的第二电绝缘结构214的材料，以暴露半导体裸片104的第二表面B2并且提供实质上为平面的表面，如图5所示。
第五半导体封装体500还包括耦合到半导体裸片104的第二表面B2的热沉518。热沉518有助于将热量从第五半导体封装体500去除。在一个实施例中，热沉518大于半导体裸片104以提供更好的散热，并且在尺寸上大致与半导体封装体500相同。热沉518可以具有平坦的顶表面，但作为选择，热沉518也可以包括其它配置，诸如波纹配置，以使用于散热的表面面积最大化。
根据各种实施例，第五半导体封装体500是最终产品半导体封装体。应清楚的是，在其它实施例中可以适当地结合关于图1至图5的半导体封装体描述的这些实施例。例如，第五半导体封装体500可以是没有热沉518的最终产品半导体封装体。也就是说，在该最终产品半导体封装体中，图5的第五半导体封装体500可以具有暴露的裸片背面(例如，半导体裸片104的第二表面B2)。适当结合图1至图5的半导体封装体方面的其它实施例是可以预想到的并且落入本公开的范围。
图6示意性地示出根据各种实施例的图1至图5中所述类型的半导体封装体600的仰视图。在该半导体封装体600的仰视图中省略结合图1至图5描述的焊料球116、迹线114、焊料掩膜115和各种电绝缘结构(例如，电绝缘结构112、212、312、412和512)，以免用太多细节使图不清楚。
通过虚线矩形表示出半导体裸片104，以指示半导体裸片104在基底102背后的部分在图6的仰视图中是不可见的。半导体裸片104的第一表面B1在形成于基底102中的开口106内是可见的。
一个或多个线键合焊盘630布置在半导体裸片104的第一表面B1上，以助于将一根或多根键合线110附着到半导体裸片104。在一个实施例中，将开口106内的一个或多个线键合焊盘630配置成对用于半导体裸片104的大部分或所有I/O信号进行布线。一般而言，一根或多根键合线110直接耦合到一个或多个线键合焊盘630并且还直接耦合到布置在基底102的第一表面A1上的诸如焊盘(未示出)或迹线(例如，图1至图5中的114)的类似结构，该类似结构可以进一步将电信号布线到布置在基底102的第一表面A1上的封装互连结构(例如，图1至图5的焊料球116)。
根据各种实施例，半导体裸片104包括具有第一区域的第一矩形形状，如虚线所示，并且基底的开口106包括具有第二区域的第二矩形形状，如所示的那样。当第二区域被第一区域覆盖时，如图6的半导体封装体600的仰视图所示，第二区域完全布置在第一区域内。此外，当第二区域被第一区域覆盖时，第二区域实质上位于第一区域的中心。第一矩形形状和第二矩形形状的侧边如所示那样实质上平行。
图7示意性地示出根据各种实施例的图1至图5所示类型的另一半导体封装体700的仰视图。除了图7的基底102中的开口106与图6的基底102中的开口106相比进行了偏移之外，图7的半导体封装体700包括结合图6的半导体封装体600描述的特征。根据一些实施例，半导体封装体700包括形成在开口106的所有四个侧边上的一根或多根键合线110，如所示的那样。也就是说，一根或多根键合线110耦合到沿着开口106的四个侧边的各侧边的长度布置的一个或多个线键合焊盘630。
根据各种实施例，半导体裸片104包括具有第一区域的第一矩形形状，如虚线所示，并且基底的开口106包括具有第二区域的第二矩形形状，如所示的那样。当第二区域被第一区域覆盖时，如图7的半导体封装体700的仰视图所示，第二区域完全布置在第一区域内。此外，当如所示的那样第二区域被第一区域覆盖时，第二区域实质上位于第一区域的中心。在半导体封装体700中，第一矩形形状的侧边(例如侧边S1)从第二矩形形状的侧边(例如，侧边S2)偏移约45度，如图7中由角度θ所表示的那样。
图8示意性地示出根据各种实施例的第六半导体封装体800。第六半导体封装体800包括诸如引线框之类的基底802，该基底802具有形成在基底802的第一表面A1和第二表面A2之间的一个或多个开口806，以及配置成支持其上布置的半导体裸片104的裸片垫(diepaddle)850。如所示的那样，裸片垫850在基底802的外围部分之间实质上居中，并且在结构上使用一个或多个连接杆(tiebar)(例如，在该图中未示出但在图9中示出为一个或多个连接杆975)耦合到基底802的外围部分。裸片垫850和一个或多个连接杆是基底802的裸片支撑结构的部分。
半导体裸片104使用穿过基底802的一个或多个开口806的一根或多根键合线110而电耦合到基底802的第一表面A1。半导体裸片104还使用一个或多个互连凸块108电耦合到基底802的第二表面A2(例如，裸片垫850)。一根或多根键合线110以及一个或多个互连凸块108用来对去往半导体裸片104或者来自半导体裸片104的诸如I/O和/或电源/接地信号之类的电信号进行布线。在一个实施例中，一根或多根键合线110用来对用于半导体裸片104的所有或者实质上所有I/O信号进行布线，而一个或多个互连凸块108用来对用于半导体裸片104的所有或者实质上所有电源/接地连接进行布线。在其中半导体封装体800用于实现诸如动态随机访问存储器(DRAM)或片上系统(SoC)的另一实施例中，一个或多个互连凸块108和键合线110分别用来对具有不同速度的信号进行布线。例如，一个或多个互连凸块108可以用来对高速数据进行布线，而键合线110可以用来对具有相对低速的信号进行布线。
诸如引线或键合指(bondfinger)之类的迹线114或类似结构可以布置在基底802的第一表面A1和/或第二表面A2上，以助于重新分布电信号。焊料掩膜115可以用来保护和/或电隔离迹线114。一个或多个焊料球116耦合到基底802的第一侧边A1，以进一步便于对去往第六半导体封装体800或者来自第六半导体封装体800的电信号的布线。
电绝缘结构812布置成实质上填充基底802在半导体裸片104与裸片垫850部分之间的区域，并且实质上填充基底802的一个或多个开口806，如所示的那样。电绝缘结构812可以与已结合图1至图5描述的电绝缘结构描述的实施例一致。例如，电绝缘结构812可以包括模塑料、包封材料或底部填充材料或其组合。
图9示意性地示出根据各种实施例的图8所示类型的半导体封装体900的仰视图。为清楚起见，在该半导体封装体900的仰视图中省略结合图8描述的焊料球116、迹线114、焊料掩膜115和电绝缘结构812。
半导体封装体900包括具有裸片垫850的基底802(例如，图9中示出基底802的第一表面A1)，使用一个或多个连接杆975在结构上将该裸片垫850耦合到基底802的外围部分，如所示的那样。裸片垫850和一个或多个连接杆975是基底802的裸片支撑结构的部分。在一些实施例中，基底802(例如，包括裸片垫850和一个或多个连接杆975)可以是单个连续结构的部分。
一个或多个开口806布置在裸片垫850和基底802的外围部分之间。半导体裸片104布置在裸片垫850上，使得在图9的仰视图中半导体裸片104的中心部分不可透过裸片垫850得见。半导体裸片104的虚线部分表示半导体裸片104通过一个或多个连接杆975而从仰视图隐藏的区域。半导体裸片104的外围部分通过一个或多个开口806而可见。一个或多个线键合焊盘930布置在半导体裸片104的外围部分上，以提供用于一根或多根键合线110的连接位置。一根或多根键合线110直接耦合到一个或多个线键合焊盘930以及布置在基底802上的对应焊盘(未示出)或迹线(例如，图8的114)。在一个实施例中，一根或多根键合线110附着到半导体裸片104的四个侧边的每个侧边，如所示的那样。
在一些实施例中，附加的一根或多根键合线110a直接耦合到一个或多个线键合焊盘930并且直接耦合到裸片垫850和/或连接杆975。应清楚的是，一根或多根键合线110和附加的一根或多根键合线110a可以利用电绝缘结构(例如，图8的电绝缘结构812)来包封。在一些实施例中，裸片垫850和/或连接杆为半导体裸片104提供接地和/或电源供给。
根据各种实施例，半导体裸片104包括具有第一区域的第一矩形形状，如所示的那样。裸片垫850包括具有第二区域的第二实质上为矩形的形状(例如由虚线矩形960所示的)，如所示的那样。当第二区域被第一区域覆盖时，如图9的半导体封装体800的仰视图所示，第二区域完全布置在第一区域内。此外，当如所示的那样第二区域被第一区域覆盖时，第二区域实质上位于第一区域的中心。第一矩形形状和第二实质上为矩形的形状的侧边实质上平行，如所示的那样。结合图8和图9所述的实施例可以与结合图1至图7所述的实施例适当地结合。
图10是用于制造根据各种实施例的半导体封装体的方法1000的工艺流程图。在方框1002，方法1000包括提供具有开口(例如，图1至图7的开口106或者图8至图9的一个或多个开口806)的基底(例如，图1至图7的基底102或者图8至图9的基底802)。一般形成通过相对表面(例如，图1至图9的表面A1和表面A2)的开口，以为通过线键合布线的电信号提供路径。
在方框1004，方法1000进一步包括将半导体裸片(例如，图1至图9的半导体裸片104)电耦合到衬底以形成半导体封装体(例如，相应图1至图9的半导体封装体100、200、300、400、500、600、700、800或900)。在一些实施例中，使用一个或多个互连凸块(例如，图1至图5以及图8的一个或多个互连凸块108)将半导体裸片电耦合到基底。
在方框1006，方法1000进一步包括形成一根或多根键合线(例如，图1至图9的键合线110)以通过基底的开口将半导体裸片电耦合到基底。一根或多根键合线一般使用热、压力和/或超声能量的组合来附着到布置在半导体裸片和/或基底上的线键合焊盘(例如，图6至图7以及图9的线键合焊盘630或930)从而形成焊接。一根或多根键合线可以例如使用球键合或楔键合工艺来附着。根据各种实施例，一根或多根键合线用来对用于半导体裸片的大部分或所有I/O信号进行布线，而一个或多个互连凸块用来对用于半导体裸片的大部分或所有电源/接地信号进行布线。
在方框1008，方法1000还包括形成电绝缘结构(例如，图1至图5以及图8的相应的电绝缘结构112、212、214、312、412、512、514和812)，以至少实质上填充在半导体裸片和基底之间的区域并且还实质上填充基底的开口。根据各种实施例，电绝缘结构布置成包封一根或多根键合线。电绝缘结构可以包括例如这里所述的模塑料、包封材料或底部填充材料或其组合。例如，模塑料可以通过以下步骤来形成：将固体形式(例如粉末)的热固性树脂向预先形成的布图或模具沉积，以及施加热和/或压力使热固性树脂形成图1至图5以及图8所示的电绝缘结构。在另一示例中，根据液体配送技术对液体形式的底部填充材料进行配送，以形成图1至图5以及图8所示的电绝缘结构。
在一个实施例中，沉积底部填充材料，以实质上填充在半导体裸片与基底之间的区域并且进一步实质上填充基底的开口(例如，针对图2的第一电绝缘结构212所述)。沉积模塑料以实质上包封半导体裸片(例如，针对图2的第二电绝缘结构214所述)，该模塑料耦合到半导体裸片的顶表面(例如，图2的第二表面B2)和基底的顶表面(例如，图2的第一表面A2)。在其它实施例中，形成模塑料，以实质上填充在半导体裸片与基底之间的区域并进一步实质上填充基底的开口。还形成模塑材料来实质上包封半导体裸片(例如，针对图3的电绝缘结构312所述)。
可以去除沉积的电绝缘材料的多个部分以形成一个或多个电绝缘结构。例如，可以通过抛光工艺来去除电绝缘材料以暴露半导体裸片的背面或顶表面(例如，图4的第二表面B2)，使得一个或多个电绝缘结构与半导体裸片的第二表面实质上成一平面。热沉(例如，图5的热沉518)或其它部件可以耦合到半导体裸片的背面或顶表面，以助于将热量从半导体封装体去除。
在方框1010，方法1000进一步包括在基底上形成一个或多个特征(例如，图1至图5以及图8的焊料球116)，以提供在半导体封装体与在半导体封装体外部的诸如母板或其它电路板的电子器件之间的电路径。该一个或多个特征一般形成在半导体封装体的底表面(例如，图1至图9的第一表面A1)，并且可以包括球栅阵列(BGA)类型配置的焊料球。
尽管这里示出并描述了特定实施例，但在不脱离本公开的范围的情况下，旨在实现相同目的的各种备选和/或等同实施例或实现可以替代所示出和所描述的这些实施例。本公开旨在覆盖这里讨论的实施例的任何调整或变体。因此，应当明白的是，这里所述的实施例仅由各权利要求及其等同方案限定。

Claims (13)

1.一种半导体封装体，包括：
基底，其具有(i)第一表面、(ii)与所述第一表面相对的第二表面以及(iii)形成在所述基底的第一表面与所述基底的第二表面之间的开口；
半导体裸片，其具有(i)第一表面以及(ii)与所述第一表面相对的第二表面，所述半导体裸片的第一表面通过一个或多个互连凸块电耦合到所述基底的第二表面；
一根或多根键合线，其通过所述基底的开口将所述半导体裸片的第一表面电耦合到所述基底的第一表面；
第一电绝缘结构，其布置成填充在(i)所述半导体裸片的第一表面和(ii)所述基底的第二表面之间的区域，其中所述第一电绝缘结构包封(i)所述一根或多根键合线以及(ii)所述一个或多个互连凸块，并且其中所述第一电绝缘结构填充所述基底的开口；以及
第二电绝缘结构，其耦合到所述基底的第二表面，并且还耦合到与所述半导体裸片的第二表面垂直的所述半导体裸片的表面，
其中所述第二电绝缘结构与所述半导体裸片的第二表面成一平面，并且
其中所述第二电绝缘结构不布置在所述半导体裸片的第二表面上。
2.根据权利要求1所述的半导体封装体，进一步包括：
热沉，其耦合到所述半导体裸片的第二表面。
3.根据权利要求1所述的半导体封装体，其中所述第一电绝缘结构和第二电绝缘结构包括相同的模塑材料。
4.根据权利要求1所述的半导体封装体，其中：
所述第一电绝缘结构包括底部填充材料；并且
所述第二电绝缘结构包括与所述底部填充材料不相同的模塑材料。
5.根据权利要求1所述的半导体封装体，其中：
所述半导体裸片包括具有第一区域的第一矩形形状；
所述基底的开口包括具有第二区域的第二矩形形状；
所述第二区域被所述第一区域覆盖，使得所述第二区域完全布置在所述第一区域内；并且
所述第二区域被所述第一区域覆盖，使得所述第二区域位于所述第一区域的中心。
6.根据权利要求5所述的半导体封装体，其中：
所述第一矩形形状的侧边从所述第二矩形形状的侧边偏移约45度。
7.根据权利要求1所述的半导体封装体，进一步包括：
一个或多个焊料球，其耦合到所述基底的第一表面，以提供在所述半导体封装体与所述半导体封装体外部的电子器件之间的电路径；以及
一个或多个迹线，其形成在所述基底的第一表面上，以对所述一根或多根键合线与所述一个或多个焊料球之间的电连接进行布线；
其中所述一根或多根键合线提供用于去往所述半导体裸片或来自所述半导体裸片的所有输入/输出信号(I/O)的电连接。
8.一种半导体封装体，包括：
基底，其具有(i)第一表面、(ii)与所述第一表面相对的第二表面以及(iii)形成在所述基底的第一表面与所述基底的第二表面之间的开口；
半导体裸片，其具有(i)第一表面以及(ii)与所述第一表面相对的第二表面，所述半导体裸片的第一表面通过一个或多个互连凸块电耦合到所述基底的第二表面；
一根或多根键合线，其通过所述基底的开口将所述半导体裸片的第一表面电耦合到所述基底的第一表面；以及
第一电绝缘结构，其布置成填充在(i)所述半导体裸片的第一表面和(ii)所述基底的第二表面之间的区域，其中所述第一电绝缘结构包封(i)所述一根或多根键合线以及(ii)所述一个或多个互连凸块，并且其中所述第一电绝缘结构填充所述基底的开口，
其中所述半导体裸片的第二表面被暴露；并且
与所述半导体裸片的第二表面垂直的所述半导体裸片的至少一个表面被暴露。
9.一种半导体封装方法，包括：
提供基底，所述基底具有(i)第一表面、(ii)与所述第一表面相对的第二表面以及(iii)形成在所述基底的第一表面与所述基底的第二表面之间的开口；
将半导体裸片电耦合到所述基底以形成半导体封装体，所述半导体裸片具有(i)第一表面以及(ii)与所述第一表面相对的第二表面，所述半导体裸片的第一表面通过一个或多个互连凸块电耦合到所述基底的第二表面；
形成一根或多根键合线，以通过所述基底的开口将所述半导体裸片的第一表面电耦合到所述基底的第一表面；
形成第一电绝缘结构，以填充在(i)所述半导体裸片的第一表面和(ii)所述基底的第二表面之间的区域，其中所述第一电绝缘结构包封(i)所述一根或多根键合线以及(ii)所述一个或多个互连凸块，并且其中所述第一电绝缘结构填充所述基底的开口；以及
形成第二电绝缘结构，其耦合到所述基底的第二表面，并且还耦合到与所述半导体裸片的第二表面垂直的所述半导体裸片的表面，
其中所述第二电绝缘结构与所述半导体裸片的第二表面成一平面，并且
其中所述第二电绝缘结构不布置在所述半导体裸片的第二表面上。
10.根据权利要求9所述的方法，其中所述电绝缘结构通过配送液体形式的底部填充材料而形成。
11.根据权利要求9所述的方法，进一步包括：
去除所述电绝缘结构的一部分以暴露所述半导体裸片的第二表面，使得所述电绝缘结构与所述半导体裸片的第二表面成一平面。
12.根据权利要求11所述的方法，进一步包括：
将热沉附着到所述半导体裸片的第二表面。
13.根据权利要求9所述的方法，进一步包括：
将一个或多个焊料球附着到所述基底的第一表面，以提供在所述半导体封装体与所述半导体封装体外部的电子器件之间的电路径。
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