JP2008537332A - 基板無し半導体パッケージを形成する方法 - Google Patents
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910002804 graphite Inorganic materials 0.000 claims description 3
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- 229910052737 gold Inorganic materials 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Abstract
Description
ここで図11を参照する。図11には、基板無し半導体パッケージ100を形成するために用いられるベースプレート102の平面図を示す。ベースプレート102は複数のキャビティ104を備える。この特定の例では、キャビティ104はベースプレート102上に、2×3配列のキャビティ104を形成するようにグループ化されている。各グループのキャビティ104は、さらに複数のダイ支持領域106のそれぞれの周囲に配置されている。この特定の例では、ベースプレート102の高さ、即ち、厚さは、約0.56mmであり、キャビティ104の各々の深さは約0.40mmである。しかしながら、ベースプレート102の寸法またはキャビティ104の寸法によって本発明が限定されないことが理解される。上述のように、当業者には、キャビティ104の配置、形状、または数によって本発明が限定されないことが理解される。ベースプレート102は黒鉛またはアルミニウムボートから構成されてよい。これは再利用可能である。
Claims (20)
- 半導体パッケージを形成する方法であって、
複数のキャビティを有するベースプレートを提供するベースプレート提供工程と、
はんだ材料を用いてベースプレート上にキャリアを形成するキャリア形成工程と、はんだ材料は複数のキャビティを充填することによって複数の柱を形成することと、
キャリア上に集積回路(IC)ダイを配置するダイ配置工程と、
ICダイおよびキャリアを電気的に接続する電気接続工程と、
ICダイ、電気接続、および少なくともキャリアの一部を封入するように成形作業を実行する成形工程と、からなる方法。 - 成形工程の実行後にベースプレートを除去する工程と、柱の先端は露出されることと、を含む請求項1に記載の方法。
- はんだ材料はベースプレート上に2パスで印刷される請求項1に記載の方法。
- はんだ材料は、共晶はんだ、高鉛はんだ、および鉛フリーはんだのうちの1つである請求項3に記載の方法。
- はんだ材料はステンシルを用いてベースプレート上に印刷される請求項3に記載の方法。
- ステンシルの厚さは約0.102mm(約4ミル)未満である請求項5に記載の方法。
- ベースプレートは、はんだ材料から分離可能な材料から製造されている請求項1に記載の方法。
- ベースプレートの材料は、黒鉛、アルミニウム、およびステンレス鋼のうちの1つである請求項7に記載の方法。
- ベースプレートの厚さは約1ミリメートル(mm)未満である請求項8に記載の方法。
- 複数のキャビティの各々の深さは約0.40mmである請求項9に記載の方法。
- 複数のはんだ小滴を形成するように複数の柱をリフローする工程を含む請求項1に記載の方法。
- 複数のはんだ小滴からコントロールド・コラプス・チップ・キャリア・コネクション(C5)型の相互接続が形成される請求項11に記載の方法。
- ICダイとキャリアとの間の電気接続はワイヤボンディングによる請求項1に記載の方法。
- ICダイは接着テープを用いてキャリアに取り付けられている請求項1に記載の方法。
- 接着テープおよびベースプレートの対向する表面間のスタンドオフは約0.075mmに維持される請求項14に記載の方法。
- ICダイとキャリアとの間の電気接続はフリップチップボンディングによる請求項1に記載の方法。
- 半導体パッケージを形成する方法であって、
複数のキャビティを有するベースプレートを提供するベースプレート提供工程と、
はんだ材料を用いてベースプレート上にキャリアを形成するキャリア形成工程と、はんだ材料は複数のキャビティを充填することによって複数のはんだ柱を形成することと、
キャリア上に集積回路(IC)ダイを取り付けるダイ取付工程と、
ICダイを囲む複数のはんだ柱のそれぞれとICダイのボンディングパッドとをワイヤボンディングするワイヤボンド工程と、
ICダイ、電気接続、およびキャリアの一部を封入するように成形作業を実行する成形工程と、からなる方法。 - 柱の先端が露出されるように成形工程の実行後にベースプレートを除去する工程を含む請求項17に記載の方法。
- 複数の半導体パッケージを形成する方法であって、
複数のキャビティを有するベースプレートを提供するベースプレート提供工程と、
はんだ材料を用いてベースプレート上にキャリアを形成するキャリア形成工程と、はんだ材料は複数のキャビティを充填することによって複数の柱を形成することと、
キャリア上に集積回路(IC)ダイを配置するダイ配置工程と、
ICダイを複数の柱のそれぞれと電気的に接続する電気接続工程と、
ICダイ、電気接続、および少なくともキャリアの一部を封入するように成形作業を実行する成形工程と、
複数のICダイのうちの隣接するICダイを分離するようにシンギュレート作業を実行することによって、複数の半導体パッケージを形成するシンギュレート工程と、からなる方法。 - 柱の先端を露出するようにベースプレートを除去する工程を含む請求項19に記載の方法。
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US11/108,220 US7160755B2 (en) | 2005-04-18 | 2005-04-18 | Method of forming a substrateless semiconductor package |
PCT/US2006/006417 WO2006112947A1 (en) | 2005-04-18 | 2006-02-23 | Method of forming a substrateless semiconductor package |
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JP2008537332A true JP2008537332A (ja) | 2008-09-11 |
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JP2008506455A Pending JP2008537332A (ja) | 2005-04-18 | 2006-02-23 | 基板無し半導体パッケージを形成する方法 |
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US (1) | US7160755B2 (ja) |
JP (1) | JP2008537332A (ja) |
MY (1) | MY138000A (ja) |
TW (1) | TW200711010A (ja) |
WO (1) | WO2006112947A1 (ja) |
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TW200711010A (en) | 2007-03-16 |
US7160755B2 (en) | 2007-01-09 |
MY138000A (en) | 2009-04-30 |
WO2006112947A1 (en) | 2006-10-26 |
US20060234421A1 (en) | 2006-10-19 |
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