CN102169515B - 一种专用集成电路中时钟树延迟时间的估计方法和系统 - Google Patents
一种专用集成电路中时钟树延迟时间的估计方法和系统 Download PDFInfo
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- CN102169515B CN102169515B CN201010117747.7A CN201010117747A CN102169515B CN 102169515 B CN102169515 B CN 102169515B CN 201010117747 A CN201010117747 A CN 201010117747A CN 102169515 B CN102169515 B CN 102169515B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Abstract
Description
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CN201010117747.7A CN102169515B (zh) | 2010-02-26 | 2010-02-26 | 一种专用集成电路中时钟树延迟时间的估计方法和系统 |
US13/031,953 US8453085B2 (en) | 2010-02-26 | 2011-02-22 | Method for estimating the latency time of a clock tree in an ASIC design |
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CN201010117747.7A CN102169515B (zh) | 2010-02-26 | 2010-02-26 | 一种专用集成电路中时钟树延迟时间的估计方法和系统 |
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CN102169515A CN102169515A (zh) | 2011-08-31 |
CN102169515B true CN102169515B (zh) | 2014-04-16 |
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CN (1) | CN102169515B (zh) |
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CN102479264A (zh) * | 2010-11-25 | 2012-05-30 | 上海华虹集成电路有限责任公司 | 一种降低瞬态功耗的方法 |
CN102799698B (zh) * | 2011-05-26 | 2014-07-23 | 国际商业机器公司 | 一种用于专用集成电路的时钟树规划的方法和系统 |
WO2013044494A1 (zh) * | 2011-09-30 | 2013-04-04 | 中国科学院微电子研究所 | 集成电路仿真方法及系统 |
US8677305B2 (en) | 2012-06-04 | 2014-03-18 | International Business Machines Corporation | Designing a robust power efficient clock distribution network |
US8775996B2 (en) | 2012-11-19 | 2014-07-08 | International Business Machines Corporation | Direct current circuit analysis based clock network design |
US8635579B1 (en) * | 2012-12-31 | 2014-01-21 | Synopsys, Inc. | Local clock skew optimization |
CN104573148B (zh) * | 2013-10-17 | 2017-11-14 | 北京华大九天软件有限公司 | 一种降低电路中时序器件漏电功耗的方法 |
CN104598659B (zh) | 2013-10-31 | 2018-09-18 | 格芯公司 | 对数字电路进行仿真的方法和设备 |
CN105653748B (zh) * | 2014-11-14 | 2019-03-08 | 京微雅格(北京)科技有限公司 | 一种时钟树资源的分配方法和时钟树架构 |
CN105868431B (zh) * | 2015-01-22 | 2018-12-21 | 京微雅格(北京)科技有限公司 | 基于锚点的布线方法 |
CN105512381B (zh) * | 2015-12-03 | 2019-08-09 | 上海兆芯集成电路有限公司 | 时钟延迟验证方法 |
CN105550459B (zh) * | 2015-12-29 | 2019-03-19 | 山东海量信息技术研究院 | 一种asic设计时钟网络提取系统 |
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EP4068142A1 (en) | 2016-12-23 | 2022-10-05 | Google LLC | Integrated circuit design system and method |
KR20180092692A (ko) * | 2017-02-10 | 2018-08-20 | 삼성전자주식회사 | Beol을 고려하여 집적 회로를 설계하기 위한 컴퓨터 구현 방법 및 컴퓨팅 시스템 |
CN108256189B (zh) * | 2018-01-06 | 2021-08-03 | 嘉兴倚韦电子科技有限公司 | 集成电路半定制后端设计高效时钟树物理位置优化方法 |
CN109255159B (zh) * | 2018-08-17 | 2023-04-07 | 东南大学 | 一种基于机器学习的电路路径延时波动预测方法 |
CN111666732B (zh) * | 2019-03-07 | 2023-09-26 | 瑞昱半导体股份有限公司 | 集成电路布局设计方法 |
US10810344B1 (en) * | 2019-03-29 | 2020-10-20 | Hongchang Liang | Multi-instantiation time budgeting for integrated circuit design and manufacturing |
US11042678B2 (en) | 2019-06-19 | 2021-06-22 | Samsung Electronics Co., Ltd. | Clock gate latency modeling based on analytical frameworks |
CN112231998A (zh) * | 2020-10-14 | 2021-01-15 | 北京百瑞互联技术有限公司 | 一种集成电路的时钟网络抽取方法、装置及其存储介质 |
CN112257364B (zh) * | 2020-10-23 | 2022-05-20 | 北京大学 | 一种gpu加速计算的集成电路静态时序分析方法 |
CN112613261B (zh) * | 2020-12-24 | 2022-11-22 | 天津国芯科技有限公司 | 一种确定block端口时钟域的方法 |
CN114764118A (zh) * | 2021-01-14 | 2022-07-19 | 深圳比特微电子科技有限公司 | 测试电路、测试方法和包括测试电路的计算系统 |
CN113177383B (zh) * | 2021-04-29 | 2023-01-31 | 飞腾信息技术有限公司 | 一种基于dummy的时钟设计方法 |
CN114818595B (zh) * | 2022-06-24 | 2022-09-13 | 飞腾信息技术有限公司 | 芯片模块接口时钟构建方法、装置、存储介质及电子设备 |
CN117371379A (zh) * | 2022-06-30 | 2024-01-09 | 深圳市中兴微电子技术有限公司 | 时序库最大负载的生成方法和装置、存储介质及电子装置 |
CN116341481B (zh) * | 2023-05-26 | 2023-08-22 | 南京芯驰半导体科技有限公司 | 一种时钟文件的确认方法、装置、电子设备及存储介质 |
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JP2009152451A (ja) * | 2007-12-21 | 2009-07-09 | Texas Instr Japan Ltd | 集積回路装置とそのレイアウト設計方法 |
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2010
- 2010-02-26 CN CN201010117747.7A patent/CN102169515B/zh not_active Expired - Fee Related
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2011
- 2011-02-22 US US13/031,953 patent/US8453085B2/en not_active Expired - Fee Related
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US20120047478A1 (en) | 2012-02-23 |
US8453085B2 (en) | 2013-05-28 |
CN102169515A (zh) | 2011-08-31 |
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