CN104598659B - 对数字电路进行仿真的方法和设备 - Google Patents
对数字电路进行仿真的方法和设备 Download PDFInfo
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- CN104598659B CN104598659B CN201310530202.2A CN201310530202A CN104598659B CN 104598659 B CN104598659 B CN 104598659B CN 201310530202 A CN201310530202 A CN 201310530202A CN 104598659 B CN104598659 B CN 104598659B
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000008859 change Effects 0.000 claims abstract description 4
- 230000004048 modification Effects 0.000 claims description 14
- 238000012986 modification Methods 0.000 claims description 14
- 238000005086 pumping Methods 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 4
- 230000005284 excitation Effects 0.000 claims description 2
- 238000012795 verification Methods 0.000 abstract description 15
- 238000013461 design Methods 0.000 abstract description 12
- 230000005540 biological transmission Effects 0.000 description 32
- 230000006870 function Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 230000006399 behavior Effects 0.000 description 10
- 238000012545 processing Methods 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 238000004590 computer program Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000009466 transformation Effects 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (12)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310530202.2A CN104598659B (zh) | 2013-10-31 | 2013-10-31 | 对数字电路进行仿真的方法和设备 |
US14/524,413 US10146895B2 (en) | 2013-10-31 | 2014-10-27 | Method and apparatus for simulating a digital circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310530202.2A CN104598659B (zh) | 2013-10-31 | 2013-10-31 | 对数字电路进行仿真的方法和设备 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104598659A CN104598659A (zh) | 2015-05-06 |
CN104598659B true CN104598659B (zh) | 2018-09-18 |
Family
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Application Number | Title | Priority Date | Filing Date |
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CN201310530202.2A Expired - Fee Related CN104598659B (zh) | 2013-10-31 | 2013-10-31 | 对数字电路进行仿真的方法和设备 |
Country Status (2)
Country | Link |
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US (1) | US10146895B2 (zh) |
CN (1) | CN104598659B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105138769B (zh) * | 2015-08-24 | 2018-11-23 | 深圳市紫光同创电子有限公司 | 一种用于可编程电路的时序模型生成方法及装置 |
CN106503296B (zh) * | 2016-09-23 | 2019-08-27 | 京微齐力(北京)科技有限公司 | 一种基于白盒的工艺映射方法及装置 |
TWI627521B (zh) * | 2017-06-07 | 2018-06-21 | 財團法人工業技術研究院 | 時序估算方法與模擬裝置 |
CN111931445B (zh) | 2020-10-09 | 2020-12-29 | 芯华章科技股份有限公司 | 用于调试逻辑系统设计的方法、仿真器及存储介质 |
CN112417798B (zh) * | 2020-11-27 | 2023-05-23 | 成都海光微电子技术有限公司 | 一种时序测试方法、装置、电子设备及存储介质 |
CN112597720B (zh) * | 2020-12-28 | 2023-03-21 | 海光信息技术股份有限公司 | 一种功耗数据的收集方法、装置 |
CN115796090B (zh) * | 2022-12-13 | 2024-01-26 | 无锡沐创集成电路设计有限公司 | 电路模型生成方法、电路仿真验证方法及对应装置 |
CN116029239B (zh) * | 2022-12-30 | 2023-09-05 | 芯耀辉科技有限公司 | 静态时序分析方法及其系统、计算机可读取介质 |
Citations (1)
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---|---|---|---|---|
US5768145A (en) * | 1996-06-11 | 1998-06-16 | Lsi Logic Corporation | Parametrized waveform processor for gate-level power analysis tool |
Family Cites Families (25)
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US5625803A (en) * | 1994-12-14 | 1997-04-29 | Vlsi Technology, Inc. | Slew rate based power usage simulation and method |
US6457159B1 (en) * | 1998-12-29 | 2002-09-24 | Cadence Design Systems, Inc. | Functional timing analysis for characterization of virtual component blocks |
US20020042704A1 (en) * | 2000-08-31 | 2002-04-11 | Najm Farid N. | Apparatus and methods for characterizing electronic circuits having multiple power supplies |
JP3892256B2 (ja) * | 2000-09-08 | 2007-03-14 | 富士通株式会社 | 信号波形シミュレーション装置、信号波形シミュレーション方法および信号波形シミュレーションプログラムを記録したコンピュータ読み取り可能な記録媒体 |
US6584598B2 (en) * | 2001-02-16 | 2003-06-24 | Silicon Metrics Corporation | Apparatus for optimized constraint characterization with degradation options and associated methods |
US6807660B1 (en) * | 2002-10-01 | 2004-10-19 | Sequence Design, Inc. | Vectorless instantaneous current estimation |
US7206731B2 (en) * | 2003-06-02 | 2007-04-17 | Agilent Technologies, Inc. | Electromagnetic/circuit co-simulation and co-optimization with parametric layout components |
US7240304B2 (en) | 2004-05-04 | 2007-07-03 | Freescale Semiconductor, Inc. | Method for voltage drop analysis in integreted circuits |
US7477999B2 (en) * | 2006-10-26 | 2009-01-13 | Samplify Systems, Inc. | Data compression for a waveform data analyzer |
US7937256B2 (en) * | 2006-12-02 | 2011-05-03 | Altos Design Automation, Inc. | Systems and methods of efficient library characterization for integrated circuit cell libraries |
US7809542B2 (en) * | 2007-05-07 | 2010-10-05 | International Business Machines Corporation | System and method for glitch analysis in circuits |
EP2006784A1 (en) | 2007-06-22 | 2008-12-24 | Interuniversitair Microelektronica Centrum vzw | Methods for characterization of electronic circuits under process variability effects |
JP4422179B2 (ja) * | 2007-10-19 | 2010-02-24 | 株式会社半導体理工学研究センター | 半導体集積回路のタイミング解析装置及び方法 |
US7849430B2 (en) * | 2008-03-24 | 2010-12-07 | Oracle America, Inc. | Reverse donut model |
US8108194B2 (en) * | 2008-04-25 | 2012-01-31 | Cadence Design Systems, Inc. | Peak power detection in digital designs using emulation systems |
US8452581B2 (en) | 2009-05-05 | 2013-05-28 | Oracle America, Inc. | Technique using power macromodeling for register transfer level power estimation |
US8527911B1 (en) * | 2009-06-09 | 2013-09-03 | Jasper Design Automation, Inc. | Comprehending a circuit design |
CN102169515B (zh) * | 2010-02-26 | 2014-04-16 | 国际商业机器公司 | 一种专用集成电路中时钟树延迟时间的估计方法和系统 |
CN102314525B (zh) * | 2010-06-30 | 2013-03-20 | 中国科学院微电子研究所 | 一种低功耗电路设计优化方法 |
US8612911B2 (en) | 2011-02-23 | 2013-12-17 | International Business Machines Corporation | Estimating power consumption of an electronic circuit |
US8407654B2 (en) | 2011-02-23 | 2013-03-26 | International Business Machines Corporation | Glitch power reduction |
CN102799698B (zh) * | 2011-05-26 | 2014-07-23 | 国际商业机器公司 | 一种用于专用集成电路的时钟树规划的方法和系统 |
US8438520B2 (en) * | 2011-08-29 | 2013-05-07 | International Business Machines Corporation | Early decoupling capacitor optimization method for hierarchical circuit design |
US8566767B1 (en) * | 2011-11-23 | 2013-10-22 | Cadence Design Systems, Inc. | System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation |
JP5949933B2 (ja) * | 2012-10-24 | 2016-07-13 | 富士通株式会社 | シミュレーションプログラム、シミュレーション装置およびシミュレーション方法 |
-
2013
- 2013-10-31 CN CN201310530202.2A patent/CN104598659B/zh not_active Expired - Fee Related
-
2014
- 2014-10-27 US US14/524,413 patent/US10146895B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5768145A (en) * | 1996-06-11 | 1998-06-16 | Lsi Logic Corporation | Parametrized waveform processor for gate-level power analysis tool |
Non-Patent Citations (1)
Title |
---|
IEEE Standard for Standard Delay Format(SDF) for the Electronic Design Process;IEEE Computer Society;《IEEE Standard》;20011214;第8页,4.5.4节,第3段 * |
Also Published As
Publication number | Publication date |
---|---|
US10146895B2 (en) | 2018-12-04 |
US20150120268A1 (en) | 2015-04-30 |
CN104598659A (zh) | 2015-05-06 |
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