CN102467583B - 追踪不确定信号的方法和装置 - Google Patents
追踪不确定信号的方法和装置 Download PDFInfo
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- CN102467583B CN102467583B CN201010532265.8A CN201010532265A CN102467583B CN 102467583 B CN102467583 B CN 102467583B CN 201010532265 A CN201010532265 A CN 201010532265A CN 102467583 B CN102467583 B CN 102467583B
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- signal
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- logic device
- sequential logic
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
Description
Claims (18)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010532265.8A CN102467583B (zh) | 2010-10-29 | 2010-10-29 | 追踪不确定信号的方法和装置 |
US13/280,853 US8490037B2 (en) | 2010-10-29 | 2011-10-25 | Method and apparatus for tracking uncertain signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201010532265.8A CN102467583B (zh) | 2010-10-29 | 2010-10-29 | 追踪不确定信号的方法和装置 |
Publications (2)
Publication Number | Publication Date |
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CN102467583A CN102467583A (zh) | 2012-05-23 |
CN102467583B true CN102467583B (zh) | 2014-07-23 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201010532265.8A Active CN102467583B (zh) | 2010-10-29 | 2010-10-29 | 追踪不确定信号的方法和装置 |
Country Status (2)
Country | Link |
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US (1) | US8490037B2 (zh) |
CN (1) | CN102467583B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9141738B2 (en) * | 2012-06-04 | 2015-09-22 | Reveal Design Automation | Sequential non-deterministic detection in hardware design |
CN104636509B (zh) * | 2013-11-08 | 2019-05-28 | 恩智浦美国有限公司 | 门级仿真中验证时序问题的系统及方法 |
CN114510866B (zh) * | 2021-12-08 | 2023-04-18 | 芯华章科技股份有限公司 | 用于追踪逻辑系统设计的错误的方法及相关设备 |
CN114692551A (zh) * | 2022-03-22 | 2022-07-01 | 中国科学院大学 | 一种Verilog设计文件安全关键信号的检测方法 |
Citations (3)
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CN1399724A (zh) * | 1999-09-24 | 2003-02-26 | 明导公司 | 仿真系统中使用的具有集成调试功能的可重构集成电路 |
US7184936B1 (en) * | 2004-07-12 | 2007-02-27 | Cisco Technology, Inc. | Timing variation measurement system and method |
CN101165694A (zh) * | 2006-10-20 | 2008-04-23 | 国际商业机器公司 | 专用集成电路中i/o块的优化布置和验证的方法和装置 |
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WO2000057317A1 (en) * | 1999-03-19 | 2000-09-28 | Moscape, Inc. | System and method for performing assertion-based analysis of circuit designs |
US6415430B1 (en) * | 1999-07-01 | 2002-07-02 | Nec Usa, Inc. | Method and apparatus for SAT solver architecture with very low synthesis and layout overhead |
US6536019B1 (en) * | 2000-09-28 | 2003-03-18 | Verisity Design, Inc. | Race condition detection and expression |
US20020178427A1 (en) * | 2001-05-25 | 2002-11-28 | Cheng-Liang Ding | Method for improving timing behavior in a hardware logic emulation system |
US7356689B2 (en) * | 2001-07-09 | 2008-04-08 | Lucent Technologies Inc. | Method and apparatus for tracing packets in a communications network |
US7224689B2 (en) * | 2001-08-17 | 2007-05-29 | Sun Microsystems, Inc. | Method and apparatus for routing of messages in a cycle-based system |
US6810507B2 (en) | 2002-01-17 | 2004-10-26 | Sun Microsystems, Inc. | Method and apparatus for isolating the root of indeterminate logic values in an HDL simulation |
US20040093198A1 (en) * | 2002-11-08 | 2004-05-13 | Carbon Design Systems | Hardware simulation with access restrictions |
US7237214B1 (en) * | 2003-03-04 | 2007-06-26 | Synplicity, Inc. | Method and apparatus for circuit partitioning and trace assignment in circuit design |
US7742907B2 (en) * | 2003-04-15 | 2010-06-22 | Nec Laboratories America, Inc. | Iterative abstraction using SAT-based BMC with proof analysis |
US7356672B2 (en) * | 2004-05-28 | 2008-04-08 | The Regents Of The University Of California | Warp processor for dynamic hardware/software partitioning |
US7146583B1 (en) * | 2004-08-06 | 2006-12-05 | Xilinx, Inc. | Method and system for implementing a circuit design in a tree representation |
US7398494B2 (en) | 2005-08-30 | 2008-07-08 | International Business Machines Corporation | Method for performing verification of logic circuits |
US20070088717A1 (en) * | 2005-10-13 | 2007-04-19 | International Business Machines Corporation | Back-tracking decision tree classifier for large reference data set |
US20080072182A1 (en) * | 2006-09-19 | 2008-03-20 | The Regents Of The University Of California | Structured and parameterized model order reduction |
US20080115099A1 (en) * | 2006-11-15 | 2008-05-15 | Priyadarsan Patra | Spatial curvature for multiple objective routing |
US7543266B2 (en) * | 2006-11-20 | 2009-06-02 | Microsoft Corporation | Lock-free state merging in parallelized constraint satisfaction problem solvers |
US7725863B2 (en) * | 2007-02-27 | 2010-05-25 | Agate Logic, Inc. | Reverse routing methods for integrated circuits having a hierarchical interconnect architecture |
US8839218B2 (en) * | 2007-06-04 | 2014-09-16 | International Business Machines Corporation | Diagnosing alias violations in memory access commands in source code |
US7707530B2 (en) * | 2007-11-16 | 2010-04-27 | International Business Machines Corporation | Incremental timing-driven, physical-synthesis using discrete optimization |
US7934183B2 (en) | 2008-04-25 | 2011-04-26 | Synopsys, Inc. | Method and apparatus for simulating behavioral constructs using indeterminate values |
US8024168B2 (en) | 2008-06-13 | 2011-09-20 | International Business Machines Corporation | Detecting X state transitions and storing compressed debug information |
US7958472B2 (en) | 2008-09-30 | 2011-06-07 | Synopsys, Inc. | Increasing scan compression by using X-chains |
US8484590B2 (en) * | 2009-06-02 | 2013-07-09 | Jesse Conrad Newcomb | Method of predicting electronic circuit floating gates |
US8200693B2 (en) * | 2009-06-26 | 2012-06-12 | Fair Isaac Corporation | Decision logic comparison and review |
CN102169515B (zh) * | 2010-02-26 | 2014-04-16 | 国际商业机器公司 | 一种专用集成电路中时钟树延迟时间的估计方法和系统 |
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2010
- 2010-10-29 CN CN201010532265.8A patent/CN102467583B/zh active Active
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2011
- 2011-10-25 US US13/280,853 patent/US8490037B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1399724A (zh) * | 1999-09-24 | 2003-02-26 | 明导公司 | 仿真系统中使用的具有集成调试功能的可重构集成电路 |
US7184936B1 (en) * | 2004-07-12 | 2007-02-27 | Cisco Technology, Inc. | Timing variation measurement system and method |
CN101165694A (zh) * | 2006-10-20 | 2008-04-23 | 国际商业机器公司 | 专用集成电路中i/o块的优化布置和验证的方法和装置 |
Also Published As
Publication number | Publication date |
---|---|
US8490037B2 (en) | 2013-07-16 |
US20120110526A1 (en) | 2012-05-03 |
CN102467583A (zh) | 2012-05-23 |
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Effective date of registration: 20171024 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. Effective date of registration: 20171024 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC |
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Effective date of registration: 20230804 Address after: Taiwan, Hsinchu, China Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd. Address before: Grand Cayman, Cayman Islands Patentee before: GLOBALFOUNDRIES INC. |