CN102163463B - Double coin search method for reducing BCH (broadcast channel) decoding delay - Google Patents
Double coin search method for reducing BCH (broadcast channel) decoding delay Download PDFInfo
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- CN102163463B CN102163463B CN 201110105601 CN201110105601A CN102163463B CN 102163463 B CN102163463 B CN 102163463B CN 201110105601 CN201110105601 CN 201110105601 CN 201110105601 A CN201110105601 A CN 201110105601A CN 102163463 B CN102163463 B CN 102163463B
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Abstract
The invention relates to a double coin search method for reducing BCH (broadcast channel) decoding delay, comprising the following steps of: reading an NAND FLASH, carrying out syndrome calculation on BCH code data with 528 bytes in each group by virtue of a syndrome calculation circuit 2, the delay caused by the syndrome technology to a read operation is 0, and the delay of coin search to a decoding operation is reduced by utilizing the facts that the numbers of errors of BCH code data have different occurrence probabilities and the area overhead is extremely low, as the probability of single error is far higher than the probability of multiple errors, a coin search circuit with higher degree of parallelism is used for correction of the single error, and the coin search circuit with lower degree of parallelism is used for correction of multiple errors. When one BCH code data error is produced, the double coin search circuit 5 executes a parallel coin search circuit 16, and when more than one BCH code data errors are produced, the double coin search circuit 5 executes a parallel coin search circuit 8. Thus the BCH decoding delay can be greatly reduced.
Description
Technical field
The invention belongs to NAND FLASH error-correcting code technique field, be specifically related to a kind of two chien search methods of the BCH of reduction decoding delay.
Background technology
NAND Flash claims again " quickflashing ", originates from the eighties in 20th century, is a kind of of nonvolatile memory.In recent years, because NAND Flash high power capacity, characteristics cheaply, application surface is gradually wide, and nearly all consumption electronic product such as USB flash disk, mp3, mp4, digital camera and mobile phone etc., all be unable to do without NANDFlash.Can say, as long as relate to the place of mass data storage, just bound NAND Flash.
Because the singularity of NAND Flash physical arrangement, when data store on the NAND Flash, may produce other bit reversal, thereby causing storing data makes mistakes, so in order to improve the reliability of the data, need to before storage, carry out suitable coding to data, to guarantee that system can correct it when data are made mistakes.Forward error correction is to use maximum a kind of error correcting systems in the storage system, often adopts the linear block codess such as Hamming, BCH and RS as error correcting code, improves the data storing reliability of system.
Early stage NAND Flash substantially is single layer cell (SLC) type, and technique is relatively ripe, and the probability that data are made mistakes in the storing process is little, generally adopts Hamming code as the ECC error correcting code, can satisfy system requirements.Progress along with NAND Flash designing technique and technique, NAND Flash is multilevel-cell (MLC) structure from single layer cell (SLC) Structure Transformation, can store the Bit data more than 2 on each storage unit, it is large that impact between the bit becomes, error probability increases, and along with making technology reaches 32nm, the various charge effects under the sub-micro have further increased the possibility that data are made mistakes.So the Hamming code of monobit errro correction can't satisfy the requirement of ECC error correction system far away.
Summary of the invention
In order to overcome the deficiency of above-mentioned prior art existence, the object of the present invention is to provide a kind of two chien search methods of the BCH of reduction decoding delay, can greatly reduce the decoding time-delay of BCH.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of two chien search methods that reduce the BCH decoding delay, set in advance the BCH code translator, this BCH code translator comprises the single-ended RAM3 as the data buffer that mutually communicates to connect with its first order code translator and second level code translator, first order code translator is read flash controller 1 and syndrome counting circuit 2 for mutual communication connection, second level code translator is to be the mutual nothing of the communication connection BM iterative algorithm unit 4 of inverting in twos successively, Chien search circuit 5 and output buffer memory 6, the wherein nothing of second level code translator syndrome counting circuit 2 communication connection of BM iterative algorithm unit 4 with first order code translator of inverting, when carrying out the BCH decoding, successively read continuously the BCH code data by reading flash controller 1 according to once reading the rule of pool-size size for the BCH code data of 528Bytes, when reading the BCH code data BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit 2 calculates, and the BCH code deposit data that reads is entered single-ended RAM3, after single-ended RAM3 is filled with the BCH code data, syndrome counting circuit 2 is carried out syndrome calculate the corresponding syndrome input of the BCH code data of trying to achieve without inverting BM iterative algorithm unit 4, and by the error polynomial that calculates BCH code without this syndrome of BM iterative algorithm unit 4 usefulness of inverting, then the error polynomial of BCH code and the BCH code data in the single-ended RAM3 are transferred to two Chien search circuits 5 and finished search to BCH code in the BCH code data, and the BCH code data are transplanted on output buffer memory 6 in the single-ended RAM3, export at last buffer memory 6 the BCH code data of correspondence are delivered to bus interface 7.
The described mode that the BCH code deposit data that reads is entered single-ended RAM3 is divided into 4 sectors for the physical space with every page of 2KB of NAND FLASH, each sector is the 528B size, one group of corresponding BCH code data of each sector storage, the 512B storage unit is used for the data message 8 of storage BCH code data before this sector, and the 16B storage unit is used for BCH code data storage check bit 9 thereafter, single wrong probability occurs so and greatly improves.Because the data field is consistent with the free area in physical arrangement, so adopt which kind of storage mode can not exert an influence to the data reliability.
The quantity of BCH code error in data can be judged in the described nothing BM iterative algorithm unit 4 of inverting by the calculating of syndrome, when the quantity of BCH code error in data is 1, two Chien search circuits 5 adopt 16 road parallel Chien search circuit, when the quantity of BCH code error in data greater than 1 the time, two Chien search circuits 5 adopt 8 road parallel Chien search circuit.
Calculate by when reading NAND FLASH, the BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit 2, the time-delay that brings to read operation because of the syndrome technology is 0, utilize the probability of occurrence of BCH code error in data quantity different, reduce chien search to the time-delay of decoded operation with minimum area overhead, be far longer than the probability that a plurality of mistakes occur owing to the probability of single error occurring, the Chien search circuit that degree of parallelism is higher is used for correcting single wrong, and the Chien search circuit that degree of parallelism is lower is used for correcting a plurality of mistakes.When the quantity of BCH code error in data was 1, Chien search circuit 5 was carried out 16 road parallel Chien search circuit, when the quantity of BCH code error in data greater than 1 the time, Chien search circuit 5 is carried out 8 road parallel Chien search circuit.So just can greatly reduce the BCH decoding delay.
Description of drawings
Fig. 1 is the structural representation of a sector of NAND FLASH 2K page or leaf of the present invention.
Fig. 2 is principle of work control flow chart of the present invention.
Fig. 3 is work schedule coordinate diagram of the present invention, and the square on the coordinate represents shared time span.
Embodiment
The present invention will be described in more detail below in conjunction with accompanying drawing.
As shown in Figure 2, reduce two chien search methods of BCH decoding delay, set in advance the BCH code translator, this BCH code translator comprises the single-ended RAM3 as the data buffer that mutually communicates to connect with its first order code translator and second level code translator, first order code translator is read flash controller 1 and syndrome counting circuit 2 for mutual communication connection, second level code translator is to be the mutual nothing of the communication connection BM iterative algorithm unit 4 of inverting in twos successively, Chien search circuit 5 and output buffer memory 6, the wherein nothing of second level code translator syndrome counting circuit 2 communication connection of BM iterative algorithm unit 4 with first order code translator of inverting, when carrying out the BCH decoding, successively read continuously the BCH code data by reading flash controller 1 according to once reading the rule of pool-size size for the BCH code data of 528Bytes, as shown in Figure 3, when reading the BCH code data BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit 2 calculates, and the BCH code deposit data that reads is entered single-ended RAM3, after single-ended RAM3 is filled with by the BCH code data, syndrome counting circuit 2 is carried out syndrome calculate the corresponding syndrome input of the BCH code data of trying to achieve without inverting BM iterative algorithm unit 4, and by the error polynomial that calculates BCH code without this syndrome of BM iterative algorithm unit 4 usefulness of inverting, then the error polynomial of BCH code and the BCH code data in the single-ended RAM3 are transferred to Chien search circuit 5 and finished search to BCH code in the BCH code data, and the BCH code data are transplanted on output buffer memory 6 in the single-ended RAM3, export at last buffer memory 6 the BCH code data of correspondence are delivered to bus interface 7.The described mode that the BCH code deposit data that reads is entered single-ended RAM3 is divided into 4 sectors for the physical space with every page of 2KB of NAND FLASH, as shown in Figure 1, each sector is the 528B size, one group of corresponding BCH code data of each sector storage, the 512B storage unit is used for the data message 8 of storage BCH code data before this sector, and the 16B storage unit is used for BCH code data storage check bit 9 thereafter.The BCH code of described BCH code data (8191,8087,8) has from α
1To α
81918191 element positions, these 8191 element positions respectively corresponding codeword number are from γ
8190To γ
0, and the code element that Chien search circuit 5 uses is γ
0 arrivesγ
4223, it is α that the traversal starting point is set
3968, specifically by an X α
3968Constant multiplier is realized.The quantity of BCH code error in data can be judged in the described nothing BM iterative algorithm unit 4 of inverting by the calculating of syndrome, when the quantity of BCH code error in data is 1, two Chien search circuits 5 are carried out 16 road parallel Chien search circuit, when the quantity of BCH code error in data greater than 1 the time, two Chien search circuits 5 are carried out 8 road parallel Chien search circuit.
Claims (3)
1. two chien search methods that reduce the BCH decoding delay, it is characterized in that: set in advance the BCH code translator, this BCH code translator comprises the single-ended RAM(3 as the data buffer that mutually communicates to connect with its first order code translator and second level code translator), first order code translator is read flash controller (1) and syndrome counting circuit (2) for mutual communication connection, second level code translator is without inverting BM iterative algorithm unit (4), two Chien search circuits (5) and output buffer memory (6), wherein without BM iterative algorithm unit (4) and the mutually communication connection of two Chien search circuits (5) of inverting, two Chien search circuits (5) and mutually communication connection of output buffer memory (6), without syndrome counting circuit (2) communication connection of BM iterative algorithm unit (4) with first order code translator of inverting, when carrying out the BCH decoding, successively read continuously the BCH code data by reading flash controller (1) according to once reading the rule of pool-size size for the BCH code data of 528Bytes, when reading the BCH code data BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit (2) calculates, and the BCH code deposit data that reads is entered single-ended RAM(3), after single-ended RAM3 is filled with by the BCH code data, syndrome counting circuit (2) is carried out syndrome calculate the corresponding syndrome input of the BCH code data of trying to achieve without inverting BM iterative algorithm unit (4), and by the error polynomial that calculates BCH code without the BM iterative algorithm unit (4) of inverting with this syndrome, then the error polynomial of BCH code and the BCH code data in the single-ended RAM3 are transferred to two Chien search circuits (5) and finished search to BCH code in the BCH code data, and the BCH code data are transplanted on output buffer memory (6) in the single-ended RAM3, export at last buffer memory (6) the BCH code data of correspondence are delivered to bus interface (7).
2. two chien search methods of reduction according to claim 1 BCH decoding delay, it is characterized in that: described the BCH code deposit data that reads is entered single-ended RAM(3) mode be divided into 4 sectors for the physical space with every page of 2KB of NANDFLASH, each sector is the 528B size, one group of corresponding BCH code data of each sector storage, the 512B storage unit is used for the data message (8) of storage BCH code data before this each sector, and the 16B storage unit is used for BCH code data storage check bit (9) thereafter.
3. according to claim 1 or two chien search methods of reduction claimed in claim 2 BCH decoding delay, it is characterized in that: the quantity of BCH code error in data can be judged in the described nothing BM iterative algorithm unit (4) of inverting by the calculating of syndrome, when the quantity of BCH code error in data is 1, two Chien search circuits (5) are carried out 16 road parallel Chien search circuit, when the quantity of BCH code error in data greater than 1 the time, two Chien search circuits (5) are carried out 8 road parallel Chien search circuit.
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| CN112099986B (en) * | 2020-08-11 | 2022-02-01 | 西安电子科技大学 | ECC decoding system and method of branch pipeline structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1688110A (en) * | 2005-06-09 | 2005-10-26 | 上海交通大学 | Reed solomon decoder based on CAM |
| CN101174838A (en) * | 2006-11-01 | 2008-05-07 | 富士通株式会社 | Maximum likelihood detector, error correction circuit and medium storage device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1688110A (en) * | 2005-06-09 | 2005-10-26 | 上海交通大学 | Reed solomon decoder based on CAM |
| CN101174838A (en) * | 2006-11-01 | 2008-05-07 | 富士通株式会社 | Maximum likelihood detector, error correction circuit and medium storage device |
Non-Patent Citations (2)
| Title |
|---|
| 侯毅等.多码率RS码部分并行译码结构设计.《北京航空航天大学学报》.2010,第36卷(第7期), * |
| 张亮等.高速光通信中的级联码设计与VLSI实现.《电路与系统学报》.2010,第15卷(第2期), * |
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