CN102163463A

CN102163463A - Double coin search method for reducing BCH (broadcast channel) decoding delay

Info

Publication number: CN102163463A
Application number: CN 201110105601
Authority: CN
Inventors: 孙宏滨; 牛众品; 郑南宁
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2011-04-26
Filing date: 2011-04-26
Publication date: 2011-08-24
Anticipated expiration: 2031-04-26
Also published as: CN102163463B

Abstract

The invention relates to a double coin search method for reducing BCH (broadcast channel) decoding delay, comprising the following steps of: reading an NAND FLASH, carrying out syndrome calculation on BCH code data with 528 bytes in each group by virtue of a syndrome calculation circuit 2, the delay caused by the syndrome technology to a read operation is 0, and the delay of coin search to a decoding operation is reduced by utilizing the facts that the numbers of errors of BCH code data have different occurrence probabilities and the area overhead is extremely low, as the probability of single error is far higher than the probability of multiple errors, a coin search circuit with higher degree of parallelism is used for correction of the single error, and the coin search circuit with lower degree of parallelism is used for correction of multiple errors. When one BCH code data error is produced, the double coin search circuit 5 executes a parallel coin search circuit 16, and when more than one BCH code data errors are produced, the double coin search circuit 5 executes a parallel coin search circuit 8. Thus the BCH decoding delay can be greatly reduced.

Description

A kind of two chien search methods that reduce the BCH decoding delay

Technical field

The invention belongs to NAND FLASH error-correcting code technique field, be specifically related to a kind of two chien search methods of the BCH of reduction decoding delay.

Background technology

NAND Flash claims " quickflashing " again, originates from the eighties in 20th century, is a kind of of nonvolatile memory.In recent years, because NAND Flash high power capacity, characteristics cheaply, application surface is gradually wide, and nearly all consumption electronic product as USB flash disk, mp3, mp4, digital camera and mobile phone etc., all be unable to do without NANDFlash.We can say, as long as relate to the place of mass data storage, just bound NAND Flash.

Because the singularity of NAND Flash physical arrangement, when data storage is to NAND Flash, may produce other bit reversal, thereby causing storing data makes mistakes, so in order to improve the reliability of data, need before storage, carry out suitable coding, to guarantee that system can correct it when data are made mistakes to data.Forward error correction is to use maximum a kind of error correcting systems in the storage system, often adopts linear block codess such as Hamming, BCH and RS as error correcting code, improves the data storing reliability of system.

Early stage NAND Flash substantially is single layer cell (SLC) type, and technology is ripe relatively, and the data probability of errors is little in the storing process, generally adopts Hamming code as the ECC error correcting code, can satisfy system requirements.Progress along with NAND Flash designing technique and technology, NAND Flash is multilevel-cell (MLC) structure from single layer cell (SLC) structural transformation, can store the Bit data more than 2 on each storage unit, it is big that influence between the bit becomes, error probability increases, and along with making technology reaches 32nm, the various charge effects under the sub-micro have further increased the possibility that data are made mistakes.So the Hamming code of monobit errro correction can't satisfy the requirement of ECC error correction system far away.

Summary of the invention

In order to overcome the deficiency that above-mentioned prior art exists, the object of the present invention is to provide a kind of two chien search methods of the BCH of reduction decoding delay, can reduce the decoding time-delay of BCH greatly.

In order to achieve the above object, the technical solution adopted in the present invention is:

A kind of two chien search methods that reduce the BCH decoding delay, set in advance the BCH code translator, this BCH code translator comprises the single-ended RAM3 as the data buffer that communicates to connect mutually with its first order code translator and second level code translator, first order code translator is read flash controller 1 and syndrome counting circuit 2 for what communicate to connect mutually, second level code translator is to be the nothing that communicates to connect the mutually in twos successively BM iterative algorithm unit 4 of inverting, chien search circuit 5 and output buffers 6, wherein the nothing of the second level code translator BM iterative algorithm unit 4 of inverting communicates to connect with the syndrome counting circuit 2 of first order code translator, when carrying out the BCH decoding, read the BCH code data by reading flash controller 1 continuously according to once reading the rule of pool-size size for the BCH code data of 528Bytes one by one, when reading the BCH code data BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit 2 calculates, and the BCH code deposit data that reads is gone into single-ended RAM3, after single-ended RAM3 is filled with the BCH code data, syndrome counting circuit 2 is carried out syndrome to be calculated the pairing syndrome input of the BCH code data tried to achieve and not to have the BM iterative algorithm unit 4 of inverting, and calculate the wrong polynomial expression of BCH code by nothing this syndrome of BM iterative algorithm unit 4 usefulness of inverting, then the wrong polynomial expression of BCH code and the BCH code data in the single-ended RAM3 are transferred to two chien search circuit 5 and finished search BCH code in the BCH code data, and the BCH code data are transplanted on output buffers 6 in single-ended RAM3, last output buffers 6 is delivered to bus interface 7 with the BCH code data of correspondence.

Described mode of the BCH code deposit data that reads being gone into single-ended RAM3 is divided into 4 sectors for the physical space with every page of 2KB of NAND FLASH, each sector is the 528B size, the BCH code data of one group of correspondence of each sector storage, the 512B storage unit is used to store the data message 8 of BCH code data before this sector, and the 16B storage unit is used for the storage check bit 9 of BCH code data thereafter, occurs single wrong probability so and improves greatly.Because the data field is consistent on physical arrangement with the free area, so adopt which kind of storage mode can not exert an influence to the data reliability.

The quantity of BCH code error in data can be judged in the described nothing BM iterative algorithm unit 4 of inverting by the calculating of syndrome, when the quantity of BCH code error in data is 1, two chien search circuit 5 adopt 16 tunnel parallel chien search circuit, when the quantity of BCH code error in data greater than 1 the time, two chien search circuit 5 adopt 8 tunnel parallel chien search circuit.

Calculate by when reading NAND FLASH, the BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit 2, the time-delay that brings to read operation because of the syndrome technology is 0, utilize the probability of occurrence difference of BCH code error in data quantity, reduce the time-delay of chien search with minimum area overhead to decoded operation, be far longer than the probability that a plurality of mistakes occur owing to the probability of single error occurs, the higher chien search circuit of degree of parallelism is used to correct single mistake, and the chien search circuit that degree of parallelism is lower is used to correct a plurality of mistakes.When the quantity of BCH code error in data was 1, chien search circuit 5 was carried out 16 tunnel parallel chien search circuit, when the quantity of BCH code error in data greater than 1 the time, chien search circuit 5 is carried out 8 tunnel parallel chien search circuit.So just can greatly reduce the BCH decoding delay.

Description of drawings

Fig. 1 is the structural representation of a sector of NAND FLASH 2K page or leaf of the present invention.

Fig. 2 is a principle of work control flow chart of the present invention.

Fig. 3 is a work schedule coordinate diagram of the present invention, and the square on the coordinate is represented shared time span.

Embodiment

The present invention will be described in more detail below in conjunction with accompanying drawing.

As shown in Figure 2, reduce two chien search methods of BCH decoding delay, set in advance the BCH code translator, this BCH code translator comprises the single-ended RAM3 as the data buffer that communicates to connect mutually with its first order code translator and second level code translator, first order code translator is read flash controller 1 and syndrome counting circuit 2 for what communicate to connect mutually, second level code translator is to be the nothing that communicates to connect the mutually in twos successively BM iterative algorithm unit 4 of inverting, chien search circuit 5 and output buffers 6, wherein the nothing of the second level code translator BM iterative algorithm unit 4 of inverting communicates to connect with the syndrome counting circuit 2 of first order code translator, when carrying out the BCH decoding, read the BCH code data by reading flash controller 1 continuously according to once reading the rule of pool-size size for the BCH code data of 528Bytes one by one, as shown in Figure 3, when reading the BCH code data BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit 2 calculates, and the BCH code deposit data that reads is gone into single-ended RAM3, after single-ended RAM3 is filled with by the BCH code data, syndrome counting circuit 2 is carried out syndrome to be calculated the pairing syndrome input of the BCH code data tried to achieve and not to have the BM iterative algorithm unit 4 of inverting, and calculate the wrong polynomial expression of BCH code by nothing this syndrome of BM iterative algorithm unit 4 usefulness of inverting, then the wrong polynomial expression of BCH code and the BCH code data in the single-ended RAM3 are transferred to chien search circuit 5 and finished search BCH code in the BCH code data, and the BCH code data are transplanted on output buffers 6 in single-ended RAM3, last output buffers 6 is delivered to bus interface 7 with the BCH code data of correspondence.Described mode of the BCH code deposit data that reads being gone into single-ended RAM3 is divided into 4 sectors for the physical space with every page of 2KB of NAND FLASH, as shown in Figure 1, each sector is the 528B size, the BCH code data of one group of correspondence of each sector storage, the 512B storage unit is used to store the data message 8 of BCH code data before this sector, and the 16B storage unit is used for the storage check bit 9 of BCH code data thereafter.The BCH code of described BCH code data (8191,8087,8) has from α ¹To α ⁸¹⁹¹8191 element positions, codeword number that these 8191 element positions are corresponding respectively are from γ ₈₁₉₀To γ ₀, and the code element that chien search circuit 5 uses is γ _{0 arrives}γ ₄₂₂₃, it is α that the traversal starting point is set ³⁹⁶⁸, specifically by an X α ³⁹⁶⁸Constant multiplier is realized.The quantity of BCH code error in data can be judged in the described nothing BM iterative algorithm unit 4 of inverting by the calculating of syndrome, when the quantity of BCH code error in data is 1, two chien search circuit 5 are carried out 16 tunnel parallel chien search circuit, when the quantity of BCH code error in data greater than 1 the time, two chien search circuit 5 are carried out 8 tunnel parallel chien search circuit.

Claims

1. two chien search methods that reduce the BCH decoding delay, it is characterized in that: set in advance the BCH code translator, this BCH code translator comprises the single-ended RAM (3) as the data buffer that communicates to connect mutually with its first order code translator and second level code translator, first order code translator is read flash controller (1) and syndrome counting circuit (2) for what communicate to connect mutually, second level code translator is to be the nothing that communicates to connect the mutually in twos successively BM iterative algorithm unit (4) of inverting, chien search circuit (5) and output buffers (6), wherein the nothing of the second level code translator BM iterative algorithm unit (4) of inverting communicates to connect with the syndrome counting circuit (2) of first order code translator, when carrying out the BCH decoding, read the BCH code data by reading flash controller (1) continuously according to once reading the rule of pool-size size for the BCH code data of 528Bytes one by one, when reading the BCH code data BCH code data of every group of 528Bytes being carried out syndrome via syndrome counting circuit (2) calculates, and the BCH code deposit data that reads is gone into single-ended RAM (3), after single-ended RAM3 is filled with by the BCH code data, syndrome counting circuit (2) is carried out syndrome to be calculated the pairing syndrome input of the BCH code data tried to achieve and not to have the BM iterative algorithm unit (4) of inverting, and calculate the wrong polynomial expression of BCH code with this syndrome by the nothing BM iterative algorithm unit (4) of inverting, then the wrong polynomial expression of BCH code and the BCH code data in the single-ended RAM3 are transferred to chien search circuit (5) and finished search BCH code in the BCH code data, and the BCH code data are transplanted on output buffers (6) in single-ended RAM3, last output buffers (6) is delivered to bus interface (7) with the BCH code data of correspondence.

2. two chien search methods of reduction BCH decoding delay according to claim 1, it is characterized in that: the described mode that the BCH code deposit data that reads is gone into single-ended RAM (3) is divided into 4 sectors for the physical space with every page of 2KB of NANDFLASH, each sector is the 528B size, the BCH code data of one group of correspondence of each sector storage, the 512B storage unit is used to store the data message (8) of BCH code data before this sector, and the 16B storage unit is used for the storage check bit (9) of BCH code data thereafter.

3. according to two chien search methods of claim 1 or the described reduction of claim 2 BCH decoding delay, it is characterized in that: the BCH code of described BCH code data (8191,8087,8) has from α ¹To α ⁸¹⁹¹8191 element positions, codeword number that these 8191 element positions are corresponding respectively are from γ ₈₁₉₀To γ ₀, and the code element that chien search circuit (5) uses is γ _{0 arrives}γ ₄₂₂₃, it is α that the traversal starting point is set ³⁹⁶⁸, specifically by an X α ³⁹⁶⁸Constant multiplier is realized.

4. according to claim 1 or the described two chien search methods that reduce the BCH decoding delay of claim 2, it is characterized in that: the quantity of BCH code error in data can be judged in the described nothing BM iterative algorithm unit (4) of inverting by the calculating of syndrome, when the quantity of BCH code error in data is 1, two chien search circuit (5) are carried out 16 tunnel parallel chien search circuit, when the quantity of BCH code error in data greater than 1 the time, two chien search circuit (5) are carried out 8 tunnel parallel chien search circuit.