CN104464821B

CN104464821B - It is a kind of to prevent MLC Nand Flash from the method for UECC problems occur

Info

Publication number: CN104464821B
Application number: CN201410530983.XA
Authority: CN
Inventors: 肖锐; 方浩俊; 胡颖颖
Original assignee: Ramaxel Technology Shenzhen Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2014-10-10
Filing date: 2014-10-10
Publication date: 2017-07-28
Anticipated expiration: 2034-10-10
Also published as: CN104464821A

Abstract

Prevent MLC Nand Flash from the method for UECC problems occur the invention discloses a kind of, the operational order that system is accessed into MLC Nand Flash is accessed according to MLC Nand Flash storage organization in units of page, high bit page is stored for upper page, the page of low bit of storage is lower page；First judge whether current page is upper page before page operations are write, it is true if it is to set and read delay designations Need_delay, and record present system time Timestamp_write, it is flase to read delay designations if not then setting；First judge whether Need_delay is true before page operations are read, if true, then the time difference of present system time and the Timestamp_write of record is calculated, judge whether the time difference is more than safe time interval, the delay operation if being not more than, then perform read command operation；If Need_delay is flase, read command operation is directly carried out.Situation for easily producing bit upsets during read-write operation, optimizes the operating process of read-write operation order, is effectively reduced the problem of bit upsets and UECC occurs in large area, so as to effectively raise the validity for reading data.

Description

It is a kind of to prevent MLC Nand Flash from the method for UECC problems occur

Technical field

The present invention relates to a kind of Flash technology, more particularly to one kind prevents MLC Nand Flash from going out in read operation The method of existing UECC problems.

Background technology

MLC Nand Flash have higher storage density with respect to SLC Nand flash, have more in solid state hard disc field To be more widely applied.

Fig. 1 is NAND FLASH MEMORY CELL structure charts, is divided into source electrode (Source), is drained (Drain), control gate Pole (Control Gate) and floating grid (Floating Gate).Electric charge is injected into floating boom to represent to be written with " 0 ", is not noted Enter electric charge to represent to be written with " 1 ", erasing operation is exactly to discharge the electric charge in floating boom, injection electric charge has two ways, thermoelectricity Son injection (Hot Electron Injection) and F-N tunnel-effects (Fowler Nordheim Tunneling).Former It is to be charged by source electrode to floating boom, latter is to be charged by silicon base layer to floating boom, and Nor Flash are injected by thermoelectric regime Electric charge, Nand Flash are then charged by F-N tunnel-effects to floating boom.For having the unit of electric charge in floating boom, due to floating The induction effect of grid, forms the space-charge region of positively charged between source electrode and drain electrode, at this moment no matter in control pole either with or without adding Bias voltage, transistor all will be in the conduction state, and only works as control pole for not having the transistor of electric charge in floating boom Appropriate bias voltage is applied with, electric charge is induced on silicon base layer, source electrode and drain electrode could be turned on, and also just be said no to control When pole processed applies bias voltage, what transistor was off.One cell can represent the Flash referred to as MLC of 2Bit data (Multi-Level Cell), MLC can represent " 00 ", " 10 ", " 01 ", " 11 ".

Fig. 2 is NAND FLASH BLOCK structural representations, and MLC Nand Flash particles are made up of multiple pieces of Block, Block is the least unit of erasing operation, and each Block points are several page of Page, and Page is minimum read/write unit, by certain The memory cell of quantity can be constituted, and several memory cell on a Wordline constitute two Page, each MEMORY Represent that two electronics of data are respectively stored in two page in CELL.Page is by data field (Data Area) and redundant area (Spare Area) is constituted, and the former is used for depositing the data of user, and the latter is used for depositing some Added Management information, including ECC (Error Checking and Correcting) region and the Meta regions of storage FTL management informations.In order to improve speed, Particle can be divided between several areas Plane, Plane can carry out identical read-write erasing operation.Enter to a Page Before row manifolding, it is necessary to first the Block is wiped.And each physics Block erasing times be it is limited, typically can be It is thousands of between tens of thousands of.

Read procedure：In the Block chosen by address, selected Page control pole does not apply voltage, other Page's Control pole applies 5V voltage, is not so that the memory cell in the Page chosen is all turned on, choosing has electric charge in Page Memory cell conducts, data storage " 0 "；Uncharged memory cell cut-off, data storage " 1 ".So as to be read from I/O Choose Page data.

Write process：In the Block chosen by address, selected Page control pole can be applied in 20V voltage, other Page control pole is then applied in 10V voltage, it is necessary to which the String of write-in can be grounded 0V, it is not necessary to which the String of write-in is then 10V voltage is applied in, so needs just to be applied in 20V pressure difference in the memory cell write, starts to inject electricity to floating boom Lotus, completes write operation after a period of time.

MLC Nand Flash this electrical characteristic determines that it asking for bit upsets easily occurs during read-write Topic, prior art there occurs that bit upsets are realized as latter by ECC error correction or BCH error correction, by error correcting code bit is overturn into Row is corrected.

ECC error correcting capability be it is limited, 1KB data typically can only error correction 60bit, it is excessive in the event of the number of mistake It can not then be repaired；Though BCH error correction can correct the bit reversal of several, it is time-consuming longer, even if only 1bit mistakes when also Coding and decoding is carried out to whole information, taken longer.

So if occur bit upset quantity exceed error correcting capability institute energy error correction scope, the data having access to can Can be wrong, it is impossible to precognition, system will be unable to normal operation.ECC just refer to " Error Correcting Code's " Write a Chinese character in simplified form, Chinese is " error checking and correction "." the UnableError Correcting Code " letter that UECC just refers to Write, Chinese is " can not realize error checking and correction ".

All be above from occur bit upset after, the remedial measure of progress.There is the possibility for not being likely to reduced and bit upsets occur Occur without or occur that less and also just solve the problem of bit is overturn.

The content of the invention

For disadvantages described above, present invention aims at proposing how to reduce the probability that bit upsets occur, especially for When MLC Nand Flash write orders are immediately performed read command after performing, there is the reading error in data that large area bit reversal is caused The problem of, it is ensured that the data for the MLC Nand Flash that system is read are correct, and then ensure the stability of system.

In order to solve the problems, such as the problem above present invention propose it is a kind of prevent MLC Nand Flash from UECC method occur, It is characterized in that by system access MLC Nand Flash operational order according to MLC Nand Flash storage organization with Page accesses for unit, and the page of high bit of storage is upper page, and the page of low bit of storage is lower page； First judge whether current page is upper page before writing page operations, if it is setting reading delay designations Need_delay is True, and present system time Timestamp_write is recorded, delay designations are read for flase if not then setting；Reading First judge whether Need_delay is true before page operations, if true, then calculate present system time and record Timestamp_write time difference, judge whether the time difference is more than safe time interval, be delayed behaviour if being not more than Make, then perform read command operation；If Need_delay is flase, read command operation is directly carried out.

Described prevents MLC Nand Flash from the method for UECC problems occur, it is characterised in that each write operation, will write Operation is that unit enters line command fractionation by page, is write backward successively according to page numeric order, writes the page of an even-order number Afterwards, the page of latter odd-order number is and then write.

Described prevents MLC Nand Flash from the method for UECC problems occur, it is characterised in that between described safety time Every, pass through particle swarm optimization algorithm calculate obtain.

Described prevents MLC Nand Flash from the method for UECC problems occur, it is characterised in that particle swarm optimization algorithm meter Calculate and obtain specific safety time, it is assumed that safe time interval is exactly a particle, empirically set between initial safety time Every it is 0 to set optimization aim to occur bit upset numbers, when algorithm optimization reaches maximum times or reaches the optimization threshold of setting Stop iteration during value, resulting particle optimal solution is required safe time interval.

The present invention easily produces the situation of bit upsets, pin by analyzing MLC Nand Flash during read-write operation The operating process of read-write operation order is optimized to the situation, large area is effectively reduced and bit upsets and UECC's occurs Problem, so as to effectively raise the validity for reading data.

Brief description of the drawings

Fig. 1 is NAND FLASH MEMORY CELL structure charts；

Fig. 2 is NAND FLASH BLOCK structural representations；

Fig. 3 is the distribution schematic diagram of share pages in Block；

Fig. 4 is write order handling process；

Fig. 5 is read command handling process.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.

Analysis finds the electrical characteristic of MLC Nand Flash read-write operation, mono- memory cell of MLC Nand Flash Referred to as memory cell, can store 2bits information, and this 2bits belongs to two different page, such one group Page is share pages, and that deposits low-order bit is lower page, and that deposits high order bit is upper page, is performing After upper page write order, if going to read the data in page immediately, the bit upsets of larger proportion are had, so that The information read is caused there are UECC mistakes and can not be corrected by reading recovery read retry.

The distribution that Fig. 3 is share pages in the distribution schematic diagram of share pages in Block, each block is Similar, page arranges by page numeric orders, wherein page00 and page06, page01 and page07, page04 with Page10, page05 and page11, page08 and page14, page09 and page15 separately constitute share pages, page 00th, 01,04,05,08,09 is all lower page, and what these page were stored is the lower bit data in memory cell； Page 06,07,10,11,14,15 is upper page, and that these page are stored is the upper bit in memory cell Data.Namely same group share pages lower page corresponding page sequence numbers come corresponding upper page Rule before corresponding page sequence numbers is arranged, and the page of other sequence numbers is also that the rule is grouped and arranged.

Fig. 4 is write order handling process, and according to the characteristic of MLC Nand Flash particles, lower must be first write every time Bit, then write upper bit, is so not in just bit upsets, that is, needs first to write lower page and write upper page's again It is required that, system carries out actual write order according to following flow and operated：Write order is received, first since a page of even-order number Write, whether judge the page is upper page, if it is set Need_delay to be true, Timestamp_write is Present system time, then writes the page of an odd-order number after even page, if it is determined that the page is lower page, then Setting Need_delay is flase, and Timestamp_write is 0, then writes the page of an odd-order number after even page, Equally it is made whether as Upper page operation, the order of the overall sequence number by page from small to large carries out actual write operation, Be recycled to always all page data all write untill.

Fig. 5 is read command handling process.Arrived when system receives read command, whether judge Need_delay is true, If otherwise directly execution read command；Then set Timestamp_read to be present system time if YES, calculate The time difference for the timestamp_write that Timestamp_read has with record, whether judge the time difference>Between safety time Every if it is performing read command, and Need_delay is set into flase；If<When safe time interval is then delayed corresponding Between, the time is personal distance time and the difference of time difference above calculated, then performs read command, and by Need_delay It is set to flase.

Using the optimized algorithm dynamic access current desired personal distance time, it is to avoid setting fixed interval is brought Not versatility and can not adaptivity shortcoming.Particle swarm optimization algorithm is that a kind of particle degree of adapting it to that obtains is substantially equal to Perfect condition, the process of optimal solution is finally given by iterative manner.The personal distance time is entered using particle swarm optimization algorithm Row optimization, safe time interval is exactly a particle, empirically sets initial safe time interval, set optimization aim as Generation bit upset numbers are 0, and iteration, gained are stopped when algorithm optimization reaches maximum times or reaches the optimization threshold value of setting To particle optimal solution be required safe time interval.The safe time interval come out by optimized algorithm dynamic calculation, Can realize has different safe time intervals under different NAND particle characteristics, so as to reach required safe time interval Adaptivity.

Above disclosed is only an embodiment of the present invention, can not limit the interest field of sheet with this certainly, One of ordinary skill in the art will appreciate that all or part of flow of above-described embodiment is realized, and according to the claims in the present invention institute The equivalent variations of work, still fall within the scope that the present invention is covered.

Claims

1. a kind of prevent MLC Nand Flash from the method for UECC problems occur, it is characterised in that system is accessed into MLC Nand Flash operational order is accessed according to MLC Nand Flash storage organization in units of page, the page of high bit of storage For upper page, the page of low bit of storage is lower page；Write page operation before first judge current page whether be Upper page, it is true if it is to set and read delay designations Need_delay, and records present system time Timestamp_write, flase is designated as if not reading delay is then set；First judge Need_delay before page operations are read Whether it is true, if true, then the time difference of system time and the Timestamp_write of record, judges institute before calculating State whether the time difference is more than safe time interval, the delay operation if being not more than, then perform read command operation；If Need_ Delay is flase, directly carries out read command operation.

2. according to claim 1 prevent MLC Nand Flash from the method for UECC problems occur, it is characterised in that every time Write operation, enters line command for unit by page by write operation and splits, write backward successively according to page numeric order, write an idol After the page of sequence number, the page of latter odd-order number is and then write.

3. according to claim 1 prevent MLC Nand Flash from the method for UECC problems occur, it is characterised in that described Safe time interval, pass through particle swarm optimization algorithm calculate obtain.

4. according to claim 1 prevent MLC Nand Flash from the method for UECC problems occur, it is characterised in that particle Colony optimization algorithm, which is calculated, obtains specific safety time, it is assumed that safe time interval is exactly a particle, empirically sets initial Safe time interval, set optimization aim as occur bit upset number be 0, when algorithm optimization reaches maximum times or reaches Stop iteration during the optimization threshold value of setting, resulting particle optimal solution is required safe time interval.