CN1688110A - Reed solomon decoder based on CAM - Google Patents
Reed solomon decoder based on CAM Download PDFInfo
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- CN1688110A CN1688110A CN 200510026613 CN200510026613A CN1688110A CN 1688110 A CN1688110 A CN 1688110A CN 200510026613 CN200510026613 CN 200510026613 CN 200510026613 A CN200510026613 A CN 200510026613A CN 1688110 A CN1688110 A CN 1688110A
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Abstract
A Read Solomon decoder based on an addressing storage is composed of an adjoint unit, an error position polynomial unit, a Qian unit, a frequency domain error pattern unit, a time domain error pattern unit and an error-correcting unit. The head of the received RS code enters into the adjoint unit to generate an adjoint factor to be read out by the error position polynomial unit and generate its factor to be normalized by a search list, the Qian unit reads out the factor to generator error numbers to judge if the decode is successful. The frequency domain error pattern unit reads at the normalized error position polynomial factor to form a frequency domain error pattern after operation to by read out by the time domain error pattern unit to generate a time domain error pattern to be corrected by the correcting unit together with the received code to generate decoded codes.
Description
Technical field
The present invention relates to a kind of RS (Read-solomon) decoder, can be used for satellite system, wireless communication transmissions system, storage system and high definition television etc., belong to electronic technology field based on addressable memory.
Background technology
The RS sign indicating number is a kind of multibit code that very strong error correcting capability is arranged.(N is to be based upon galois field GF (2 t) to RS
m) on error correcting code, wherein m is the figure place of a symbol, the number of RS coded identification is n=2
m-1, wherein the information code number is k=n-2t, and the check code number is 2t, and minimum intersymbol is apart from d
0=2t+1.The RS sign indicating number is widely used in the engineering reality, as satellite system, wireless communication transmissions system, storage system and high definition television etc.
Existing RS decoder adopts the euclidean decoding algorithm more, on realizing, adopted in circuit the memory of first in first out, it is a kind of pipeline organization circuit, for example H.M.Shao is at document " A VLSI design of apipeline Reed-Solomon decoder " (IEEE Transactions on Computers, 1985, Vol.5 (C-34): the pipeline organization RS decoder that has provided typical employing push-up storage Page:393-402.).The core of RS decoding is an interative computation, the RS decoder of pipeline organization can linearity increase along with the increase of interative computation number of times expending of hardware resource, therefore the pipeline organization RS decoder based on push-up storage has the wasteful and low shortcoming of operation efficiency of hardware resource, is not suitable for the realization of high speed lsi system.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art, design provides a kind of Read-solomon decoder based on addressable memory, reduces the expending of hardware resource improved operation efficiency.
For realizing this purpose, the present invention has provided the RS decoder that adopts addressable memory.Addressable memory has adopted the memory addressing mode, comprises readable and writable memory and read-only memory.The cell data of readable and writable memory can be read and write repeatedly, is a kind of loop structure circuit, thereby not expending of hardware resource can increase with the increase of interative computation number of times.
The RS decoder of the present invention's design is by the syndrome unit, and error location polynomial unit, Qian Shi unit, frequency domain error pattern unit, time domain error pattern unit and error correction unit six parts are formed.The RS code word that receives is connected to the syndrome unit, writes the receiving code word memory, behind interative computation, obtains the syndrome coefficient, writes the syndrome memory; The multinomial unit, output connection error position of syndrome unit, read the syndrome coefficient by the error location polynomial unit, write error position multinomial memory, behind interative computation and read-write operation, form the error location polynomial coefficient, utilize look-up table again,, write normalization error location polynomial memory the normalization of error location polynomial coefficient; The output of error location polynomial unit connects Qian Shi unit and frequency domain error pattern unit respectively, and Qian Shi reads the unit normalization error location polynomial coefficient, and through interative computation, the generation error number judges whether decoding is successful; Normalization error location polynomial coefficient is read in frequency domain error pattern unit, forms the frequency domain error pattern after the computing, writes frequency domain error pattern memory; The output of frequency domain error pattern unit connects time domain error pattern unit, read the frequency domain error pattern by time domain error pattern unit, write the time domain error pattern memory, behind interative computation and read-write operation, the data of time domain error pattern memory are exactly the time domain error pattern; The output of time domain error pattern unit connects error correction unit, and read the time domain error pattern and receive code word by error correction unit, through error correction, the final code word that generates after deciphering.
Each unit in the RS decoder of the present invention is formed by three basic module circuit: memory, controller and arithmetic unit.Memory has mainly adopted readable and writable memory, is used to store various code words, pattern or multinomial coefficient, and this external memory has also adopted read-only memory, each element of storage Galois field; Arithmetic unit is made up of adder and multiplier, finishes the addition and the multiplying of Galois field respectively; Controller sends control signal.The groundwork principle of RS decoder of the present invention is: controller sends control signal, the readout memory data, and the input arithmetic unit is finished computing, the dateout write memory of arithmetic unit.
The structure and the course of work of each component units are as follows in the RS decoder of the present invention:
1) the syndrome unit comprises controller, and a storage receives the readable and writable memory of the readable and writable memory of code word, a storage syndrome, the read-only memory of a storage Galois field element, and an adder and a multiplier.The RS prefix of code word that receives is introduced into the syndrome unit, writes the receiving code word memory, receives code word and Galois field element through 2t interative computation, and the gained data are exactly the syndrome coefficient, write the syndrome memory.
2) the error location polynomial unit comprises controller, one with the readable and writable memory of the readable and writable memory of the storage syndrome of syndrome units shared, four polynomial readable and writable memories in storage errors position, a storage normalization error location polynomial, the read-only memory of a storage Galois field element, and two multipliers and an adder.The syndrome coefficient is read in the error location polynomial unit, write error position multinomial memory, behind t interative computation of data process and read-write operation of memory, just formed the error location polynomial coefficient, utilize look-up table again, to the normalization of error location polynomial coefficient, write normalization error location polynomial memory.
3) the Qian Shi unit comprises controller, read-only memory with the readable and writable memory of the storage normalization error location polynomial of error location polynomial units shared, a storage Galois field element, and a counter, a multiplier and an adder.Qian Shi reads the unit normalization error location polynomial coefficient, through n interative computation, generation error number, judges whether decoding is successful.
4) frequency domain error pattern unit comprises controller, one with the readable and writable memory of the storage syndrome of syndrome units shared, one and the readable and writable memory of the storage normalization error location polynomial of error location polynomial units shared, readable and writable memory and t multiplier and t adder of a storage frequency domain error pattern.Normalization error location polynomial coefficient is read in frequency domain error pattern unit, through n computing, forms the frequency domain error pattern, writes frequency domain error pattern memory.
5) time domain error pattern unit comprises controller, one with the readable and writable memory of the readable and writable memory of the storage frequency domain error pattern of frequency domain error pattern units shared, a storage time domain error pattern, the read-only memory of a storage Galois field element, and a multiplier and an adder.The frequency domain error pattern is read in time domain error pattern unit, writes the time domain error pattern memory, and behind 2t interative computation of data process and read-write operation of memory, the data of time domain error pattern memory are exactly the time domain error pattern.
6) error correction unit comprises controller, and one receives the readable and writable memory, of code word and the readable and writable memory and the adder composition of the storage time domain error pattern of time domain error pattern units shared with the storage of syndrome units shared.Error correction unit is read the time domain error pattern and is received code word, through error correction, and the code word after the final generation decoding, decoding finishes.
RS decoder of the present invention has adopted addressable memory, can save a large amount of computing circuits and memory circuit, greatly reduces expending of hardware resource, is fit to the realization of large scale integrated circuit; And this decoder adopts the memory addressing mode, has avoided the redundant operation of pipeline organization, can improve the efficient of computing, is fit to high speed circuit and realizes.Therefore, the RS decoder that the present invention provides has hardware resource and expends for a short time, and the advantage that the little and suitable high speed lsi of operand is realized is a kind of decoder of RS efficiently.
Description of drawings
Fig. 1 RS decoder architecture of the present invention figure.
The calculator circuit figure of Fig. 2 RS decoder of the present invention.
The syndrome cellular construction figure of Fig. 3 RS decoder of the present invention.
The error location polynomial cellular construction figure of Fig. 4 RS decoder of the present invention.
The Qian Shi cellular construction figure of Fig. 5 RS decoder of the present invention.
The frequency domain error pattern cellular construction figure of Fig. 6 RS decoder of the present invention.
The time domain error pattern cellular construction figure of Fig. 7 RS decoder of the present invention.
The error correction unit structure chart of Fig. 8 RS decoder of the present invention.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is further described.
The present invention has provided the RS decoder that adopts addressable memory.Addressable memory has adopted the memory addressing mode, rather than the memory displacement mode.Addressable memory comprises readable and writable memory and read-only memory, and the data in the readable and writable memory can be read and write repeatedly, is a kind of loop structure circuit.
With reference to Fig. 1, decoder of the present invention is made up of six unit: syndrome unit, error location polynomial unit, Qian Shi unit, frequency domain error pattern unit, time domain error pattern unit and error correction unit.The RS code word that receives is connected to the syndrome unit, writes the receiving code word memory, behind 2t interative computation, obtains the syndrome coefficient, writes the syndrome memory.The multinomial unit, output connection error position of syndrome unit, read the syndrome coefficient by the error location polynomial unit, write error position multinomial memory, behind t interative computation of data process and read-write operation of memory, just formed the error location polynomial coefficient, utilize look-up table again,, write normalization error location polynomial memory the normalization of error location polynomial coefficient.The output of error location polynomial unit connects Qian Shi unit and frequency domain error pattern unit respectively, and Qian Shi reads the unit normalization error location polynomial coefficient, through n interative computation, generation error number, judges whether decoding is successful; Normalization error location polynomial coefficient is read in frequency domain error pattern unit, through n computing, forms the frequency domain error pattern, writes frequency domain error pattern memory.The output of frequency domain error pattern unit connects time domain error pattern unit, read the frequency domain error pattern by time domain error pattern unit, write the time domain error pattern memory, behind n interative computation of data process and read-write operation of memory, the data of time domain error pattern memory are exactly the time domain error pattern.The output of time domain error pattern unit connects error correction unit, and read the time domain error pattern and receive code word by error correction unit, through error correction, the final code word that generates after deciphering, decoding finishes.
Each unit in the RS decoder of the present invention is formed by three basic module circuit: controller, memory and arithmetic unit.Controller sends control signal; Memory is used to store data; Arithmetic unit is finished the addition and the multiplying of Galois field.Wherein memory adopts addressable mode, is divided into two kinds of readable and writable memory and read-only memorys.Readable and writable memory is used to store various code words, pattern or multinomial coefficient, and address bus, BDB Bi-directional Data Bus, read signal and four ports of write signal are arranged; Each element of read-only memory storage Galois field has address bus, data/address bus, three ports of read signal.
With reference to Fig. 2, arithmetic unit mainly comprises arithmetic unit 1 and arithmetic unit 2.Arithmetic unit 1 is by an adder , and multiplier and register D form; Arithmetic unit 2 is by an adder , and two multiplier and register a, b form.
With reference to Fig. 3, the syndrome unit is made up of three modular circuits: controller; Memory: comprise that (capacity is that (capacity is 2t * m) and (capacity is n * m) to read-only memory _ α for n * m), readable and writable memory _ s to readable and writable memory _ r; Arithmetic unit: arithmetic unit 1.The syndrome unit is used to produce the syndrome multinomial coefficient, and its execution in step is as follows: 1) receive code word under the effect of controller, write readable and writable memory _ r successively, the address bus of read-only memory _ α (n element of storage Galois field) is made as 0; 2) controller reads the data under read-only memory _ α current address, send into the input 1 of arithmetic unit 1, controller is under timeticks, read all data of readable and writable memory _ r successively, and send into the input 2 of arithmetic unit 1 successively, through n clock, deposit the output port data of arithmetic unit 1 in readable and writable memory _ s; 3) read-only memory _ α address bus adds 1, repeats 2), be 2t until read-only memory _ α address bus, iteration finishes, and readable and writable memory _ s institute deposit data is exactly the syndrome multinomial coefficient.
With reference to Fig. 4, the error location polynomial unit is made up of three modular circuits: controller; Memory: comprise that (capacity is that (capacity is that (capacity is that (capacity is that (capacity is t * m) and read-only memory _ α for t * m), readable and writable memory _ σ for t * m), readable and writable memory _ U for 2t * m), readable and writable memory _ L for 2t * m), readable and writable memory _ Q for readable and writable memory _ s, readable and writable memory _ R; Arithmetic unit: arithmetic unit 2.The error location polynomial unit is used to produce the error location polynomial coefficient, and its execution in step is as follows:
1) readable and writable memory _ R is read and write to the data of readable and writable memory _ s, the cell data of location superlatively of readable and writable memory _ Q writes 1, remaining element writes 0, all unit of readable and writable memory _ L deposit 0 in, the lowest address unit of readable and writable memory _ U deposits 1 in, remaining element deposits 0 in, the highest non-zero unit data of register a storage readable and writable memory _ R, the highest non-zero unit data of register b storage readable and writable memory _ Q;
2) controller is read the data of readable and writable memory _ R and readable and writable memory _ Q successively, sense data must satisfy location cell data non-zero superlatively, the data of readable and writable memory _ R and readable and writable memory _ Q are sent into the input 1 and the input 2 of arithmetic unit 2 respectively and carried out computing, if the address of high non-zero unit of readable and writable memory _ R is not less than the address of high non-zero unit of readable and writable memory _ Q, operation result writes readable and writable memory _ R successively, otherwise, write readable and writable memory _ Q;
3) controller reads the data of readable and writable memory _ L, readable and writable memory _ U successively, and computing is carried out in input 1 and the input 2 of sending into arithmetic unit 2 respectively, if the address of high non-zero unit of readable and writable memory _ R is not less than the address of high non-zero unit of readable and writable memory _ Q, operation result writes readable and writable memory _ L successively, otherwise, write readable and writable memory _ U;
4) repeat 2) and 3), (address of the highest non-zero unit of or readable and writable memory _ Q) is less than t, and (or readable and writable memory _ data U) are the coefficient of error location polynomial to readable and writable memory _ L until readable and writable memory _ R;
5) to error location polynomial normalization, promptly finish division arithmetic, the present invention has adopted look-up table.(each cell data of or readable and writable memory _ U) is read to readable and writable memory _ L, look into their corresponding address in read-only memory _ α, each cell data is subtracted each other the new address of formation in read-only memory _ α corresponding address and the highest unit in read-only memory _ α corresponding address, the new address of gained is exactly a normalization error location polynomial coefficient in the data of read-only memory _ α, at last the error location polynomial coefficient is write readable and writable memory _ σ successively.
With reference to Fig. 5, the Qian Shi unit is made up of three modular circuits: controller; Memory: comprise readable and writable memory _ σ and read-only memory _ α; Arithmetic unit: arithmetic unit 1 sum counter.The Qian Shi unit is used for judging whether decoding can be successful, and its execution in step is as follows: 1) address bus of read-only memory _ α is made as 0, and counter is made as 0; 2) read element under read-only memory _ α current address, send into 1 mouthful of the input of arithmetic unit 1, under timeticks, read each cell data of readable and writable memory _ σ successively, and send into the input 2 of arithmetic unit 1, through t clock, the output port data of arithmetic unit 1 is preserved, and whether judged result be-1, if counter adds up; 3) read-only memory _ α address bus adds 1, repeats 2), be n-1 until read-only memory _ α address bus, iteration finishes.Whether judge the counter result greater than t, if decoding failure is changed to 0 with whether successfully decoded the sign, if not, successfully decoded, whether successfully decoded the sign is changed to 1.
With reference to Fig. 6, frequency domain error pattern unit is made up of three modular circuits: controller; Memory: comprise that (capacity is n * m) for readable and writable memory _ s, readable and writable memory _ σ and readable and writable memory _ E; Arithmetic unit: arithmetic unit 3.Frequency domain error pattern circuit is at first read the data of readable and writable memory _ s and readable and writable memory _ σ, enter circuit according to timeticks, export successively through 2t beat, as preceding 2t frequency domain error pattern, pass through n-2t beat again, finish and the computing of error location polynomial coefficient and output successively, formed whole frequency domain error pattern, frequency domain error pattern data write readable and writable memory _ E successively the most at last.
With reference to Fig. 7, time domain error pattern unit is made up of three modular circuits: controller; Memory: comprise that (capacity is n * m) and read-only memory _ α for readable and writable memory _ E, readable and writable memory _ e; Arithmetic unit: arithmetic unit 1.Time domain error pattern unit is used to produce the time domain error pattern, and its execution in step is as follows: 1) address of read-only memory _ α is made as 0; 2) read data under read-only memory _ α current address, send into the input 1 of arithmetic unit 1, under timeticks, get each address cell data of readable and writable memory _ E successively, and send into the input 2 of arithmetic unit 1, through n timeticks, the output port data of arithmetic unit 1 is write readable and writable memory e; 3) read-only memory _ α address bus adds 1, repeats 2), be n-1 until read-only memory _ α address bus, iteration finishes, and the data of readable and writable memory _ e are exactly the time domain error pattern.
With reference to Fig. 8, error correction unit is made up of three modular circuits: controller; Memory: comprise readable and writable memory _ e and readable and writable memory _ r; Arithmetic unit: adder.The error correction unit error correction procedure is: each cell data of reading readable and writable memory _ e and readable and writable memory _ r according to timeticks successively, and enter two input ports of adder respectively, through n timeticks, the data of adder output are decoding back code word, and decoding finishes.
Claims (6)
1, a kind of Read-solomon decoder based on addressable memory, it is characterized in that adopting the memory addressing mode, by the syndrome unit, error location polynomial unit, Qian Shi unit, frequency domain error pattern unit, time domain error pattern unit and error correction unit are formed, the RS code word that receives is connected to the syndrome unit, writes the receiving code word memory, behind interative computation, obtain the syndrome coefficient, write the syndrome memory; The multinomial unit, output connection error position of syndrome unit, read the syndrome coefficient by the error location polynomial unit, write error position multinomial memory, behind interative computation and read-write operation, form the error location polynomial coefficient, utilize look-up table again,, write normalization error location polynomial memory the normalization of error location polynomial coefficient; The output of error location polynomial unit connects Qian Shi unit and frequency domain error pattern unit respectively, and Qian Shi reads the unit normalization error location polynomial coefficient, and through interative computation, the generation error number judges whether decoding is successful; Normalization error location polynomial coefficient is read in frequency domain error pattern unit, forms the frequency domain error pattern after the computing, writes frequency domain error pattern memory; The output of frequency domain error pattern unit connects time domain error pattern unit, read the frequency domain error pattern by time domain error pattern unit, write the time domain error pattern memory, behind interative computation and read-write operation, the data of time domain error pattern memory are exactly the time domain error pattern; The output of time domain error pattern unit connects error correction unit, and read the time domain error pattern and receive code word by error correction unit, through error correction, the final code word that generates after deciphering.
2, according to the Read-solomon decoder based on addressable memory of claim 1, it is characterized in that described syndrome unit comprises controller, a storage receives the readable and writable memory of the readable and writable memory of code word, a storage syndrome, the read-only memory of a storage Galois field element, and an adder and a multiplier.
3, according to the Read-solomon decoder based on addressable memory of claim 1, it is characterized in that described error location polynomial unit comprises controller, one with the readable and writable memory of the readable and writable memory of the storage syndrome of syndrome units shared, four polynomial readable and writable memories in storage errors position, a storage normalization error location polynomial, the read-only memory of a storage Galois field element, and two multipliers and an adder.
4, according to the Read-solomon decoder based on addressable memory of claim 1, it is characterized in that described Qian Shi unit comprises controller, read-only memory with the readable and writable memory of the storage normalization error location polynomial of error location polynomial units shared, a storage Galois field element, and a counter, a multiplier and an adder.
5, according to the Read-solomon decoder based on addressable memory of claim 1, it is characterized in that described frequency domain error pattern unit comprises controller, one with the readable and writable memory of the storage syndrome of syndrome units shared, one and the readable and writable memory of the storage normalization error location polynomial of error location polynomial units shared, readable and writable memory and a plurality of multiplier and the adder of a storage frequency domain error pattern.
6, according to the Read-solomon decoder based on addressable memory of claim 1, it is characterized in that described time domain error pattern unit comprises controller, one with the readable and writable memory of the readable and writable memory of the storage frequency domain error pattern of frequency domain error pattern units shared, a storage time domain error pattern, the read-only memory of a storage Galois field element, and a multiplier and an adder.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101873143A (en) * | 2010-06-01 | 2010-10-27 | 福建新大陆电脑股份有限公司 | Syndrome computing circuit in RS (Reed-Solomon) error correcting code decoder and computing method thereof |
| CN102163463A (en) * | 2011-04-26 | 2011-08-24 | 西安交通大学 | Double coin search method for reducing BCH (broadcast channel) decoding delay |
| CN101409601B (en) * | 2007-10-10 | 2012-05-30 | 索尼株式会社 | Reception device, reception method, information processing device, information processing method, and program |
-
2005
- 2005-06-09 CN CN 200510026613 patent/CN1688110A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409601B (en) * | 2007-10-10 | 2012-05-30 | 索尼株式会社 | Reception device, reception method, information processing device, information processing method, and program |
| CN101873143A (en) * | 2010-06-01 | 2010-10-27 | 福建新大陆电脑股份有限公司 | Syndrome computing circuit in RS (Reed-Solomon) error correcting code decoder and computing method thereof |
| CN101873143B (en) * | 2010-06-01 | 2013-03-27 | 福建新大陆电脑股份有限公司 | Syndrome computing circuit in RS (Reed-Solomon) error correcting code decoder and computing method thereof |
| CN102163463A (en) * | 2011-04-26 | 2011-08-24 | 西安交通大学 | Double coin search method for reducing BCH (broadcast channel) decoding delay |
| CN102163463B (en) * | 2011-04-26 | 2013-01-02 | 西安交通大学 | Double coin search method for reducing BCH (broadcast channel) decoding delay |
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