CN102142417A - 在基板上搭载半导体结构体的半导体装置及其制造方法 - Google Patents

在基板上搭载半导体结构体的半导体装置及其制造方法 Download PDF

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CN102142417A
CN102142417A CN2010106108929A CN201010610892A CN102142417A CN 102142417 A CN102142417 A CN 102142417A CN 2010106108929 A CN2010106108929 A CN 2010106108929A CN 201010610892 A CN201010610892 A CN 201010610892A CN 102142417 A CN102142417 A CN 102142417A
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substrate
semiconductor
sealant
semiconductor device
external connection
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肋坂伸治
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Abstract

一种半导体装置，包含：半导体结构体，该半导体结构体具有半导体衬底和凸设在半导体衬底表面的外部连接用电极；搭载半导体结构体的基板；和密封层，该密封层层叠在除了外部连接用电极以外的半导体衬底上、和包含半导体衬底侧面的基板上。

Description

在基板上搭载半导体结构体的半导体装置及其制造方法
技术领域
本发明涉及一种在基板(ベ一ス板)上搭载半导体结构体的半导体装置及其制造方法。
背景技术
在日本特开2008-60298号公报中，作为IC芯片的封装方法，有所谓的WLP(Wafer Level Package)法和EWLP(Embedded Wafer Level Package)法。WLP法是对晶片状态的半导体晶片进行树脂密封和端子形成之后，按芯片尺寸进行切分的方法(例如参考专利文献1的图2～图10)。由此，可以制造与内置的IC芯片具有相同尺寸的小型封装。
EWLP法是进一步地封装由WLP法制造的芯片，使该芯片成为嵌入衬底(日本语：基板)的状态的方法(例如参考专利文献1的图11～图16)。具体而言，将通过WLP法而实现了封装化的多个半导体芯片2排列在基板1上，在半导体芯片2的周围将格子状的半硬化树脂片14a重叠在基板1上，进一步地在该半硬化树脂片14a和半导体芯片2上重叠半硬化树脂片15a，并且通过加热、加压使这些半硬化树脂片14a、15a硬化。之后，由激光在半硬化树脂片15a硬化而成的绝缘层15上形成通孔16，通过半加成法(セミアディティブ)形成配线17、18，将配线17、18连接到半导体芯片2的电极12。之后，在配线17、18上形成焊料21，按每个半导体芯片2来切割(ダィシング)基板1、密封层14和绝缘层15。
然而，在专利文献1中记载的制造方法中，为了将配线17、18连接到电极12，需要由激光来形成通孔16的工序。因此，需要激光加工的设备。此外，增加了制造工时，并且制造成本也增加了。
因此，本发明要解决的课题是能够省略由激光加工形成通孔的工序，并且能够减少半导体装置的制造工序、制造时间和制造成本。
发明内容
为了解决以上课题，根据本发明的一个实施方式，提供一种半导体装置，具有：半导体结构体，该半导体结构体具有半导体衬底和凸设在所述半导体衬底表面上的外部连接用电极；搭载所述半导体结构体的基板；和密封层，该密封层层叠在除了所述外部连接用电极以外的所述半导体衬底上和包含所述半导体衬底侧面的所述基板上。
根据本发明的其他实施方式，提供一种半导体装置，其中，将具有凸设在半导体衬底表面上的外部连接用电极的多个半导体结构体装载在基板上，在除了所述外部连接用电极以外的所述半导体衬底上和包含所述半导体衬底侧面的所述基板上层叠密封层。
附图说明
图1是本发明的实施方式中的半导体装置的剖视图。
图2是在图1中示出的半导体装置的制造方法的工序图。
图3是接着图2的工序的工序图。
图4是接着图3的工序的工序图。
图5是接着图4的工序的工序图。
图6是接着图5的工序的工序图。
图7是接着图6的工序的工序图。
具体实施方式
下面，采用附图说明用于实施本发明的实施方式。然而，在下面描述的实施方式中，虽然为了实施本发明而在技术上给出了优选的各种限制，但是本发明的范围不限定在下面的实施方式和图示例中。
图1是半导体装置1的剖视图。
该半导体装置1具有基板31、半导体结构体10、密封层32、上层配线33和焊料球35等。半导体结构体10具有半导体芯片11、钝化膜13、多个连接垫12、保护膜25、再配线21和柱状电极(外部连接用电极)22等。并且，在半导体芯片11的表面上凸设圆柱形状、棱柱形状及其他柱形状的柱状电极22，通过粘着剂层30将该半导体芯片11粘着在基板31上，在基 板31上层叠密封层32以覆盖半导体芯片11，并且柱状电极22贯通密封层32。
半导体芯片11是单片化的半导体衬底。半导体芯片11由硅等构成，在半导体芯片11的表面上形成LSI。多个连接垫12形成在半导体芯片11的表面上，将连接垫12连接到LSI的配线上。钝化膜13覆盖LSI。例如，钝化膜13由氧化硅或氮化硅构成。此外，在钝化膜13上设置露出连接垫12的开口部13a。
在钝化膜13上层叠保护膜25。保护膜25由聚酰亚胺系树脂和其他树脂构成。例如，关于保护膜25，可以采用聚酰亚胺(PI)、聚苯并恶唑(PBO)等高性能塑料材料，环氧系、苯酚系、硅系等塑料材料，或它们的复合材料等。
在保护膜25上设置露出连接垫12的开口部25a。保护膜25的开口部25a比钝化膜13的开口部13a小，在开口部25a的外周部，连接垫12和保护膜25紧密连接。
在包含连接垫12上表面的保护膜25上形成基底金属层(未图示)。基底金属层是在铜(Cu)膜或钛(Ti)上层叠铜而构成的膜。在俯视图中，基底金属层被图案化为规定的形状。将基底金属层的一部分层叠在连接垫12上，基底金属层经由开口部13a、25a连接到连接垫12上。在基底金属层上形成再配线21。再配线21是铜(Cu)膜。在俯视图中，再配线21被图案化为规定的形状，并且再配线21与基底金属层的图案形状基本上相同。并且，也可以不形成保护膜25，而在钝化膜13上形成再配线21。
在再配线21的一部分上形成柱状电极22。柱状电极22由铜和其他金属构成。各再配线21电连接分别相对应的连接垫12和柱状电极22。
半导体芯片11通过粘着剂层30粘着到基板31上。半导体芯片11的粘着面是与形成钝化膜13、连接垫12和柱状电极22的面相反的面。
基板31由玻璃纤维强化环氧树脂(包含玻璃布环氧树脂)、碳纤维强化环氧树脂(包含碳布环氧树脂)、玻璃纤维强化聚酰亚胺树脂(包含玻璃布聚酰亚胺树脂)、碳纤维强化聚酰亚胺树脂(包含碳布聚酰亚胺树脂)和其他纤维强化树脂构成。
密封层32层叠在除了柱状电极22以外的半导体芯片11的表面上和包 含半导体芯片11侧面的基板31上。这里，在半导体芯片11的周围，密封层32层叠在基板31上。由该密封层32覆盖半导体芯片11，密封层32的一部分层叠在半导体芯片11上。再配线21的除了形成柱状电极22的区域以外的区域被密封层32覆盖。柱状电极22贯通密封层32，密封层32的表面与柱状电极22的表面(顶面)同一平面地设置，柱状电极22的表面不被密封层32覆盖。
该密封层32是使半硬化状态(B-stage状态)的片状树脂(半固化片(prepreg))硬化而得到的。此外，密封层32由纤维强化树脂或未纤维强化的树脂构成。具体地，密封层32由玻璃纤维强化环氧树脂(包含玻璃布环氧树脂)、玻璃纤维强化聚酰亚胺树脂(包含玻璃布聚酰亚胺树脂)和其他纤维强化树脂构成。或者，密封层32由未纤维强化的衬底用材料的环氧树脂、衬底用材料的聚酰亚胺树脂和其他衬底用材料的树脂构成。例如，包括松下电工株式会社制造的低介电常数、高耐热的多层印刷配线板用材料MEGTRON6、半导体封装衬底用材料MEGTRON3等。此外，也可以采用日立化成工业株式会社制造的FR-4多层材料“MCL”、高耐热、高可靠性的FR-4多层材料“MCL”、无卤素(halogen-free)FR-4多层材料“MCL”、高Tg环氧多层材料“MCL”、高弹性、低热膨胀的多层材料“MCL”、无卤素高弹性、低热膨胀的多层材料“MCL”、面向薄型封装的无卤素高弹性、低热膨胀的多层材料“MCL”、低介质损耗因数高耐热多层材料“MCL”、无卤素低介电常数低介质损耗因数高耐热多层材料“MCL”、无卤素低介电常数高耐热多层材料“MCL”等。密封层32具有遮光性。
在密封层32上形成上层配线33。上层配线33是铜(Cu)膜、钛(Ti)膜、在钛上层叠铜而成的膜和其他导电膜。在俯视图中，上层配线33被图案化为规定的形状。上层配线33的一部分层叠在柱状电极22的表面(顶面)，上层配线33连接到柱状电极22。
在密封层32上层叠涂层(ォ一バ一コ一ト 
Figure BSA00000401990700041
)34，上层配线33由涂层34覆盖。涂层34由树脂材料构成。此外，涂层34是阻焊剂。即，在涂层34上形成开口部34a，在该开口部34a内露出上层配线33的一部分，并且在其上形成焊料球35。通过将焊料球35结合到上层配线33，焊料球35与上层配线33相互电连接。此外，也可以不设置焊料球35。
在搭载半导体芯片11的面的相反面上，层叠导电膜36，在导电膜36上层叠涂层37。导电膜36与上层配线33为同样的组成。涂层37与涂层34为同样的组成。
并且，在图1中，将一个半导体芯片11搭载在基板31上，并且将该半导体芯片11嵌入密封层32。与此相对地，也可以将多个半导体芯片11搭载在基板31上，并且将这些半导体芯片11嵌入密封层32。
参考图2～图7，说明半导体装置1的制造方法。图2～图7是示出半导体装置1的制造工序的图。在半导体装置1的制造方法中，如图2～图3所示的前工序和如图4～图7所示的后工序有很大的区别。前工序是制造半导体结构体10的工序，后工序是封装制造出的半导体结构体10的工序。
首先，说明作为前工序的半导体结构体10的制造工序。
图2a是切割之前的半导体晶片110的剖视图。如图2a所示，半导体晶片110是非单片化的半导体基板。也就是说，半导体晶片110被作为预定分割线的格子状的切割线路(ダィシングストリ一ト)112划分为多个芯片区域111。这些芯片区域111排列为矩阵状。
在半导体晶片110的表面，按每个芯片区域111而形成LSI。此外，在半导体晶片110的表面形成多个连接垫12。在半导体晶片110的表面成膜钝化膜13，LSI被钝化膜13覆盖。
首先，如图2b所示，在半导体晶片110的表面成膜绝缘性树脂膜，通过将该绝缘性树脂膜图案化，从而在该绝缘性树脂膜上形成开口部25a和槽25b，将该绝缘性树脂膜分割为每个芯片区域111的保护膜25。这里，槽25b沿着切割线路112形成格子状。
形成基底金属层和再配线21。基底金属层和再配线21的形成方法采用半加成法。
具体而言，首先，在包含经由钝化膜13和保护膜25的开口部13a、25a而露出的连接垫12上表面的保护膜25的上表面整体上形成基底金属层。在这种情况下，基底金属层可以仅是通过无电解电镀(無電解メツキ)而形成的铜层，或者可以仅是通过溅射而形成的铜层，也可以是在由溅射所形成的钛等的薄膜层上、通过溅射来形成铜层从而得到的层。
接下来，在基底金属层的上表面，图案形成抗镀膜。在这种情况下， 在与再配线21形成区域相对应的部分上的抗镀膜上形成开口部。
接下来，如图2c所示，在基底金属层上形成再配线21。具体地，通过将基底金属层作为电镀电流路径来进行铜的电解电镀(電解メツキ)，从而在抗镀膜开口部内的基底金属层上表面形成再配线21。
接下来，剥离抗镀膜。在此时刻，基底金属层还未被图案化。
在形成再配线21之后，如图2d所示，通过将比再配线21厚的干膜抗蚀剂122贴附在再配线21和保护膜25之上的一个面上，并且使该干膜抗蚀剂122曝光、显影，从而在干膜抗蚀剂122上形成开口部122a。在开口部122a内，露出再配线21的一部分。形成开口部122a的位置是之后形成柱状电极22的位置，在不形成之后形成的柱状电极22的位置上残留干膜抗蚀剂122。
接下来，将干膜抗蚀剂122作为掩膜，在由干膜抗蚀剂122覆盖了再配线21的一部分的状态下，将再配线21作为电极而进行电解电镀法。由此，如图3a所示，在开口部122a内，在再配线21之上生长柱状电极22。在此，使柱状电极22生长地比再配线21更厚。
接下来，如图3b所示，在形成柱状电极22之后，去除干膜抗蚀剂122。
在此，在如上所述地贴附干膜抗蚀剂122之前，或者在如上所述地去除干膜抗蚀剂122之后，通过蚀刻来去除再配线21的基底金属层中的、不与被图案化的再配线21重叠的部分。此时，虽然再配线21的上层和柱状电极22的表面被部分地蚀刻，但是由于再配线21和柱状电极22与基底金属层相比足够厚，所以残留下再配线21和柱状电极22。
接下来，如图3c所示，沿着切割线路112切割半导体晶片110，使半导体晶片110单片化为多个半导体芯片11。由此，完成在半导体芯片11表面竖立设置多个柱状电极22而成的半导体结构体10。
接着，说明制造出的半导体结构体10的封装工序。
如图4a所示，预备母基板131，在该母基板131的一个面的搭载半导体芯片11的区域，通过涂布或贴附而形成粘着剂层30。并且，在母基板131上矩阵状地排列多个半导体芯片11，并且由粘着剂层30将半导体芯片11粘着到母基板131上。由此，将多个半导体芯片11矩阵状地搭载到母基板131上。在将半导体芯片11粘着到母基板131上时，将与形成柱状电极 22的面相反的面粘着到母基板131上。在此，母基板131是切断图1所示的基板31之前的状态下的基板。
接下来，如图4b所示，将由一层构成的片状半固化片132从这些半导体芯片11和柱状电极22之上层叠到母基板131，并且对该半固化片132进行加压、加热。这里，通过向母基板131对半固化片132进行加压，从而将半固化片132的一部分层叠到半导体芯片11上并且将半导体芯片11嵌入半固化片132，进一步地，使柱状电极22贯通半固化片132。通过加热半固化片132，使半固化片132硬化，从而形成密封层32。
在形成由纤维强化树脂构成的密封层32的情况下，半固化片132是纤维强化半固化片。另一方面，在形成由未纤维强化的树脂构成的密封层32的情况下，半固化片132是未纤维强化的半固化片。所谓的纤维强化半固化片，是将热硬化性树脂(环氧树脂、聚酰亚胺树脂等)浸含在纤维(玻璃纤维、玻璃布、碳纤维、碳布等)中而使该树脂半硬化而得的片状半固化片。所谓的未纤维强化半固化片，是采用不将热硬化性树脂(环氧树脂、聚酰亚胺树脂等)浸含在纤维中而使该树脂半硬化为片状而得的半固化片。作为纤维强化半固化片，特别优选地，采用半硬化状态的玻璃纤维强化环氧树脂或玻璃纤维强化聚酰亚胺树脂。作为未纤维强化的半固化片，特别优选地，采用未纤维强化的半硬化状态的环氧树脂或聚酰亚胺树脂。
接下来，如图5a所示，研磨密封层32的表面和柱状电极22的顶面。通过研磨，使密封层32的表面和柱状电极22的顶面平坦化。此外，在研磨前没有从密封层32的表面露出的柱状电极22，通过研磨而露出其顶面。
接下来，如图5b所示，通过无电解电镀法、电解电镀法或汽相生长法(例如溅射法)或它们的组合，在密封层32的表面和柱状电极22的顶面上生长导电膜133。同时，在相反侧的面上也生长导电膜36。
接下来，在导电膜133上施加抗蚀剂(可以是干膜抗蚀剂，也可以是液态的抗蚀剂)，将该抗蚀剂曝光、显影，并且以残留的抗蚀剂作为掩膜来蚀刻导电膜133。由此，如图6a所示，将导电膜133形状加工成为上层配线33。在上层配线33的图案化之后，去除抗蚀剂。
接下来，如图6b所示，将涂层34图案化，从而涂层34覆盖上层配线33和密封层32，并且使上层配线33的一部分从涂层34的开口部34a露出。 在成膜涂层34时，在相反面上也成膜涂层37。
此外，在图6a示出的工序之后、图6b示出的工序之前，通过交替进行绝缘层的形成和再配线的形成，可以将配线多层化。此外，在图6a示出的工序之后、图6b示出的工序之前，可以从密封层32的表面直到母基板131的相反面地形成透孔。
接下来，如图7a所示，在各开口部34a内，在上层配线33上形成焊料球35。此外，可以省略焊料球35的形成，也可以在下面描述的切割处理之后进行焊料球35的形成。
接下来，按每个半导体芯片11地格子状地切割母基板131和密封层32，当分割成多个半导体装置1时，如图7b所示，母基板131通过切割而被分割为每个半导体装置1的基板31，密封层32也被分割。通过以上工序，完成半导体装置1。
另外，在一个半导体装置1中包含多个半导体芯片11的情况下，不按每个半导体芯片11切割母基板131和密封层32，而是按每个由多个半导体芯片11构成的组来切割母基板131和密封层32。
如上所述，根据本实施方式，由于在形成密封层32时利用了半固化片132(参考图4b)，所以可以使预先形成在半导体芯片11上的柱状电极22贯通半固化片132。也就是说，由于在层叠半固化片132并将其加热、加压之后，通过研磨形成密封层32，所以形成密封层32的工序兼作为形成覆盖半导体芯片11上表面的绝缘膜(密封层)的工序，和形成覆盖包含半导体芯片11的半导体结构体10的周侧面的绝缘膜(密封层)的步骤。因此，在半导体装置1的制造方法中，可以实现绝缘膜(密封层)的形成工序的减少。
此外，在现有的如专利文献1所示的EWLP法中，半导体结构体2的密封膜13的上表面和绝缘层14的上表面在制造过程中可以平坦地形成，但是由于硬化收缩或热膨胀等会形成阶差，配线可能被切断而受到破坏，所以在半导体结构体2和绝缘层14的上表面形成上层绝缘膜15之后，并且通过激光形成通孔16之后，在上层绝缘膜15上形成上层配线18。
根据本实施方式，由于可以在密封层32上直接形成上层配线33，所以不需要进行在形成密封层32之后、由激光在密封层32上形成通孔并在该 激光通孔内形成电极这样的工序。因此，可以减少用于制造半导体装置1所需要的工序、时间、成本。进一步地，由于不需要形成上层绝缘膜，所以可以使半导体装置1的厚度变薄。
此外，由于半固化片132是半硬化状态的，所以即使柱状电极22高，也可以在柱状电极22的周围形成具有厚度的密封层32。

Claims (15)

1.一种半导体装置，其特征在于，包含：
半导体结构体，该半导体结构体具有半导体衬底和凸设在所述半导体衬底表面的外部连接用电极；
搭载所述半导体结构体的基板；以及
密封层，该密封层层叠在除了所述外部连接用电极以外的所述半导体衬底上、和包含所述半导体衬底侧面的所述基板上。
2.根据权利要求1所述的半导体装置，其特征在于，
所述密封层是使所述外部连接用电极贯通半固化片并硬化该半固化片而成的层。
3.根据权利要求2所述的半导体装置，其特征在于，
所述密封层是一层的，是玻璃纤维强化环氧树脂、玻璃纤维强化聚酰亚胺树脂、或未纤维强化的环氧树脂或聚酰亚胺树脂。
4.根据权利要求1所述的半导体装置，其特征在于，
在所述半导体衬底上，设置有连接垫和与所述连接垫连接而设置的配线，所述外部连接用电极设置在所述配线的接合区上。
5.根据权利要求1所述的半导体装置，其特征在于，
所述半导体衬底由粘着剂层粘着到基板上。
6.根据权利要求1所述的半导体装置，其特征在于，
在所述密封层上，上层配线被设置为，不经由绝缘膜而直接连接到所述外部连接用电极。
7.根据权利要求1所述的半导体装置，其特征在于，
所述外部连接用电极是柱状电极。
8.一种半导体装置的制造方法，其特征在于，包括以下工序：
将多个半导体结构体载置在基板上，该半导体结构体具有凸设在半导体衬底表面的外部连接用电极，
在除了所述外部连接用电极以外的所述半导体衬底上、和包含所述半导体衬底侧面的所述基板上层叠密封层。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述密封层的层叠，是在所述半导体衬底和所述基板上重叠半固化片，使所述外部连接用电极贯通所述半固化片，并使所述半固化片硬化，从而使所述半固化片成为所述密封层。
10.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述半导体衬底是被芯片化的衬底，
在层叠所述密封层之前，将多个所述半导体衬底搭载在所述基板上，
所述密封层的层叠，是在所述基板和多个所述半导体衬底上重叠半固化片，使所述外部连接用电极贯通所述半固化片，并使所述半固化片硬化，从而使所述半固化片成为所述密封层，
在层叠所述密封层之后，切割所述基板和所述密封层。
11.根据权利要求9所述的半导体装置的制造方法，其特征在于，
所述半固化片是一层的，是玻璃纤维强化环氧树脂、玻璃纤维强化聚酰亚胺树脂、或未纤维强化的环氧树脂或聚酰亚胺树脂。
12.根据权利要求8所述的半导体装置的制造方法，其特征在于，
在所述半导体衬底上，形成连接垫和与所述连接垫连接而形成的配线，所述外部连接用电极形成在所述配线的接合区上。
13.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述半导体衬底由粘着剂层粘着到基板上。
14.根据权利要求8所述的半导体装置的制造方法，其特征在于，
在所述密封层上，不经由绝缘膜而直接连接到所述外部连接用电极地形成上层配线。
15.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述外部连接用电极是柱状电极。
CN2010106108929A 2009-11-13 2010-11-12 在基板上搭载半导体结构体的半导体装置及其制造方法 Pending CN102142417A (zh)

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