CN102136827A - Differential amplifier capable of compensating input offset voltage and compensating method - Google Patents

Abstract

The invention discloses a differential amplifier capable of compensating input offset voltage, which comprises differential input geminate transistors including a first transistor and a second transistor, wherein a source electrode of the first transistor is connected with a current source through a first polarity fuse switch, a source electrode of the second transistor is connected with the current source through a second polarity fuse switch, a plurality of trimmer resistors are serially connected between the source electrode of the first transistor and the source electrode of the second transistor, and each trimmer resistor is connected with a resistance fuse switch in parallel. Simultaneously, the invention also provides an input offset voltage compensating method. The differential amplifier capable of compensating input offset voltage and the compensating method adopt a resistance trimming network to compensate the input offset voltage, and maintain the symmetrical appearance of the differential geminate transistors; and simultaneously, a drift compensation mechanism is also provided.

Description

Can compensate the differential amplifier and the compensation method of input offset voltage

[technical field]

The present invention relates to electronic applications, particularly a kind of circuit and method that compensates the input offset voltage in the differential amplifier by semifixed resistor introducing trim voltage.

[background technology]

Differential amplifier also claims differential amplifier, is a kind of circuit that the difference of two input voltages can be amplified.Differential amplifier is usually used in direct current and amplifies, and it can be the balance input and output, also can be single-ended (non-equilibrium) input and output, is commonly used to realize the mutual conversion of balance and unbalanced circuit, is a kind of elementary cell of various integrated circuits.

Please refer to Fig. 1, it shows the structural representation of a kind of typical differential amplifier 100 of the prior art.Described differential amplifier 100 comprises first branch road that is formed by NMOS pipe M1 and the 3rd NMOS pipe M3 and second branch road that is formed by the 2nd NMOS pipe M2 and the 4th NMOS pipe M4.Wherein the grid of the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 links to each other and the grid of the 3rd NMOS pipe M3 self links to each other with draining.Wherein the grid of NMOS pipe M1 is as an input V of described differential amplifier 100 _p, the grid of described the 2nd NMOS pipe M2 is as another input V of described differential amplifier 100 _N, the voltage between the source electrode of the drain electrode of described the 2nd NMOS pipe M2 and described the 4th NMOS pipe M4 is as the output of described differential amplifier 100.

Desirable differential amplifier should be 0 o'clock at input voltage, and output voltage also is 0.But because in the actual conditions, reasons such as asymmetry owing to manufacturing process and device, be difficult to accomplish that two input stages of described differential amplifier are symmetrical fully, so can produce input voltage is 0 o'clock, output voltage is not 0 situation, at this moment, need make that described output voltage is 0 in the certain bucking voltage of input input of described differential amplifier, described bucking voltage also claims input offset voltage.In application number is 200810003736.9 Chinese patent " compensation method of amplifier DC offset voltage and device ", a kind of compensation method and device of DC offset voltage of amplifier are provided, and its main thought is to eliminate imbalance by the breadth length ratio of regulating NMOS pipe M1 as shown in fig. 1 or the 2nd NMOS pipe M2.But there are two shortcomings in the compensation method of the DC offset voltage of this Patent publish with device: first, this method makes the NMOS that wins manage M1 or the 2nd NMOS pipe M2 has had asymmetric structure, when variations in temperature, can produce new imbalance and temperature and float phenomenon so; The second, need comparatively complicated control circuit, increased circuit complexity and chip area.

Therefore, be necessary to propose a kind of new technical scheme and solve the problems referred to above.

[summary of the invention]

The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit avoiding the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used to limit the scope of the invention.

One object of the present invention is to provide a kind of differential amplifier that compensates input offset voltage, its inside includes the resistor trimming network that is used to produce trim voltage, and proofreaies and correct input offset voltage and carry out temperature-compensating with the trim voltage that this resistor trimming network produces.

Another object of the present invention is to provide a kind of compensation method of input offset voltage of differential amplifier, its by regulating the fuse in the resistor trimming network conducting and end and produce suitable trim voltage, and by producing fine-adjusting current based on current mirroring circuit with the resistance of the same temperature coefficient of semifixed resistor.

In order to reach purpose of the present invention, according to an aspect of the present invention, the invention provides a kind of differential amplifier that compensates input offset voltage, described differential amplifier comprises: imported pipe by the difference that the first transistor and transistor seconds form, the source electrode of described the first transistor links to each other with a current source via the first polarity fuse switch, the source electrode of described transistor seconds links to each other with described current source via the second polarity fuse switch, be in series with several semifixed resistors between the source electrode of described the first transistor and the source electrode of transistor seconds, each semifixed resistor melting resistance disconnecting switch in parallel.

Further, described the first transistor and transistor seconds are the NMOS pipes, the drain electrode of described the first transistor and transistor seconds links to each other with a constant-current source, described constant-current source comprises the 3rd NMOS pipe and the 4th NMOS pipe, wherein the drain electrode of the 3rd NMOS pipe and the 4th NMOS pipe connects power supply, described the 3rd NMOS pipe links to each other with the grid of the 4th NMOS pipe and the grid of the 3rd NMOS pipe self links to each other with drain electrode, the drain electrode of described the first transistor connects the source electrode of described the 3rd NMOS pipe, and the drain electrode of described transistor seconds connects the source electrode of described the 4th NMOS pipe.

Further, the resistance difference of the semifixed resistor of described several series connection, be in fusing or conducting state with described semifixed resistor parallel resistor fuse switch, one in the described first polarity fuse switch and the second polarity fuse switch is in blown state.

Further, the electric current that described current source provides is by reference voltage and the electric current of biasing resistor generation or the image current of described electric current, described reference voltage has and the described difference input temperature coefficient identical to the threshold voltage difference of pipe, and described biasing resistor has the temperature coefficient identical with described semifixed resistor.

Further, described current source comprises first branch road, mirror image first electric current that produce first electric current by reference voltage and biasing resistor with second branch road that produces second electric current and the 3rd branch road of described second electric current of mirror image,

Described first branch road comprises the 8th NMOS pipe of series connection, the 9th NMOS pipe and biasing resistor, the drain electrode of described the 8th NMOS pipe connects power supply, the source electrode of described the 8th NMOS pipe links to each other with the drain electrode of the 9th NMOS pipe, the source electrode of described the 9th NMOS pipe links to each other with an end of described biasing resistor, the other end ground connection of described biasing resistor, described first branch road also comprises a comparator, an input input reference voltage of described comparator, between one end of another input connection of described comparator and the source electrode of described the 9th NMOS pipe and described biasing resistor, the output of described comparator connects the grid of described the 9th NMOS pipe

Described second branch road comprises the 7th NMOS pipe and the 6th NMOS pipe of series connection, the drain electrode of described the 7th NMOS pipe connects power supply, the source electrode of described the 7th NMOS pipe links to each other with the drain electrode of described the 6th NMOS pipe, the grid of described the 7th NMOS pipe links to each other with the grid of described the 8th NMOS pipe, and the grid of described the 8th NMOS pipe links to each other with self source electrode

Described the 3rd branch road comprises the 5th NMOS pipe, the drain electrode of described the 5th NMOS pipe is connected in the described first polarity fuse switch and the second polarity fuse switch, the source ground of described the 5th NMOS pipe, the grid of described the 5th NMOS pipe links to each other with the grid of described the 6th NMOS pipe, and the drain electrode of described the 6th NMOS pipe links to each other with self grid.

Further, described difference input is operated in sub-threshold region to pipe, and the breadth length ratio of described the first transistor is identical with the breadth length ratio of described transistor seconds.

According to a further aspect in the invention, the invention provides a kind of compensation method of input offset voltage, described compensation method comprises: the input offset voltage of measuring described differential amplifier; Determine the melting resistance disconnecting switch of needs fusing according to the size of described input offset voltage; Determine some in the fusing first polarity fuse switch or the second polarity fuse switch according to the polarity of described input offset voltage, make the input offset voltage of described differential amplifier equal or level off to 0.

Further, described compensation method also is included in the design phase of described differential amplifier, the breadth length ratio of described difference input to pipe is set, make described difference input be operated in sub-threshold region to pipe, near threshold voltage, therefore described difference input is leading by threshold voltage to the gate source voltage mismatch of pipe to the gate source voltage of pipe in described difference input this moment.

Further, described size according to described input offset voltage determines that the melting resistance disconnecting switch of needs fusing comprises:

A merchant of/2nd according to the current value of electric current in the magnitude of voltage of described input offset voltage and the described current source determines the total resistance of needed semifixed resistor; With

Decide the melting resistance disconnecting switch of needs fusing according to the resistance of the total resistance of needed semifixed resistor and each semifixed resistor.

Further, described compensation method comprises that also employing acts on the electric current of biasing resistor generation and the current source that image current provides described differential amplifier thereof based on a reference voltage, described reference voltage has and the described difference input temperature coefficient identical to the threshold voltage difference of pipe, and described biasing resistor has the temperature coefficient identical with described semifixed resistor.

Compared with prior art, the differential amplifier of compensated for the input offset voltage among the present invention and bearing calibration have the following advantages:

First, employing resistor trimming network is introduced semifixed resistor and then is produced trim voltage to compensate described input offset voltage, by adjusting the fusing and the conducting of melting resistance disconnecting switch, the first polarity fuse switch and the second polarity fuse switch in the described resistor trimming network, can realize different resistances and the semifixed resistor that is in different branch, and then the trim voltage of different sizes of generation and polarity compensate described input offset voltage;

The second, the biasing resistor and the semifixed resistor that adopt identical material to make can make described trim voltage and reference voltage have identical temperature coefficient;

The 3rd, by the difference input is set pipe is operated in sub-threshold region, make input offset voltage leading by the mismatch threshold voltage difference.Select for use reference voltage to float according to concrete manufacturing process with the temperature of compensation input offset voltage with suitable temperature coefficient.

[description of drawings]

In conjunction with reaching ensuing detailed description with reference to the accompanying drawings, the present invention will be more readily understood, the structure member that wherein same Reference numeral is corresponding same, wherein:

Fig. 1 is the structural representation of a kind of typical differential amplifier of the prior art;

Fig. 2 is the differential amplifier equivalent circuit diagram in one embodiment among the present invention;

Fig. 3 is the differential amplifier equivalent circuit diagram in another embodiment among the present invention;

Fig. 4 is the differential amplifier circuit diagram in one embodiment among the present invention;

Fig. 5 is the resistor trimming network circuit diagram in one embodiment among the present invention;

Fig. 6 is the differential amplifier circuit diagram in another embodiment among the present invention; With

Fig. 7 is the compensation method method flow diagram in one embodiment of the input offset voltage among the present invention.

[embodiment]

Detailed description of the present invention is mainly come the running of direct or indirect simulation technical solution of the present invention by program, step, logical block, process or other symbolistic descriptions.Be the thorough the present invention that understands, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the present invention then may still can realize.Affiliated those of skill in the art use these descriptions herein and state that the others skilled in the art in affiliated field effectively introduce their work essence.In other words, be the purpose of the present invention of avoiding confusion, owing to method, program, composition and the circuit known are readily appreciated that, so they are not described in detail.

Alleged herein " embodiment " or " embodiment " are meant special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different in this manual local " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or optionally mutually exclusive with other embodiment embodiment.In addition, represent the sequence of modules in method, flow chart or the functional block diagram of one or more embodiment and revocablely refer to any particular order, also be not construed as limiting the invention.

Differential amplifier among the present invention has been introduced trim voltage and has been compensated input offset voltage, described trim voltage is produced by the electric current of the semifixed resistor of introducing in the differential input stage and the described semifixed resistor of flowing through, and the electric current of the described described semifixed resistor of flowing through is provided by a current source.On the one hand, the present invention adopts the resistor trimming network to realize described semifixed resistor, by adjusting the fusing and the conducting of melting resistance disconnecting switch, the first polarity fuse switch and the second polarity fuse switch in the described resistor trimming network, can realize different resistances and the semifixed resistor that is in different branch, and then the trim voltage of different sizes of generation and polarity compensate described input offset voltage.On the other hand, current source among the present invention acts on electric current and the image current generation thereof that biasing resistor generates based on a reference voltage, described reference voltage has and the described difference input temperature coefficient identical to the threshold voltage difference of pipe, described biasing resistor has the temperature coefficient identical with described semifixed resistor, floats with the temperature that reaches the described input offset voltage of compensation.

Please refer to Fig. 2 and Fig. 3, it shows the equivalent schematic of differential amplifier in an embodiment 200 among the present invention.Described differential amplifier 200 comprises first branch road that is formed by NMOS pipe M1 and the 3rd NMOS pipe M3 and second branch road that is formed by the 2nd NMOS pipe M2 and the 4th NMOS pipe M4.Wherein the drain electrode of the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 meets power supply VCC, and the grid of described the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 links to each other and the grid of the 3rd NMOS pipe M3 self links to each other with source electrode.The drain electrode of described NMOS pipe M1 connects the source electrode of described the 3rd NMOS pipe M3, and the drain electrode of described the 2nd NMOS pipe M2 connects the source electrode of described the 4th NMOS pipe M4, and the source electrode of described NMOS pipe M1 and described the 2nd NMOS pipe M2 is simultaneously via a variable current source I _sGround connection.Wherein the grid of NMOS pipe M1 is as an input V of described differential amplifier 200 _p, the grid of described the 2nd NMOS pipe M2 is as another input V of described differential amplifier 200 _N, the voltage between the source electrode of the drain electrode of described the 2nd NMOS pipe M2 and described the 4th NMOS pipe M4 is as the output V of described differential amplifier 200 _o

In order to compensate the input offset voltage V of described differential amplifier 200 _Os, can be according to described input offset voltage V _OsPositive and negative and big or small in described first branch road or second branch road series connection semifixed resistor R _Trim, by described semifixed resistor R _TrimElectric current I with the described semifixed resistor of flowing through _TrimCan produce trim voltage V _Trim=R _Trim* I _TrimCompensate described input offset voltage V _OsMake that the output voltage of described differential amplifier 200 is 0.

Specifically, described semifixed resistor R _TrimRealize by resistor trimming network (Trimming Network).Please continue with reference to figure 4 in conjunction with Fig. 2 and Fig. 3, it shows the enforcement schematic diagram of differential amplifier in an embodiment 400 among the present invention.Include resistor trimming network 420 in the described differential amplifier 400, described resistor trimming network 420 comprises some to semifixed resistor combination 422 between the source electrode of the source electrode that is connected on described NMOS pipe M1 and described the 2nd NMOS pipe M2, and every pair of semifixed resistor combination 422 comprises semifixed resistor and the melting resistance disconnecting switch that is connected in parallel.Easily full of beard reaches, by controlling described some connected sum fusing to the melting resistance disconnecting switch in the semifixed resistor combination 422, the source electrode and described the 2nd NMOS that can change described NMOS pipe M1 manage the resistance of connecting between the source electrode of M2, such as in one embodiment, described some to including three pairs of semifixed resistor combinations in the semifixed resistor combination 422, as shown in Figure 5, the semifixed resistor R during wherein first pair of semifixed resistor makes up _Trim1, the semifixed resistor R in the second pair of semifixed resistor combination _Trim2With the semifixed resistor R in the 3rd pair of semifixed resistor combination _Trim3Resistance value ratio be 1: 2: 4.Suppose described semifixed resistor R _Trim1Resistance be a standard unit (this standard unit can specifically be set by the designer), as the first melting resistance disconnecting switch F ₁Fusing, the second melting resistance disconnecting switch F ₂With the 3rd melting resistance disconnecting switch F ₃During conducting, the resistance of connecting between the source electrode of the source electrode of described NMOS pipe M1 and described the 2nd NMOS pipe M2 just is a standard unit; As the second melting resistance disconnecting switch F ₂Fusing, the first melting resistance disconnecting switch F ₁With the 3rd melting resistance disconnecting switch F ₃During conducting, the resistance of connecting between the source electrode of the source electrode of described NMOS pipe M1 and described the 2nd NMOS pipe M2 just is two standard units; As the first melting resistance disconnecting switch F ₁With the second melting resistance disconnecting switch F ₂Fusing, the 3rd melting resistance disconnecting switch F ₃During conducting, the resistance of connecting between the source electrode of the source electrode of described NMOS pipe M1 and described the 2nd NMOS pipe M2 just is three standard units; As the first melting resistance disconnecting switch F ₁With the second melting resistance disconnecting switch F ₂Conducting, the 3rd melting resistance disconnecting switch F ₃During fusing, the resistance of connecting between the source electrode of the source electrode of described NMOS pipe M1 and described the 2nd NMOS pipe M2 just is four standard units, ..., and the like, the resistance of connecting between the source electrode of the source electrode of described NMOS pipe M1 and described the 2nd NMOS pipe M2 can be arbitrary in one to seven standard unit.Certainly, described some number of combinations that semifixed resistor is made up in 422 not necessarily only are three pairs, and each resistance to semifixed resistor in the described semifixed resistor combination 422 also not necessarily must be identical or different, decides on specific embodiment.

Described resistor trimming network 420 also comprises source electrode and the current source I that is connected on described NMOS pipe M1 _sBetween the first polarity fuse switch F _p, and be connected on the source electrode of described the 2nd NMOS pipe M2 and the second polarity fuse switch F between the current source 430 _NThe described first polarity fuse switch F _pWith the second polarity fuse switch F _NConducting and fusing decision by described some trim voltage V that semifixed resistor combination 422 is produced _TrimSuch as, the described first polarity fuse switch F _pFusing, and the second polarity fuse switch F _NDuring conducting, described differential amplifier 400 is equivalent to differential amplifier 200 as described in Figure 2; And as the described first polarity fuse switch F _pConducting, and the second polarity fuse switch F _NDuring fusing, described differential amplifier 400 is equivalent to differential amplifier 200 as described in Figure 3.

In sum, the differential amplifier among the present invention has creatively been introduced the resistor trimming network and has been produced trim voltage V _TrimWherein, some semifixed resistor is made up in the resistor trimming network can realize adjusting described semifixed resistor R _TrimThe effect of size of resistance; The described first polarity fuse switch F _pWith the second polarity fuse switch F _NCan realize adjusting described trim voltage V _TrimThe polarity effect.Because the differential amplifier among the present invention has kept the symmetric form of differential pair tube, so when variations in temperature, described differential pair tube can not produce new imbalance, simultaneously in order to compensate described differential pair tube and semifixed resistor R _TrimTemperature drift, the present invention also provides described current source I _sThe generation circuit, described current source I _sCan be based on a reference voltage V _RefAct on biasing resistor R _BiasThe image current of the electric current that generates generates, described reference voltage V _RefHave and the threshold voltage difference Δ V of described difference input pipe _ThIdentical temperature coefficient, described biasing resistor R _BiasHave and described semifixed resistor R _TrimIdentical temperature coefficient is to reach the described input offset voltage V of compensation _OsTemperature float.

Please refer to Fig. 6, it shows the enforcement schematic diagram of differential amplifier in another embodiment 600 among the present invention.Described differential amplifier 600 not only comprises the basic structure of differential amplifier described in Fig. 4, also comprise an electric current source generating circuit 620, described electric current source generating circuit 620 comprises comparator 622, by the 8th NMOS pipe M8, the 9th NMOS pipe M9 and the biasing resistor R of series connection _BiasThe 3rd branch road that forms, the 4th branch road that forms by the 7th NMOS pipe M7 and the 6th NMOS pipe M6 of series connection and be connected in the described first polarity fuse switch F _pWith the second polarity fuse switch F _NAnd the 5th NMOS between the ground connection GND manages M5.Wherein constitute current mirroring circuit mutually between the 3rd branch road and the 4th branch road, the 6th NMOS pipe M6 and the 5th NMOS pipe M5.Wherein the 8th NMOS pipe M8 links to each other with the grid of the 7th NMOS pipe M7, and the grid of the 8th NMOS pipe M8 links to each other with source electrode; The grid of described the 6th NMOS pipe M6 and the 5th NMOS pipe M5 links to each other, and the grid of the 6th NMOS pipe M8 links to each other with drain electrode.

The output of described comparator 622 is connected in the grid of described the 9th NMOS pipe M9, and an input of described comparator 622 connects the source electrode with described the 9th NMOS pipe M9.By above-mentioned structure, another input input reference voltage V of described comparator 622 _RefThe time, at source electrode and the described biasing resistor R of described the 9th NMOS pipe M9 _BiasBetween magnitude of voltage also equal reference voltage V _RefMagnitude of voltage.The described described biasing resistor R that flows through _BiasElectric current I _b=V _Ref/ R _BiasGive described the 5th NMOS pipe M5 through the current mirroring circuit image copying that comprises described the 3rd branch road, the 4th branch road etc., the electric current of described the 5th NMOS pipe M5 that then flows through is Then described

Wherein

Obviously, described V _TrimFor the trim voltage of introducing by the resistor trimming network, work as R _TrimAnd R _BiasWhen selecting the resistance with material for use, can be so that V _TrimHave and V _RefIdentical temperature coefficient.Only need select the reference voltage V of suitable temperature coefficient for use _RefJust can be to input offset voltage V _OSTemperature coefficient compensate, make input offset voltage V _OSTemperature is floated and is improved.

Described differential amplifier is when IC designs, the breadth length ratio of the difference input of described differential amplifier inside to pipe need be set, make described difference input be operated in sub-threshold region to pipe, this moment, gate source voltage approached threshold voltage, and therefore described difference input is leading by threshold voltage to the gate source voltage mismatch of pipe.That is to say, NMOS pipe M1 and the 2nd NMOS pipe M2 at first is set is operated in sub-threshold region that this moment, drain current and the gate source voltage of the one NMOS pipe M1 and the 2nd NMOS pipe M2 had exponential relationship:

$I_D=I_{D0}\×\left(\frac{w}{l}\right)\×\exp \left(\frac{V_{\mathrm{gs}}-V_{\mathrm{th}}}{n\×V_T}\right)$

Wherein n is a sub-threshold slope, V _TBe thermoelectric potential, V _T=kt/q, I _D0Be the elaboration relevant with manufacturing process, V _ThBe threshold voltage.

The breadth length ratio of the one NMOS pipe M1 and the 2nd NMOS pipe M2 is set respectively, makes:

Make

Also be V _Gs-V _Th=0, V _Gs=V _Th

This moment metal-oxide-semiconductor gate source voltage V _GsMisalignment voltage by threshold voltage V _ThDominate, then input offset voltage V _OSFor:

V _OS＝V _P-V _N＝(V _P-V _S)-(V _N-V _S)

＝(V _gs1-V _gs2)+V _trim

＝(V _th1-V _th2)+V _trim

＝ΔV _th+V _trim

Because described differential amplifier is after initial production, all fuse switchs all are in conducting state, so described trim voltage V _Trim=0.And at this moment need suitable fuse switch fusing, to adjust described trim voltage V _TrimSize and polarity, make the input offset voltage V of described differential amplifier _OSEqual or level off to 0.For this reason, the invention provides a kind of compensation method of input offset voltage.

Please refer to Fig. 7, it shows the method flow diagram of input offset voltage compensation method in an embodiment 700 of the differential amplifier among the present invention.Described input offset voltage compensation method 700 goes for being similar to the compensation of the input offset voltage of Fig. 4 or the differential amplifier that comprises the resistor trimming network shown in Figure 6.Described input offset voltage compensation method 700 comprises:

Step 702 is measured the input offset voltage V of described differential amplifier _Os

Input offset voltage V _OS=Δ V _Th+ V _Trim, and initial V _Trim=0, then this moment the reality that measures input offset voltage V ^* _Os=Δ V _Th

Step 704 is determined the melting resistance disconnecting switch that needs fuse according to the size of described input offset voltage, determines the fusing first polarity fuse switch F according to the polarity of described input offset voltage _pThe perhaps second polarity fuse switch F _NIn some, make the input offset voltage of described differential amplifier equal or level off to 0;

In order to make described input offset voltage V _OsEqual or level off to 0.Need the compensation size to equal | V ^* _Os|, polarity and V ^* _OsOpposite V _TrimFor this reason, on the one hand, according to the input offset voltage V that measures ^* _OsPolarity, can determine to need the fusing first polarity fuse switch F _pThe perhaps second polarity fuse switch F _NIn which, such as fusing the first polarity fuse switch F _p, can be with semifixed resistor R _TrimPlace first branch road, produce positive trim voltage V _TrimAnd the second polarity fuse switch F that fuses _N, can be with semifixed resistor R _TrimPlace second branch road, produce negative trim voltage V _Trim

On the other hand, can determine the melting resistance disconnecting switch that needs fuse according to the size of described input offset voltage, so that obtain suitable semifixed resistor resistance.Specifically, 1/2nd merchant according to the current value of electric current in the magnitude of voltage of the input offset voltage that measures in the step 702 and the described current source can calculate needed semifixed resistor R _TrimTotal resistance the electric current in first branch road and second branch road because described current source is flowed through respectively, every branch road is 1/2nd of a described current source current.And the size of current in the described current source is by described reference voltage V _REFDecision, as can be known described by preamble, trim voltage V _TrimSize:

$\left|V_{\mathrm{trim}}\right|=k\×\frac{R_{\mathrm{trim}}}{R_{\mathrm{bias}}}\×V_{\mathrm{REF}},$ Wherein $k=\frac{1}{2}\×\frac{{(w/l)}_5\×{(w/l)}_7}{{(w/l)}_6\×{(w/l)}_8}.$

So according to the input offset voltage V that measures _OsSize and the reference voltage V of employing _REFSize, the substitution following formula just can calculate needed semifixed resistor R _TrimTotal resistance.Then according to needed semifixed resistor R _TrimTotal resistance and the concrete resistance of each semifixed resistor of described differential amplifier inside just can determine which melting resistance disconnecting switch that fuse.Can adopt big current fusing mode or laser blown mode to fuse then needs the fuse switch of fusing, finishes preliminary compensation process.

Step 706, employing acts on the electric current of biasing resistor generation and the current source that image current provides described differential amplifier thereof based on a reference voltage, described reference voltage has and the described difference input temperature coefficient identical to the threshold voltage difference of pipe, and described biasing resistor has the temperature coefficient identical with described semifixed resistor.

In addition, by aforementioned content as can be known, work as R _TrimAnd R _BiasWhen selecting the resistance with material for use, can be so that V _TrimHave and V _RefIdentical temperature coefficient.Then described input offset voltage V _OSTemperature coefficient be:

$\frac{{\mathrm{dV}}_{\mathrm{OS}}}{\mathrm{dT}}=\frac{d}{\mathrm{dT}}(\mathrm{\Δ}{V}_{\mathrm{th}}+V_{\mathrm{trim}})$

$=\frac{d}{\mathrm{dT}}(\mathrm{\Δ}{V}_{\mathrm{th}}+k\×\frac{R_{\mathrm{trim}}}{R_{\mathrm{bias}}}\×V_{\mathrm{ref}})$

$=\frac{\mathrm{d\Δ}{V}_{\mathrm{th}}}{\mathrm{dT}}+k\×\frac{R_{\mathrm{trim}}}{R_{\mathrm{bias}}}\×\frac{{\mathrm{dV}}_{\mathrm{ref}}}{\mathrm{dT}}$

Because input offset voltage V _OSTemperature coefficient by mismatch threshold voltage Δ V _ThTemperature coefficient leading, the manufacturing process that adopts with design is relevant, has the reference voltage V of suitable temperature coefficient according to selecting for use of concrete technology _RefCan be to input offset voltage V _OSTemperature coefficient compensate, make V _OSTemperature is floated and is improved.In specific embodiment, be directed to different manufacturing process, the temperature coefficient of the input offset voltage of the differential amplifier that finally obtains can have nothing in common with each other.Can be by the temperature coefficient of a large amount of prints in observing same batch, and determine average temperature coefficient or preferred temperature coefficient according to these a large amount of print temperatures coefficient, come suitable adjustment corresponding reference voltage V according to this average temperature coefficient or preferred temperature coefficient _REFTemperature coefficient, so just can carry out the temperature-compensating of input offset voltage at different manufacturing process.If the manufacturing process randomness that adopts is bigger, the temperature coefficient of print also be positive and negative at random, so also can consider for reference voltage V _REFAdopt zero-temperature coefficient, even so just guarantee to compensate the temperature coefficient of input offset voltage, it is poorer at least also can not become.

Though be the embodiment that adopts the NMOS pipe among each embodiment herein; but should recognize; those skilled in the art can associate many details of the embodiment of the relevant PMOS of employing pipe at an easy rate according to this paper associated description; so this paper is not repeated this partial content, but the embodiment of relevant employing PMOS pipe belongs to protection scope of the present invention equally.

Above-mentioned explanation has fully disclosed the specific embodiment of the present invention.It is pointed out that and be familiar with the scope that any change that the person skilled in art does the specific embodiment of the present invention does not all break away from claims of the present invention.Correspondingly, the scope of claim of the present invention also is not limited only to described embodiment.

Claims (10)

1. differential amplifier that can compensate input offset voltage is characterized in that it comprises:

Imported pipe by the difference that the first transistor and transistor seconds form, the source electrode of described the first transistor links to each other with a current source via the first polarity fuse switch, and the source electrode of described transistor seconds links to each other with described current source via the second polarity fuse switch,

Be in series with several semifixed resistors between the source electrode of described the first transistor and the source electrode of transistor seconds, each semifixed resistor melting resistance disconnecting switch in parallel.

2. differential amplifier according to claim 1, it is characterized in that, described the first transistor and transistor seconds are the NMOS pipes, the drain electrode of described the first transistor and transistor seconds links to each other with a constant-current source, described constant-current source comprises the 3rd NMOS pipe and the 4th NMOS pipe, wherein the drain electrode of the 3rd NMOS pipe and the 4th NMOS pipe connects power supply, described the 3rd NMOS pipe links to each other with the grid of the 4th NMOS pipe and the grid of the 3rd NMOS pipe self links to each other with drain electrode, the drain electrode of described the first transistor connects the source electrode of described the 3rd NMOS pipe, and the drain electrode of described transistor seconds connects the source electrode of described the 4th NMOS pipe.

3. differential amplifier according to claim 1, it is characterized in that, the resistance difference of the semifixed resistor of described several series connection, be in fusing or conducting state with described semifixed resistor parallel resistor fuse switch, one in the described first polarity fuse switch and the second polarity fuse switch is in blown state.

4. differential amplifier according to claim 1, it is characterized in that, the electric current that described current source provides is by reference voltage and the electric current of biasing resistor generation or the image current of described electric current, described reference voltage has and the described difference input temperature coefficient identical to the threshold voltage difference of pipe, and described biasing resistor has the temperature coefficient identical with described semifixed resistor.

5. differential amplifier according to claim 4, it is characterized in that, described current source comprises that first branch road, mirror image first electric current that produce first electric current by reference voltage and biasing resistor is with second branch road that produces second electric current and the 3rd branch road of described second electric current of mirror image

Described first branch road comprises the 8th NMOS pipe of series connection, the 9th NMOS pipe and biasing resistor, the drain electrode of described the 8th NMOS pipe connects power supply, the source electrode of described the 8th NMOS pipe links to each other with the drain electrode of the 9th NMOS pipe, the source electrode of described the 9th NMOS pipe links to each other with an end of described biasing resistor, the other end ground connection of described biasing resistor, described first branch road also comprises a comparator, an input input reference voltage of described comparator, between one end of another input connection of described comparator and the source electrode of described the 9th NMOS pipe and described biasing resistor, the output of described comparator connects the grid of described the 9th NMOS pipe

Described second branch road comprises the 7th NMOS pipe and the 6th NMOS pipe of series connection, the drain electrode of described the 7th NMOS pipe connects power supply, the source electrode of described the 7th NMOS pipe links to each other with the drain electrode of described the 6th NMOS pipe, the grid of described the 7th NMOS pipe links to each other with the grid of described the 8th NMOS pipe, and the grid of described the 8th NMOS pipe links to each other with self source electrode

Described the 3rd branch road comprises the 5th NMOS pipe, the drain electrode of described the 5th NMOS pipe is connected in the described first polarity fuse switch and the second polarity fuse switch, the source ground of described the 5th NMOS pipe, the grid of described the 5th NMOS pipe links to each other with the grid of described the 6th NMOS pipe, and the drain electrode of described the 6th NMOS pipe links to each other with self grid.

6. according to the arbitrary described differential amplifier of claim 1 to 5, it is characterized in that described difference input is operated in sub-threshold region to pipe, the breadth length ratio of described the first transistor is identical with the breadth length ratio of described transistor seconds.

7. the compensation method of an input offset voltage is applied to it is characterized in that it comprises in the differential amplifier as claimed in claim 1:

Measure the input offset voltage of described differential amplifier;

Determine the melting resistance disconnecting switch of needs fusing according to the size of described input offset voltage; Determine some in the fusing first polarity fuse switch or the second polarity fuse switch according to the polarity of described input offset voltage, make the input offset voltage of described differential amplifier equal or level off to 0.

8. compensation method according to claim 7, it is characterized in that, described compensation method also is included in the design phase of described differential amplifier, the breadth length ratio of described difference input to pipe is set, make described difference input be operated in sub-threshold region to pipe, near threshold voltage, therefore described difference input is leading by threshold voltage to the gate source voltage mismatch of pipe to the gate source voltage of pipe in described difference input this moment.

9. compensation method according to claim 7 is characterized in that, described size according to described input offset voltage determines that the melting resistance disconnecting switch of needs fusing comprises:

A merchant of/2nd according to the current value of electric current in the magnitude of voltage of described input offset voltage and the described current source determines the total resistance of needed semifixed resistor; With

Decide the melting resistance disconnecting switch of needs fusing according to the resistance of the total resistance of needed semifixed resistor and each semifixed resistor.

10. compensation method according to claim 7, it is characterized in that, described compensation method comprises that also employing acts on the electric current of biasing resistor generation and the current source that image current provides described differential amplifier thereof based on a reference voltage, described reference voltage has and the described difference input temperature coefficient identical to the threshold voltage difference of pipe, and described biasing resistor has the temperature coefficient identical with described semifixed resistor.

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