CN107888173A - Electrification reset circuit - Google Patents
Electrification reset circuit Download PDFInfo
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- CN107888173A CN107888173A CN201711452279.7A CN201711452279A CN107888173A CN 107888173 A CN107888173 A CN 107888173A CN 201711452279 A CN201711452279 A CN 201711452279A CN 107888173 A CN107888173 A CN 107888173A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
Abstract
The present invention discloses a kind of electrification reset circuit, and it includes current generating circuit, current mirroring circuit and current comparison circuit, and current generating circuit includes：MOS transistor pair and resistance pair, for producing current signal, current mirroring circuit is used to handle caused current signal；Current comparison circuit is used to produce power-on reset signal.The present invention uses topological structure, make the power-on reset signal of output there is compensation characteristic with the change of environment temperature, and supply voltage upset point is only related to the active device ratio and resistance device ratio of single type, greatly reduce in large-scale production process due to supply voltage upset point offset problem caused by the variation of ambient temperature factor in device discrete type factor and practical work process, dependable performance, low-power consumption.
Description
Technical field
The invention belongs to ic power detection field, and in particular to a kind of electrification reset circuit.
Background technology
The state machine that electrification reset circuit is used to reset digital circuit makes it initial from determination state.For simulating and mixing
Signal circuit, it can act as enabling signal and carrys out state startup of the lock-on circuit from a determination.
Some traditional electrification reset circuits produce power on signal with RC retardation ratio, and such a mode can not be applied to upper electricity
The power supply of velocity variations.Other are caused in large-scale production with two kinds of MOSFET parameters to react supply voltage value
Parameter drift.Further, it may result in higher supply voltage upset point, be not suitable for low voltage application.
Some old circuits set an accurate supply voltage upset point magnitude of voltage with referrer module.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention proposes a kind of electrification reset circuit, using topological structure, makes output
Power-on reset signal there is compensation characteristic with the change of environment temperature, and supply voltage upset point is only active with single type
Device ratio is related to resistance device ratio, greatly reduces in large-scale production process due to device discrete type factor and reality
Supply voltage upset point offset problem caused by variation of ambient temperature factor in the course of work of border.
In order to achieve the above object, technical scheme is as follows：
A kind of electrification reset circuit includes current generating circuit, including：MOS transistor pair and resistance pair, electric current produce electricity
Road is used to produce current signal；MOS transistor to including：Two proportional the first MOS transistors and the second MOS transistor,
The source electrode of first MOS transistor and the second MOS transistor is together connected on the first power line, and the grid of the first MOS transistor leads to
The one end for crossing first resistor is connected with the grid of the second MOS transistor, the drain electrode of the first MOS transistor and one end of first resistor
It is connected；Resistance to including：Two proportional first resistors and second resistance, first resistor are connected on the grid of the first MOS transistor
Between the grid of pole and the second MOS transistor, second resistance is connected on what first resistor did not connected with the drain electrode of the first MOS transistor
Between one end and second source line；Current mirroring circuit, for handling caused current signal；Current comparison circuit, for producing
Power-on reset signal.
The present invention a characteristic be：Produce an electric current upset point associated with supply voltage.Current generating circuit
Including two MOS transistors, their source electrode is connected on the power line of identical first, their grid connect by first resistor every
Open, second resistance is connected on first resistor not between one end of the drain electrode connection of the first MOS transistor and second source line, makes electricity
Flow valuve and supply voltage are associated and complete startup function.
When supply voltage is low, two electric currents all very littles of electric current centering, then flow through the electric current of resistance also very little.Two
The grid of MOS transistor is almost identical to source voltage, and the big MOS transistor of breadth length ratio will flow through larger electric current.Work as power supply
When voltage raises, the electric current increase of resistance between MOS transistor grid is flowed through.Accordingly, the grid of proportional MOS transistor pair
Pole increases to source voltage difference.The MOS transistor for having smaller breadth length ratio when rising on the supply voltage will have larger grid to source
Pole tension causes faster electric current to gather way.Desired voltage overturn point, have smaller breadth length ratio MOS transistor and have compared with
The transistor of big breadth length ratio flows through same current.When supply voltage rises above upset point voltage, there is smaller breadth length ratio
MOS transistor flows through more electric currents, and current comparison circuit output produces a power-on reset signal.
Accordingly, another characteristic of the invention is supply voltage upset point skew caused by compensation temperature.When in temperature
When rising, the grid of MOS transistor diminishes to source voltage causes electric current centering to flow through the electric current change of resistance greatly.On the other hand, it is electric
Another electric current of centering is flowed because the grid of proportional MOS transistor pair can also increase to the positive temperature coefficient of source voltage difference
Add.Temperature-compensating is realized by the breadth length ratio of setting MOS transistor and the ratio of resistance.
On the basis of above-mentioned technical proposal, following improvement can be also done：
As preferable scheme, current mirroring circuit includes：First MOS transistor, the 3rd MOS transistor, the 4th MOS crystal
Pipe and the 5th MOS transistor, the first MOS transistor and the connection of the 3rd MOS transistor mirror image, the 4th MOS transistor and the 5th MOS
Transistor mirror picture connects.
It is simple in construction using above-mentioned preferable scheme.
As preferable scheme, the first MOS transistor and the second MOS transistor are all operated in sub-threshold region.
Using above-mentioned preferable scheme, working stability.
As preferable scheme, electrification reset circuit also includes a phase inverter for being arranged at the circuit output end, anti-phase
Device is used to complete negative function, output signal is returned to logic level values.
Using above-mentioned preferable scheme, phase inverter makes output signal return to logic level values.
As preferable scheme, the breadth length ratio of the first MOS transistor is more than the breadth length ratio of the second MOS transistor.
Using above-mentioned preferable scheme, current crossover point is produced.
As preferable scheme, the first MOS transistor is PMOS transistor MP101；
Second MOS transistor is PMOS transistor MP102；
3rd MOS transistor is PMOS transistor MP103；
4th MOS transistor is nmos pass transistor MN101；
5th MOS transistor is nmos pass transistor MN102；
First resistor is resistance R101；
Second resistance is resistance R102.
PMOS transistor MP101 source electrode is connected to the first power line, and its grid and drain electrode are connected to the one of resistance R101
End；
PMOS transistor MP102 source electrode is connected to the first power line, and its grid is connected to the another of resistance R101 one end
One end, it, which drains, is connected to nmos pass transistor MN101 grid；
PMOS transistor MP103 source electrode is connected to the first power line, and its grid is connected to resistance R101 one end；
Resistance R101 one end is connected with PMOS transistor MP101 drain electrode, and its other end is with PMOS transistor MP102's
Grid connects；
Resistance R102 one end is connected with PMOS transistor MP102 grid, and its other end is with nmos pass transistor MN101's
Source electrode connects；
Nmos pass transistor MN101 source electrode is connected to second source line, and its grid and drain electrode are connected to PMOS transistor
MP102 drain electrode；
Nmos pass transistor MN102 source electrode is connected to second source line, and its grid is connected to PMOS transistor MP102 leakage
Pole.
PMOS transistor MP103 drain electrode is connected with nmos pass transistor MN103 drain electrode, and with phase inverter INV1 input
End connection.
Using above-mentioned preferable scheme, simple in construction, stable performance.
As preferable scheme, the first MOS transistor is PMOS transistor MP201；
Second MOS transistor is PMOS transistor MP202；
3rd MOS transistor is PMOS transistor MP203；
4th MOS transistor is nmos pass transistor MN201；
5th MOS transistor is nmos pass transistor MN202；
First resistor is resistance R201；
Second resistance is resistance R202.
PMOS transistor MP201 source electrode is connected to the first power line, and it, which drains, is connected to resistance R201 one end, its grid
Pole is connected to the resistance R201 other end；
PMOS transistor MP202 source electrode is connected to the first power line, and its grid is connected to resistance R201 one end, and it leaks
Pole is connected to nmos pass transistor MN202 drain electrode；
PMOS transistor MP203 source electrode is connected to the first power line, and its grid is connected to PMOS transistor MP201 grid
Pole, it, which drains, is connected to nmos pass transistor MN201 drain electrode；
Resistance R201 one end is connected with PMOS transistor MP201 drain electrode, and one end of its other end and resistance R202 connects
Connect；
Resistance R202 one end is connected with resistance R201, and its other end is connected to second source line；
Nmos pass transistor MN201 source electrode is connected to second source line, and its grid and drain electrode are connected to PMOS transistor
MP203 drain electrode；
Nmos pass transistor MN202 source electrode is connected to second source line, and its grid is connected to nmos pass transistor MN201 grid
Pole, it, which drains, is connected to PMOS transistor MP202 drain electrode；
Phase inverter INV2 input is connected to PMOS transistor MP202 drain electrode.
Using above-mentioned preferable scheme, simple in construction, stable performance.
Brief description of the drawings
Fig. 1 is a kind of one of structural representation of electrification reset circuit provided in an embodiment of the present invention.
Fig. 2 is the electric current provided in an embodiment of the present invention for respectively flowing through the first MOS transistor and the second MOS transistor with electricity
One of change curve of source voltage.
Fig. 3 is the two of a kind of structural representation of electrification reset circuit provided in an embodiment of the present invention.
Fig. 4 is the electric current provided in an embodiment of the present invention for respectively flowing through the first MOS transistor and the second MOS transistor with electricity
The two of the change curve of source voltage.
Fig. 5 is input voltage before shaping provided in an embodiment of the present invention with process deviation (conor) and temperature deviation
(temp) change curve analogous diagram.
Fig. 6 is output voltage after shaping provided in an embodiment of the present invention with process deviation (conor) and temperature deviation
(temp) change curve analogous diagram.
Embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
A kind of electrification reset circuit includes current generating circuit, current mirroring circuit and current comparison circuit.
Current generating circuit includes：MOS transistor pair and resistance pair, current generating circuit are used to produce current signal.Electricity
Current mirror circuit is used to handle caused current signal.Current comparison circuit is used to produce power-on reset signal.
MOS transistor to including：Two proportional the first MOS transistors and the second MOS transistor.Resistance to including：
Two proportional first resistors and second resistance.Current mirroring circuit includes：First MOS transistor, the 3rd MOS transistor,
Four MOS transistors and the 5th MOS transistor, the first MOS transistor and the connection of the 3rd MOS transistor mirror image, the 4th MOS transistor
Connected with the 5th MOS transistor mirror image.
The breadth length ratio of first MOS transistor is more than the breadth length ratio of the second MOS transistor.
In order to reach the purpose of the present invention, in a kind of some of embodiments of electrification reset circuit,
As shown in figure 1, the first MOS transistor is PMOS transistor MP101；Second MOS transistor is PMOS transistor
MP102；3rd MOS transistor is PMOS transistor MP103；4th MOS transistor is nmos pass transistor MN101；5th MOS is brilliant
Body pipe is nmos pass transistor MN102.
First resistor is resistance R101；Second resistance is resistance R102.
PMOS transistor MP101 source electrode is connected to the first power line node N106, and grid and drain electrode are connected to node
N101.PMOS transistor MP102 source electrode is connected to power line node N106, and grid is connected to node N102, and drain electrode is connected to
Node N103.PMOS transistor MP103 source electrode is connected to the first power line node N106, and grid is connected to node N101, leakage
Pole is connected to node N104.Resistance R101 is connected between node N101 and node N102.Resistance R102 is connected to node N102
Between second source line node N107.Nmos pass transistor MN101 source electrode is connected to second source line node N107, grid and
Drain electrode is connected to node N103.Nmos pass transistor MN102 source electrode is connected to second source line node N107, and grid is connected to section
Point N103, drain electrode are connected to node N104.Phase inverter INV1 input is connected to node N104, and output is connected to node N105.
The function of circuit shown in Fig. 1 is described as follows.
Circuit includes a PMOS transistor to (MP101, MP102), and a resistance is to (R101, R102) and two poles
The nmos pass transistor load (MN101) of pipe connected mode.Flow through PMOS transistor MP101 electric current by current mirror (MP101,
MP103) mirror image exports.Flow through PMOS transistor MP102 electric current be supported MN101 receive and by current mirror (MN101,
MN102) mirror image exports.
PMOS transistor MP103 and nmos pass transistor MN102 drain electrode, which are connected together, performs electric current comparing function.
In other embodiments, circuit may also include a phase inverter INV1 and complete negative function and recover output signal
To logic level values.
It is as follows for the implementation method of the present invention：
The PMOS transistor MP101 of one diode connected mode, resistance R101 and resistance R102 detection supply voltages, production
First electric current of raw current generating circuit.PMOS transistor MP102 grid is connected between resistance R101 and resistance R102,
The nmos pass transistor MN101 that second electric current is connected by diode is produced to receive.Resistance R101 detects first current signal,
PMOS transistor is to producing a voltage difference between MP101 and MP102 grid.Accordingly, PMOS transistor MP101 compares PMOS
Transistor MP102 has larger breadth length ratio to produce current crossover point.Flow through PMOS transistor MP101 first current signal
Exported by PMOS transistor MP103 mirror images.PMOS transistor MP102 second current signal is flowed through by NMOS load transistors
MN101 is received and exported by transistor MN102 mirror images.PMOS transistor MP103 drain electrode and nmos pass transistor MN102 drain electrode
It is connected together, electric current comparing function is completed in node N104.
Waveform shown in corresponding diagram 2, when supply voltage is low, flow through R101 electric current very little so that PMOS transistor MP101
It is roughly the same to source voltage with MP102 grid.In this case, there is the PMOS transistor MP101 of larger breadth length ratio
Bigger electric current is flowed through than transistor MP102.As a result, what PMOS transistor MP103 absorptions were all flows through nmos pass transistor MN102
Electric current, node N104 is in high level, by phase inverter INV1 it is anti-phase after in node N105 produce a logic low.
When supply voltage rise, cause the electric current increase for flowing through resistance R101.As a result, the voltage liter at resistance R101 both ends
It is high.Because the drain current of transistor is majorant of the grid to source voltage, PMOS transistor MP102 electric current is flowed through
Electric current than flowing through transistor MP101 is increased faster.
If supply voltage continues to raise, PMOS transistor MP102 flows through more electric currents than transistor MP101.As a result,
Nmos pass transistor MN102 absorbs all electric currents for flowing through PMOS transistor MP103, causes node N104 to be transformed into by high level low
Level.Then, phase inverter INV1 produces a logic high in node N105.
Under this mode of operation, PMOS transistor MP101 and MP102 are operated between sub-threshold region.Power supply upset point voltage
It is given by the following formula：
It=IMP101=IMP102 (1)
It=Δs VgsMP101, MP102/R101 (2)
VTP=VgsMP101+It* (R101+R102) (3)
Id=(W/L) * Is*exp [Vgs/ (ζ * Vt)] (4)
Δ VgsMP101, MP102=ζ * Vt*ln [(W/L) MP101/ (W/L) MP102] (5)
Final formula is obtained according to formula (1)-(5)：
VTP=VgsMP101+ ζ * Vt*1n (n) * (1+R102/R101) (6)
Wherein, VTP is power supply upset point magnitude of voltage；
VgsMp101 is PMOS transistor MP101 grid to source voltage；
Δ VgsMP101, MP102 are the differences between VgsMp101 and VgsMp102；
ζ is that subthreshold value slope coefficient is about 1.68；
Vt is thermal voltage, the about 26mV in room temperature；
N is the ratio of PMOS transistor (MP101 and MP102) breadth length ratio, and it is specially：N=[(W/L) MP101/ (W/L)
MP102]。
From equation (6) as can be seen that Section 1 VgsMp101 has negative temperature coefficient about -1mV/ Celsius on the right of equation
Degree.Section 2 thermal voltage Vt has about+0.087mV/ degrees Celsius of positive temperature coefficient on the right of equation.
In order to reach VTP single order tc compensation, the ratio of resistance ratio and transistor breadth length ratio is：
Ln (n) * (1+R102/R101)=6.48
Such as：N=8, R102/R101=2.
As R101=1000k Ω, electric current is probably 100nA.
This example illustrates a "ball-park" estimate, can finely tune accurate ratio to reach upset point voltage in difference
Single order tc compensation effect under manufacturing process.
In order to further optimize the implementation result of the present invention, in other embodiment, remaining feature technology phase
Together, difference is,
As shown in figure 3, the first MOS transistor is PMOS transistor MP201；Second MOS transistor is PMOS transistor
MP202；3rd MOS transistor is PMOS transistor MP203；4th MOS transistor is nmos pass transistor MN201；5th MOS is brilliant
Body pipe is nmos pass transistor MN202.
First resistor is resistance R201；Second resistance is resistance R202.
As shown in figure 3, PMOS transistor MP201 source electrode is connected to the first power line node N206, grid is connected to section
Point N201, drain electrode are connected to node N202.PMOS transistor MP202 source electrode is connected to power line node N206, grid connection
To node N202, drain electrode is connected to node N204.PMOS transistor MP203 source electrode is connected to the first power line node N206,
Grid is connected to node N201, and drain electrode is connected to node N203.Resistance R201 is connected between node N202 and node N201.Electricity
Resistance R202 is connected between node N201 and second source line node N207.Nmos pass transistor MN201 source electrode is connected to second
Power line node N207, grid and drain electrode are connected to node N203.Nmos pass transistor MN202 source electrode is connected to second source line
Node N207, grid are connected to node N203, and drain electrode is connected to node N204.Phase inverter INV2 input is connected to node
N204, output are connected to node N205.
Similar to upper one embodiment, circuit function is described as follows shown in Fig. 3：
Circuit includes a PMOS transistor to (MP201, MP202), and a resistance is to (R201, R202).Flow through PMOS
Transistor MP201 electric current is received by PMOS current mirrors (MP201, MP203) mirror image and by nmos pass transistor MN201, then passes through
NMOS current mirrors (MN201, MN202) mirror image exports.
PMOS transistor MP202 and nmos pass transistor MN202 performs electric current comparing function in node N204.Circuit can also wrap
A phase inverter INV2 is included to complete negative function and output signal is returned to logic level values.
As shown in figure 4, when supply voltage is low, flow through resistance R201 electric current very little, PMOS transistor MP201 and
MP202 grid voltage difference very little.Breadth length ratio of the setting PMOS transistor MP202 breadth length ratio more than MP201 is electric to ensure to work as
MP202 has larger current sourcing ability when source voltage ratio is relatively low.Because nmos pass transistor MN202 passes through PMOS current mirrors
(MP201, MP203) and NMOS current mirrors (MN201, MN202) hold PMOS transistor MP201 current signal, and electric current compares
Afterwards, PMOS transistor MP202 flows through all electric currents provided by nmos pass transistor MN202.Node N204 magnitude of voltage is drawn
To a high level.Phase inverter INV2 exports a logic low.When supply voltage raises, the electric current for flowing through resistance R201 increases
Add, cause grid of the PMOS transistor MP202 grid to source voltage than MP201 low to source voltage.As a result, PMOS crystal
Pipe MP202 current sourcing ability is more and more weaker.If supply voltage continues to raise, PMOS transistor MP202 can not be provided
Enough electric currents give nmos pass transistor MN202.Result node N204 is switched to a low level in a certain supply voltage value.It is anti-phase
Device INV2 exports logic high.
Fig. 5 be by phase inverter INV1 or INV2 before, node N104 or node N204 voltage are with process deviation
(conor) and temperature deviation (temp) change curve analogous diagram.
Fig. 6 is that node N105 or node N205 voltage are with process deviation after phase inverter INV1 or INV2
(conor) and temperature deviation (temp) change curve analogous diagram.
According to the simulation figure shown in foregoing description and Fig. 5-6, it is as follows beneficial effects of the present invention can be obtained：
1) characteristic of the invention is：Produce an electric current upset point associated with supply voltage.Electric current produces electricity
Road includes two MOS transistors, and their source electrode is connected on the power line of identical first, their grid connect by first resistor every
Open, second resistance is connected on first resistor not between one end of the drain electrode connection of the first MOS transistor and second source line, makes electricity
Flow valuve and supply voltage are associated and complete startup function.
When supply voltage is low, two electric currents all very littles of electric current centering, then flow through the electric current of resistance also very little.Two
The grid of MOS transistor is almost identical to source voltage, and the big MOS transistor of breadth length ratio will flow through larger electric current.Work as power supply
When voltage raises, the electric current increase of resistance between MOS transistor grid is flowed through.Accordingly, the grid of proportional MOS transistor pair
Pole increases to source voltage difference.The MOS transistor for having smaller breadth length ratio when rising on the supply voltage will have larger grid to source
Pole tension causes faster electric current to gather way.Desired voltage overturn point, have smaller breadth length ratio MOS transistor and have compared with
The transistor of big breadth length ratio flows through same current.When supply voltage rises above upset point voltage, there is smaller breadth length ratio
MOS transistor flows through more electric currents, and current comparison circuit output produces a power-on reset signal.
2) another characteristic of the invention is supply voltage upset point skew caused by compensation temperature.When temperature is raised,
The grid of MOS transistor diminishes to source voltage causes electric current centering to flow through the electric current change of resistance greatly.On the other hand, electric current centering
Another electric current due to proportional MOS transistor pair grid to source voltage difference positive temperature coefficient can also increase.Temperature
Degree compensation is realized by the breadth length ratio of setting MOS transistor and the ratio of resistance.
3) present invention uses topological structure, makes the power-on reset signal of output have compensation special with the change of environment temperature
Property, and supply voltage upset point is only related to the active device ratio and resistance device ratio of single type, greatly reduces
Due to electric caused by the variation of ambient temperature factor in device discrete type factor and practical work process in large-scale production process
Source voltage upset point offset problem.Be used for design temperature coefficient the present invention relates to the device proportionate relationship in circuit, device it is exhausted
Allow in large-scale production have larger skew to value.
4) because topological structure of the present invention is simple, therefore also there is dependable performance, the characteristics of low-power consumption.
The above is only the preferred embodiment of the present invention, it is noted that for the person of ordinary skill of the art,
Without departing from the concept of the premise of the invention, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect scope.
Claims (10)
- A kind of 1. electrification reset circuit, it is characterised in that including：Current generating circuit, including：MOS transistor pair and resistance pair, the current generating circuit are used to produce current signal；MOS transistor to including：Two proportional the first MOS transistors and the second MOS transistor, the first MOS transistor and The source electrode of second MOS transistor is together connected on the first power line, one end that the grid of the first MOS transistor passes through first resistor It is connected with the grid of the second MOS transistor, the drain electrode of the first MOS transistor is connected with one end of first resistor；Resistance to including：Two proportional first resistors and second resistance, first resistor are connected on the grid of the first MOS transistor And second MOS transistor grid between, second resistance be connected on first resistor not with the first MOS transistor drain electrode connection one Between end and second source line；Current mirroring circuit, for handling caused current signal；Current comparison circuit, for producing power-on reset signal.
- 2. electrification reset circuit according to claim 1, it is characterised in that the current mirroring circuit includes：First MOS is brilliant Body pipe, the 3rd MOS transistor, the 4th MOS transistor and the 5th MOS transistor, first MOS transistor and the 3rd MOS are brilliant Body pipe mirror image connects, and the 4th MOS transistor connects with the 5th MOS transistor mirror image.
- 3. electrification reset circuit according to claim 2, it is characterised in that first MOS transistor and described second MOS transistor is all operated in sub-threshold region.
- 4. electrification reset circuit according to claim 3, it is characterised in that the electrification reset circuit also includes being arranged at One phase inverter of the circuit output end, the phase inverter are used to complete negative function, output signal is returned to logic level Value.
- 5. electrification reset circuit according to claim 4, it is characterised in that the breadth length ratio of first MOS transistor is big In the breadth length ratio of second MOS transistor.
- 6. according to the electrification reset circuit described in claim any one of 3-5, it is characterised in thatFirst MOS transistor is PMOS transistor MP101；Second MOS transistor is PMOS transistor MP102；3rd MOS transistor is PMOS transistor MP103；4th MOS transistor is nmos pass transistor MN101；5th MOS transistor is nmos pass transistor MN102；The first resistor is resistance R101；The second resistance is resistance R102.
- 7. electrification reset circuit according to claim 6, it is characterised in that PMOS transistor MP101 source electrode is connected to First power line, its grid and drain electrode are connected to resistance R101 one end；PMOS transistor MP102 source electrode is connected to the first power line, and its grid is connected to the other end of resistance R101 one end, It, which drains, is connected to nmos pass transistor MN101 grid；PMOS transistor MP103 source electrode is connected to the first power line, and its grid is connected to resistance R101 one end；Resistance R101 one end is connected with PMOS transistor MP101 drain electrode, the grid of its other end and PMOS transistor MP102 Connection；Resistance R102 one end is connected with PMOS transistor MP102 grid, the source electrode of its other end and nmos pass transistor MN101 Connection；Nmos pass transistor MN101 source electrode is connected to second source line, and its grid and drain electrode are connected to PMOS transistor MP102's Drain electrode；Nmos pass transistor MN102 source electrode is connected to second source line, and its grid is connected to PMOS transistor MP102 drain electrode.
- 8. electrification reset circuit according to claim 7, it is characterised in that PMOS transistor MP103 drain electrode and NMOS Transistor MN103 drain electrode connection, and be connected with phase inverter INV1 input.
- 9. according to the electrification reset circuit described in claim any one of 3-5, it is characterised in thatFirst MOS transistor is PMOS transistor MP201；Second MOS transistor is PMOS transistor MP202；3rd MOS transistor is PMOS transistor MP203；4th MOS transistor is nmos pass transistor MN201；5th MOS transistor is nmos pass transistor MN202；The first resistor is resistance R201；The second resistance is resistance R202.
- 10. electrification reset circuit according to claim 9, it is characterised in thatPMOS transistor MP201 source electrode is connected to the first power line, and it, which drains, is connected to resistance R201 one end, and its grid connects It is connected to the resistance R201 other end；PMOS transistor MP202 source electrode is connected to the first power line, and its grid is connected to resistance R201 one end, its company of drain electrode It is connected to nmos pass transistor MN202 drain electrode；PMOS transistor MP203 source electrode is connected to the first power line, and its grid is connected to PMOS transistor MP201 grid, It, which drains, is connected to nmos pass transistor MN201 drain electrode；Resistance R201 one end is connected with PMOS transistor MP201 drain electrode, and its other end is connected with resistance R202 one end；Resistance R202 one end is connected with resistance R201, and its other end is connected to second source line；Nmos pass transistor MN201 source electrode is connected to second source line, and its grid and drain electrode are connected to PMOS transistor MP203's Drain electrode；Nmos pass transistor MN202 source electrode is connected to second source line, and its grid is connected to nmos pass transistor MN201 grid, It, which drains, is connected to PMOS transistor MP202 drain electrode；Phase inverter INV2 input is connected to PMOS transistor MP202 drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711452279.7A CN107888173B (en) | 2017-12-27 | 2017-12-27 | Power-on reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711452279.7A CN107888173B (en) | 2017-12-27 | 2017-12-27 | Power-on reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107888173A true CN107888173A (en) | 2018-04-06 |
| CN107888173B CN107888173B (en) | 2024-04-02 |
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| CN201711452279.7A Active CN107888173B (en) | 2017-12-27 | 2017-12-27 | Power-on reset circuit |
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| JP2019220884A (en) * | 2018-06-21 | 2019-12-26 | ラピスセミコンダクタ株式会社 | Semiconductor device and generation method for power-on reset signal |
| WO2022143301A1 (en) * | 2020-12-30 | 2022-07-07 | 合肥市芯海电子科技有限公司 | Power-on reset circuit, integrated circuit and electronic device |
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| Publication number | Publication date |
|---|---|
| CN107888173B (en) | 2024-04-02 |
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Address after: 215600 4 building, H building, Zhangjiagang economic and Technological Development Zone, Jiangsu. Applicant after: SUZHOU FEIDAXU MICRO-ELECTRONICS Co.,Ltd. Address before: 215000 No. 2 Pei Yuan Road, hi tech Zone, Suzhou, Jiangsu Applicant before: SUZHOU FEIDAXU MICRO-ELECTRONICS Co.,Ltd. |
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