CN107888173B - Power-on reset circuit - Google Patents

Power-on reset circuit Download PDF

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Publication number
CN107888173B
CN107888173B CN201711452279.7A CN201711452279A CN107888173B CN 107888173 B CN107888173 B CN 107888173B CN 201711452279 A CN201711452279 A CN 201711452279A CN 107888173 B CN107888173 B CN 107888173B
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resistor
transistor
mos transistor
current
drain
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CN107888173A (en
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陶冬毅
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Shenzhen Zhongming Electronics Co ltd
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Suzhou Feidaxu Micro Electronics Co ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches

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Abstract

The invention discloses a power-on reset circuit, which comprises a current generating circuit, a current mirror circuit and a current comparing circuit, wherein the current generating circuit comprises: a MOS transistor pair and a resistor pair for generating a current signal, and a current mirror circuit for processing the generated current signal; the current comparison circuit is used for generating a power-on reset signal. The invention adopts a topological structure, so that the output power-on reset signal has compensation characteristic along with the change of the ambient temperature, the power supply voltage turning point is only related to the single type of active device ratio and the resistance device ratio, the problem of power supply voltage turning point deviation caused by device discrete factors and the ambient temperature change factors in the actual working process in the large-scale production process is greatly reduced, and the invention has reliable performance and low power consumption.

Description

Power-on reset circuit
Technical Field
The invention belongs to the field of integrated circuit power supply detection, and particularly relates to a power-on reset circuit.
Background
The power-on reset circuit is used to reset the state machine of the digital circuit from a determined state. For analog and mixed signal circuits, it can be used as an enable signal to force the circuit to start from a certain state.
Some conventional power-on reset circuits use RC delays to generate the power-on signal, which is not suitable for power supplies with varying power-on speeds. Others use two types of MOSFET parameters to reflect the supply voltage values, resulting in parameter drift in mass production. Further, it may result in a higher supply voltage switching point, which is not suitable for low voltage applications. Some older circuits use a reference module to set an accurate supply voltage roll-over point voltage value.
Disclosure of Invention
In order to solve the technical problems, the invention provides a power-on reset circuit, which adopts a topological structure to ensure that an output power-on reset signal has compensation characteristics along with the change of the ambient temperature, and a power supply voltage turning point is only related to a single type of active device ratio and a resistor device ratio, so that the problem of power supply voltage turning point deviation caused by device discrete type factors and the ambient temperature change factors in the actual working process in the mass production process is greatly reduced.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a power-on reset circuit comprising a current generating circuit comprising: a MOS transistor pair and a resistor pair, wherein the current generating circuit is used for generating a current signal; the MOS transistor pair includes: the first MOS transistor and the second MOS transistor are in proportion, the sources of the first MOS transistor and the second MOS transistor are connected to the first power line together, the grid electrode of the first MOS transistor is connected with the grid electrode of the second MOS transistor through one end of the first resistor, and the drain electrode of the first MOS transistor is connected with one end of the first resistor; the resistor pair comprises: the first resistor is connected between the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor, and the second resistor is connected between one end of the first resistor which is not connected with the drain electrode of the first MOS transistor and the second power line; a current mirror circuit for processing the generated current signal; and the current comparison circuit is used for generating a power-on reset signal.
One feature of the present invention is: a current switching point associated with the supply voltage is generated. The current generating circuit comprises two MOS transistors, the sources of the MOS transistors are connected to the same first power line, the gates of the MOS transistors are separated by a first resistor, and a second resistor is connected between one end of the first resistor, which is not connected with the drain of the first MOS transistor, and the second power line, so that the current value and the power voltage are related and the starting function is completed.
When the supply voltage is low, both currents in the current pair are small, and the current through the resistor is also small. The gate-to-source voltages of the two MOS transistors are nearly the same, and a larger current will flow through the MOS transistor with a larger width-to-length ratio. When the power supply voltage increases, the current flowing through the resistor between the gates of the MOS transistors increases. Accordingly, the gate-to-source voltage difference of the proportional MOS transistor pair increases. A MOS transistor with a smaller aspect ratio at the rise of the supply voltage will have a larger gate-to-source voltage resulting in a faster current rise rate. At the desired voltage inversion point, a MOS transistor with a smaller aspect ratio flows the same current as a transistor with a larger aspect ratio. When the power supply voltage rises to be higher than the voltage of the turning point, the MOS transistor with smaller width-to-length ratio flows more current, and the current comparison circuit outputs a power-on reset signal.
Accordingly, another feature of the present invention is to compensate for temperature induced supply voltage roll-over point shifts. When the temperature rises, the gate-to-source voltage of the MOS transistor becomes small, which results in a current flowing through the resistor in the current pair becoming large. On the other hand, the positive temperature coefficient of the gate-to-source voltage difference of the proportional MOS transistor pair also increases for the other current of the current pair. Temperature compensation is achieved by setting the ratio of the width to length ratio and the resistance of the MOS transistor.
On the basis of the technical scheme, the following improvement can be made:
as a preferred aspect, the current mirror circuit includes: the first MOS transistor is connected with the third MOS transistor in a mirror image mode, and the fourth MOS transistor is connected with the fifth MOS transistor in a mirror image mode.
By adopting the preferable scheme, the structure is simple.
Preferably, both the first MOS transistor and the second MOS transistor operate in a sub-threshold region.
By adopting the preferable scheme, the working is stable.
Preferably, the power-on reset circuit further comprises an inverter arranged at the output end of the circuit, and the inverter is used for finishing the reversing function and recovering the output signal to the logic level value.
With the above preferred scheme, the inverter restores the output signal to a logic level value.
Preferably, the width-to-length ratio of the first MOS transistor is larger than that of the second MOS transistor.
With the above preferred scheme, a current crossing point is created.
As a preferred solution, the first MOS transistor is a PMOS transistor MP101;
the second MOS transistor is a PMOS transistor MP102;
the third MOS transistor is a PMOS transistor MP103;
the fourth MOS transistor is an NMOS transistor MN101;
the fifth MOS transistor is an NMOS transistor MN102;
the first resistor is a resistor R101;
the second resistor is resistor R102.
The source of the PMOS transistor MP101 is connected to the first power supply line, and the gate and drain thereof are connected to one end of the resistor R101;
the source of the PMOS transistor MP102 is connected to the first power supply line, the gate thereof is connected to the other end of one end of the resistor R101, and the drain thereof is connected to the gate of the NMOS transistor MN101;
the source of the PMOS transistor MP103 is connected to the first power supply line, and the gate thereof is connected to one end of the resistor R101;
one end of the resistor R101 is connected with the drain electrode of the PMOS transistor MP101, and the other end of the resistor R is connected with the gate electrode of the PMOS transistor MP102;
one end of the resistor R102 is connected with the gate of the PMOS transistor MP102, and the other end of the resistor R is connected with the source of the NMOS transistor MN101;
the source of the NMOS transistor MN101 is connected to the second power supply line, and the gate and drain thereof are connected to the drain of the PMOS transistor MP102;
the source of the NMOS transistor MN102 is connected to the second power supply line, and the gate thereof is connected to the drain of the PMOS transistor MP 102.
The drain of the PMOS transistor MP103 is connected to the drain of the NMOS transistor MN103, and to the input terminal of the inverter INV 1.
By adopting the preferable scheme, the structure is simple, and the performance is stable.
As a preferred solution, the first MOS transistor is a PMOS transistor MP201;
the second MOS transistor is a PMOS transistor MP202;
the third MOS transistor is a PMOS transistor MP203;
the fourth MOS transistor is an NMOS transistor MN201;
the fifth MOS transistor is an NMOS transistor MN202;
the first resistor is a resistor R201;
the second resistor is resistor R202.
The source of the PMOS transistor MP201 is connected to the first power line, the drain thereof is connected to one end of the resistor R201, and the gate thereof is connected to the other end of the resistor R201;
the source of the PMOS transistor MP202 is connected to the first power supply line, the gate thereof is connected to one end of the resistor R201, and the drain thereof is connected to the drain of the NMOS transistor MN202;
the source of the PMOS transistor MP203 is connected to the first power supply line, the gate thereof is connected to the gate of the PMOS transistor MP201, and the drain thereof is connected to the drain of the NMOS transistor MN201;
one end of the resistor R201 is connected with the drain electrode of the PMOS transistor MP201, and the other end of the resistor R202 is connected with one end of the resistor;
one end of the resistor R202 is connected with the resistor R201, and the other end of the resistor R is connected to a second power line;
the source of the NMOS transistor MN201 is connected to the second power supply line, and the gate and drain thereof are connected to the drain of the PMOS transistor MP203;
the source of the NMOS transistor MN202 is connected to the second power supply line, the gate thereof is connected to the gate of the NMOS transistor MN201, and the drain thereof is connected to the drain of the PMOS transistor MP202;
an input terminal of the inverter INV2 is connected to the drain of the PMOS transistor MP 202.
By adopting the preferable scheme, the structure is simple, and the performance is stable.
Drawings
Fig. 1 is a schematic diagram of a power-on reset circuit according to an embodiment of the present invention.
Fig. 2 is a graph showing a change curve of current flowing through a first MOS transistor and a second MOS transistor with a supply voltage according to an embodiment of the present invention.
Fig. 3 is a second schematic diagram of a power-on reset circuit according to an embodiment of the present invention.
Fig. 4 is a second curve of the current flowing through the first MOS transistor and the second MOS transistor respectively according to the power supply voltage according to the embodiment of the present invention.
Fig. 5 is a simulation diagram of a variation curve of an input voltage with a process deviation (conn) and a temperature deviation (temp) before shaping according to an embodiment of the present invention.
Fig. 6 is a simulation diagram of a variation curve of the output voltage after shaping according to the embodiment of the present invention along with a process deviation (conn) and a temperature deviation (temp).
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
A power-on reset circuit includes a current generating circuit, a current mirror circuit, and a current comparing circuit.
The current generation circuit includes: the MOS transistor pair and the resistor pair, the current generating circuit is used for generating a current signal. The current mirror circuit is used for processing the generated current signal. The current comparison circuit is used for generating a power-on reset signal.
The MOS transistor pair includes: two proportional first and second MOS transistors. The resistor pair comprises: two proportional first and second resistances. The current mirror circuit includes: the first MOS transistor is connected with the third MOS transistor in a mirror image mode, and the fourth MOS transistor is connected with the fifth MOS transistor in a mirror image mode.
The width-to-length ratio of the first MOS transistor is greater than the width-to-length ratio of the second MOS transistor.
To achieve the objects of the invention, in some embodiments of a power-on reset circuit,
as shown in fig. 1, the first MOS transistor is a PMOS transistor MP101; the second MOS transistor is a PMOS transistor MP102; the third MOS transistor is a PMOS transistor MP103; the fourth MOS transistor is an NMOS transistor MN101; the fifth MOS transistor is an NMOS transistor MN102.
The first resistor is a resistor R101; the second resistor is resistor R102.
The PMOS transistor MP101 has a source connected to the first power line node N106, and a gate and a drain connected to the node N101. The PMOS transistor MP102 has a source connected to the power line node N106, a gate connected to the node N102, and a drain connected to the node N103. The PMOS transistor MP103 has a source connected to the first power line node N106, a gate connected to the node N101, and a drain connected to the node N104. Resistor R101 is connected between node N101 and node N102. Resistor R102 is connected between node N102 and second power line node N107. The NMOS transistor MN101 has a source connected to the second power line node N107, and a gate and a drain connected to the node N103. The NMOS transistor MN102 has a source connected to the second power line node N107, a gate connected to the node N103, and a drain connected to the node N104. Inverter INV1 has an input connected to node N104 and an output connected to node N105.
The function of the circuit shown in fig. 1 is described as follows.
The circuit comprises a PMOS transistor pair (MP 101, MP 102), a resistor pair (R101, R102) and a diode-connected NMOS transistor load (MN 101). The current flowing through PMOS transistor MP101 is mirrored out through current mirrors (MP 101, MP 103). The current flowing through the PMOS transistor MP102 is received by the load MN101 and mirrored out through the current mirrors (MN 101, MN 102).
The drains of PMOS transistor MP103 and NMOS transistor MN102 are tied together to perform a current comparison function.
In other embodiments, the circuit may further include an inverter INV1 to perform an inverting function and restore the output signal to a logic level value.
The implementation method of the invention is as follows:
the PMOS transistor MP101 of one diode connection type, the resistor R101 and the resistor R102 detect the power supply voltage, and generate the first current of the current generating circuit. The gate of PMOS transistor MP102 is connected between resistor R101 and resistor R102, generating a second current that is received by diode-connected NMOS transistor MN 101. Resistor R101 senses the first current signal and creates a voltage difference between the gates of PMOS transistor pair MP101 and MP 102. Accordingly, PMOS transistor MP101 has a larger width to length ratio than PMOS transistor MP102 to create a current cross point. The first current signal flowing through PMOS transistor MP101 is mirrored by PMOS transistor MP 103. The second current signal flowing through PMOS transistor MP102 is received by NMOS load transistor MN101 and mirrored out by transistor MN102. The drain of PMOS transistor MP103 and the drain of NMOS transistor MN102 are connected together, completing the current comparison function at node N104.
Corresponding to the waveforms shown in fig. 2, when the power supply voltage is low, the current flowing through R101 is small, so that the gate-to-source voltages of PMOS transistors MP101 and MP102 are substantially the same. In this case, the PMOS transistor MP101 having a larger width-to-length ratio flows a larger current than the transistor MP 102. As a result, the PMOS transistor MP103 sinks all the current flowing through the NMOS transistor MN102, the node N104 is at the high level, and a logic low level is generated at the node N105 after the inversion by the inverter INV 1.
When the power supply voltage increases, the current flowing through the resistor R101 increases. As a result, the voltage across the resistor R101 increases. Because the drain current of the transistor is a strong function of the gate-to-source voltage, the current through PMOS transistor MP102 increases faster than the current through transistor MP 101.
If the supply voltage continues to rise, PMOS transistor MP102 flows more current than transistor MP 101. As a result, the NMOS transistor MN102 sinks all the current flowing through the PMOS transistor MP103, causing the node N104 to transition from the high level to the low level. Then, the inverter INV1 generates a logic high level at the node N105.
In this operation mode, the PMOS transistors MP101 and MP102 operate in the sub-threshold region. The power supply switching point voltage is given by the following formula:
It=IMP101=IMP102 (1)
It=ΔVgsMP101,MP102/R101 (2)
VTP=VgsMP101+It*(R101+R102) (3)
Id=(W/L)*Is*exp[Vgs/(ζ*Vt)] (4)
ΔVgsMP101,MP102=ζ*Vt*ln[(W/L)MP101/(W/L)MP102] (5)
obtaining a final formula according to formulas (1) - (5):
VTP=VgsMP101+ζ*Vt*1n(n)*(1+R102/R101) (6)
wherein VTP is the power supply turn-over point voltage value;
VgsMp101 is the gate-to-source voltage of PMOS transistor MP101;
Δvgsmp101, MP102 is the difference between VgsMP101 and VgsMP 102;
ζ is a subthreshold ramp coefficient of about 1.68;
vt is the thermal voltage at about 26mV at room temperature;
n is the ratio of the aspect ratios of the PMOS transistors (MP 101 and MP 102), which is specifically: n= [ (W/L) MP 101/(W/L) MP102].
As can be seen from equation (6), the first term to the right of the equation, vgsMP101, has a negative temperature coefficient of about-1 mV/degree Celsius. The second term on the right of the equation, vt, has a positive temperature coefficient of approximately +0.087 mV/degree Celsius.
To achieve first order temperature coefficient compensation of the VTP, the ratio of the resistance ratio to the transistor width to length ratio is:
Ln(n)*(1+R102/R101)=6.48
for example: n=8, r102/r101=2.
When r101=1000 kΩ, the current is approximately 100nA.
This example shows a rough estimate where the exact ratio can be fine tuned to achieve the first order temperature coefficient compensation effect of the roll-over point voltage under different manufacturing processes.
To further optimize the effect of the present invention, in other embodiments, the remaining feature techniques are the same, except,
as shown in fig. 3, the first MOS transistor is a PMOS transistor MP201; the second MOS transistor is a PMOS transistor MP202; the third MOS transistor is a PMOS transistor MP203; the fourth MOS transistor is an NMOS transistor MN201; the fifth MOS transistor is an NMOS transistor MN202.
The first resistor is a resistor R201; the second resistor is resistor R202.
As shown in fig. 3, the PMOS transistor MP201 has a source connected to the first power line node N206, a gate connected to the node N201, and a drain connected to the node N202.PMOS transistor MP202 has a source connected to power line node N206, a gate connected to node N202, and a drain connected to node N204. The PMOS transistor MP203 has a source connected to the first power line node N206, a gate connected to the node N201, and a drain connected to the node N203. Resistor R201 is connected between node N202 and node N201. Resistor R202 is connected between node N201 and second power line node N207. The NMOS transistor MN201 has a source connected to the second power line node N207, and a gate and a drain connected to the node N203. The NMOS transistor MN202 has a source connected to the second power line node N207, a gate connected to the node N203, and a drain connected to the node N204. Inverter INV2 has an input connected to node N204 and an output connected to node N205.
Similar to the previous embodiment, the circuit functions shown in fig. 3 are described as follows:
the circuit comprises a PMOS transistor pair (MP 201, MP 202) and a resistor pair (R201, R202). The current flowing through the PMOS transistor MP201 is mirrored by the PMOS current mirrors (MP 201, MP 203) and received by the NMOS transistor MN201, and is mirrored by the NMOS current mirrors (MN 201, MN 202) to be outputted.
PMOS transistor MP202 and NMOS transistor MN202 perform a current comparison function at node N204. The circuit may further include an inverter INV2 to perform an inverting function and restore the output signal to a logic level value.
As shown in fig. 4, when the power supply voltage is low, the current flowing through the resistor R201 is small, and the gate voltage difference of the PMOS transistors MP201 and MP202 is small. The aspect ratio of the PMOS transistor MP202 is set to be larger than that of MP201 to ensure that MP202 has a larger current supply capability when the power supply voltage is relatively low. Since the NMOS transistor MN202 holds the current signal of the PMOS transistor MP201 through the PMOS current mirror (MP 201, MP 203) and the NMOS current mirror (MN 201, MN 202), after the current comparison, the PMOS transistor MP202 flows all the currents supplied by the NMOS transistor MN202. The voltage value of node N204 is pulled high. The inverter INV2 outputs a logic low level. When the power supply voltage increases, the current flowing through the resistor R201 increases, resulting in a lower gate-to-source voltage of the PMOS transistor MP202 than the gate-to-source voltage of the MP 201. As a result, the current supply capability of the PMOS transistor MP202 becomes weaker. If the supply voltage continues to rise, the PMOS transistor MP202 will not be able to supply enough current to the NMOS transistor MN202. As a result, node N204 switches to a low level at a certain supply voltage level. The inverter INV2 outputs a logic high level.
Fig. 5 is a graph showing a voltage curve of the node N104 or the node N204 according to a process deviation (con) and a temperature deviation (temp) before passing through the inverter INV1 or INV 2.
Fig. 6 is a graph showing a voltage curve of the node N105 or the node N205 according to a process deviation (con) and a temperature deviation (temp) after passing through the inverter INV1 or INV 2.
According to the above description and the simulation graphs shown in fig. 5 to 6, the following advantageous effects of the present invention can be obtained:
1) One feature of the present invention is: a current switching point associated with the supply voltage is generated. The current generating circuit comprises two MOS transistors, the sources of the MOS transistors are connected to the same first power line, the gates of the MOS transistors are separated by a first resistor, and a second resistor is connected between one end of the first resistor, which is not connected with the drain of the first MOS transistor, and the second power line, so that the current value and the power voltage are related and the starting function is completed.
When the supply voltage is low, both currents in the current pair are small, and the current through the resistor is also small. The gate-to-source voltages of the two MOS transistors are nearly the same, and a larger current will flow through the MOS transistor with a larger width-to-length ratio. When the power supply voltage increases, the current flowing through the resistor between the gates of the MOS transistors increases. Accordingly, the gate-to-source voltage difference of the proportional MOS transistor pair increases. A MOS transistor with a smaller aspect ratio at the rise of the supply voltage will have a larger gate-to-source voltage resulting in a faster current rise rate. At the desired voltage inversion point, a MOS transistor with a smaller aspect ratio flows the same current as a transistor with a larger aspect ratio. When the power supply voltage rises to be higher than the voltage of the turning point, the MOS transistor with smaller width-to-length ratio flows more current, and the current comparison circuit outputs a power-on reset signal.
2) Another feature of the present invention is to compensate for temperature induced supply voltage roll-over point shifts. When the temperature rises, the gate-to-source voltage of the MOS transistor becomes small, which results in a current flowing through the resistor in the current pair becoming large. On the other hand, the positive temperature coefficient of the gate-to-source voltage difference of the proportional MOS transistor pair also increases for the other current of the current pair. Temperature compensation is achieved by setting the ratio of the width to length ratio and the resistance of the MOS transistor.
3) The invention adopts a topological structure, so that the output power-on reset signal has compensation characteristic along with the change of the ambient temperature, and the power supply voltage turning point is only related to the single type of active device ratio and the resistance device ratio, thereby greatly reducing the problem of power supply voltage turning point deviation caused by discrete factors of devices and the ambient temperature change factors in the actual working process in the mass production process. The invention relates to a device proportion relation in a circuit, which is used for setting a temperature coefficient, and the absolute value of a device can be greatly deviated in mass production.
4) The invention has the characteristics of reliable performance and low power consumption because of simple topological structure.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and improvements could be made by those skilled in the art without departing from the inventive concept, which fall within the scope of the present invention.

Claims (7)

1. A power-on reset circuit, comprising:
a current generation circuit comprising: a MOS transistor pair and a resistor pair, wherein the current generating circuit is used for generating a current signal;
the MOS transistor pair includes: the first MOS transistor and the second MOS transistor are in proportion, the sources of the first MOS transistor and the second MOS transistor are connected to the first power line together, the grid electrode of the first MOS transistor is connected with the grid electrode of the second MOS transistor through one end of the first resistor, and the drain electrode of the first MOS transistor is connected with one end of the first resistor;
the first MOS transistor and the second MOS transistor work in a subthreshold region, and the width-to-length ratio of the first MOS transistor is larger than that of the second MOS transistor;
the resistor pair comprises: the first resistor is connected between the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor, and the second resistor is connected between one end of the first resistor which is not connected with the drain electrode of the first MOS transistor and the second power line;
when the power supply voltage is low, both currents in the current pair are small, and the current flowing through the resistor is also small; the grid electrode to source electrode voltages of the two MOS transistors are the same, and a larger current flows through the MOS transistors with a large width-to-length ratio; when the supply voltage increases, the current flowing through the resistor between the gates of the MOS transistors increases, and correspondingly, the gate-to-source voltage difference of the proportional MOS transistor pair increases;
when the power supply voltage rises, the MOS transistor with smaller width-to-length ratio has larger gate-to-source voltage, so that the current increasing speed is faster;
at the desired voltage inversion point, the MOS transistor with smaller width-to-length ratio and the transistor with larger width-to-length ratio flow the same current, when the power supply voltage rises to be higher than the inversion point voltage, the MOS transistor with smaller width-to-length ratio flows more current, and the current comparison circuit outputs and generates a power-on reset signal;
a current mirror circuit for processing a generated current signal, the current mirror circuit comprising: the MOS device comprises a first MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor, wherein the first MOS transistor is in mirror image connection with the third MOS transistor, and the fourth MOS transistor is in mirror image connection with the fifth MOS transistor;
and the current comparison circuit is used for generating a power-on reset signal.
2. The power-on reset circuit of claim 1, further comprising an inverter disposed at an output of the circuit, the inverter configured to perform a reverse function to restore the output signal to a logic level value.
3. A power-on reset circuit according to claim 1 or 2, wherein,
the first MOS transistor is a PMOS transistor MP101;
the second MOS transistor is a PMOS transistor MP102;
the third MOS transistor is a PMOS transistor MP103;
the fourth MOS transistor is an NMOS transistor MN101;
the fifth MOS transistor is an NMOS transistor MN102;
the first resistor is a resistor R101;
the second resistor is resistor R102.
4. A power-on reset circuit according to claim 3, wherein the PMOS transistor MP101 has a source connected to the first power supply line and a gate and a drain connected to one end of the resistor R101;
the source of the PMOS transistor MP102 is connected to the first power supply line, the gate thereof is connected to the other end of one end of the resistor R101, and the drain thereof is connected to the gate of the NMOS transistor MN101;
the source of the PMOS transistor MP103 is connected to the first power supply line, and the gate thereof is connected to one end of the resistor R101;
one end of the resistor R101 is connected with the drain electrode of the PMOS transistor MP101, and the other end of the resistor R is connected with the gate electrode of the PMOS transistor MP102;
one end of the resistor R102 is connected with the gate of the PMOS transistor MP102, and the other end of the resistor R is connected with the source of the NMOS transistor MN101;
the source of the NMOS transistor MN101 is connected to the second power supply line, and the gate and drain thereof are connected to the drain of the PMOS transistor MP102;
the source of the NMOS transistor MN102 is connected to the second power supply line, and the gate thereof is connected to the drain of the PMOS transistor MP 102.
5. The power-on reset circuit according to claim 4, wherein a drain of the PMOS transistor MP103 is connected to a drain of the NMOS transistor MN103 and to an input terminal of the inverter INV 1.
6. A power-on reset circuit according to claim 1 or 2, wherein,
the first MOS transistor is a PMOS transistor MP201;
the second MOS transistor is a PMOS transistor MP202;
the third MOS transistor is a PMOS transistor MP203;
the fourth MOS transistor is an NMOS transistor MN201;
the fifth MOS transistor is an NMOS transistor MN202;
the first resistor is a resistor R201;
the second resistor is resistor R202.
7. The power-on reset circuit of claim 6, wherein,
the source of the PMOS transistor MP201 is connected to the first power line, the drain thereof is connected to one end of the resistor R201, and the gate thereof is connected to the other end of the resistor R201;
the source of the PMOS transistor MP202 is connected to the first power supply line, the gate thereof is connected to one end of the resistor R201, and the drain thereof is connected to the drain of the NMOS transistor MN202;
the source of the PMOS transistor MP203 is connected to the first power supply line, the gate thereof is connected to the gate of the PMOS transistor MP201, and the drain thereof is connected to the drain of the NMOS transistor MN201;
one end of the resistor R201 is connected with the drain electrode of the PMOS transistor MP201, and the other end of the resistor R202 is connected with one end of the resistor;
one end of the resistor R202 is connected with the resistor R201, and the other end of the resistor R is connected to a second power line;
the source of the NMOS transistor MN201 is connected to the second power supply line, and the gate and drain thereof are connected to the drain of the PMOS transistor MP203;
the source of the NMOS transistor MN202 is connected to the second power supply line, the gate thereof is connected to the gate of the NMOS transistor MN201, and the drain thereof is connected to the drain of the PMOS transistor MP202;
an input terminal of the inverter INV2 is connected to the drain of the PMOS transistor MP 202.
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JP7251929B2 (en) * 2018-06-21 2023-04-04 ラピスセミコンダクタ株式会社 Semiconductor device and power-on reset signal generation method
CN112838850B (en) * 2020-12-30 2024-09-10 合肥市芯海电子科技有限公司 Power-on reset circuit, integrated circuit and electronic equipment

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CN106972846A (en) * 2017-03-21 2017-07-21 上海华力微电子有限公司 A kind of electrification reset circuit
CN207819874U (en) * 2017-12-27 2018-09-04 苏州菲达旭微电子有限公司 Electrification reset circuit

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CN102768827A (en) * 2011-05-03 2012-11-07 硅工厂股份有限公司 Liquid crystal panel driving circuit for display stabilization
CN102832915A (en) * 2012-08-23 2012-12-19 中国科学院微电子研究所 Programmable power-on reset system
CN104601150A (en) * 2013-10-30 2015-05-06 国民技术股份有限公司 Power-on reset circuit
CN205377819U (en) * 2015-10-10 2016-07-06 意法半导体研发(深圳)有限公司 Electrify restoration circuit
CN205540381U (en) * 2016-02-02 2016-08-31 厦门新页微电子技术有限公司 Accurate excess temperature protection circuit of current feedback formula
CN106027006A (en) * 2016-05-18 2016-10-12 上海华虹宏力半导体制造有限公司 Power-on reset circuit
CN106972846A (en) * 2017-03-21 2017-07-21 上海华力微电子有限公司 A kind of electrification reset circuit
CN207819874U (en) * 2017-12-27 2018-09-04 苏州菲达旭微电子有限公司 Electrification reset circuit

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