CN105406827A

CN105406827A - Low-offset operational amplifier

Info

Publication number: CN105406827A
Application number: CN201510857486.5A
Authority: CN
Inventors: 王硕; 唐涛; 石广; 刘海林
Original assignee: Inspur Beijing Electronic Information Industry Co Ltd
Current assignee: Inspur Beijing Electronic Information Industry Co Ltd
Priority date: 2015-11-30
Filing date: 2015-11-30
Publication date: 2016-03-16

Abstract

The invention discloses a low-offset operational amplifier. The low-offset operational amplifier comprises a first-stage differential amplification circuit, a symmetrical differential amplification circuit, a symmetrical signal generation circuit and a second-stage symmetrical output amplification circuit, wherein the output end of the first-stage differential amplification circuit is connected with the first input end of the symmetrical differential amplification circuit; the second input end of the symmetrical differential amplification circuit is connected with the output end of the symmetrical signal generation circuit; and the output end of the symmetrical differential amplification circuit is connected with the second-stage symmetrical output amplification circuit. According to the low-offset operational amplifier provided by the invention, the symmetrical differential amplification circuit symmetrical to the first-stage differential amplification circuit is introduced at the rear of the first-stage differential amplification circuit of the low-offset operational amplifier; therefore, on the premise that enough gain of the first-stage differential amplification circuit is ensured, offset voltage due to asymmetry of the first-stage differential amplification circuit is eliminated through the symmetrical differential amplification circuit symmetrical to the first-stage differential amplification circuit; and thus, the low-offset operational amplifier has relatively high gain while offset voltage is eliminated.

Description

A kind of low imbalance operational amplifier

Technical field

The present invention relates to operational amplifier techniques field, particularly relate to a kind of low imbalance operational amplifier.

Background technology

A desirable operational amplifier, when input voltage is 0, output voltage also should be 0.But in fact in prior art, its differential input stage is difficult to accomplish full symmetric, usually when input voltage is 0, there is certain output voltage, usually this output voltage is called offset voltage.The offset voltage of operational amplifier weighs the very important parameter of of amplifier performance, and excessive offset voltage can increase in proportion when amplifier amplifying signal, and this will have a strong impact on the precision of operational amplifier.Offset voltage produces primarily of technique and Circuits System two aspect.Circuits System can cause imbalance due to the reason of some circuit structures, traditional suppressing method is symmetric difference amplifying circuit one-level differential amplifier circuit being replaced with full symmetric, the advantage of this method effectively can reduce imbalance, but the gain that shortcoming is operational amplifier diminishes.

Therefore, a kind of existing larger gain amplifier how is provided can effectively to suppress again the low imbalance operational amplifier of offset voltage to be the problem that those skilled in the art need to solve at present.

Summary of the invention

The object of this invention is to provide a kind of low imbalance operational amplifier, at the symmetric difference amplifying circuit introducing symmetry with it below of the one-level differential amplifier circuit of low imbalance operational amplifier.Such one-level differential amplifier circuit is ensureing under enough gains, eliminate by the symmetric difference amplifying circuit of symmetric design with it the offset voltage that the asymmetry due to one-level differential amplifier circuit causes, thus make low imbalance operational amplifier not only reach larger gain but also offset voltage has carried out effectively suppressing.

For solving the problems of the technologies described above, the invention provides a kind of low imbalance operational amplifier, comprising one-level differential amplifier circuit, symmetric difference amplifying circuit, symmetric signal generation circuit and the symmetrical output amplifier of secondary, wherein:

The output of described one-level differential amplifier circuit is connected with the first input end of described symmetric difference amplifying circuit, and described one-level differential amplifier circuit is used for amplifying voltage by obtaining one-level after input signal amplification and exporting described first input end to;

The output that second input and the described symmetric signal of described symmetric difference amplifying circuit produce circuit is connected; Wherein, described symmetric signal produces circuit for generating identical, the equal-sized symmetrical voltage of offset voltage polarity produced with described one-level differential amplifier circuit, and exports described symmetrical voltage to described second input;

The output of described symmetric difference amplifying circuit is connected with the symmetrical output amplifier of described secondary, the input signal that described symmetric difference amplifying circuit is used for amplifying described one-level voltage and described symmetrical voltage composition carries out symmetric difference amplification, obtain symmetric difference amplify voltage and export the symmetrical output amplifier of described secondary to, the symmetrical output amplifier of described secondary exports amplifying signal after being used for amplifying voltage amplification to described symmetric difference.

Preferably, described one-level differential amplifier circuit specifically comprises a PMOS, the 2nd PMOS, the 3rd PMOS and active pull-up circuit, wherein:

The source electrode of described 3rd PMOS is connected with power supply, grid and the bias voltage pole of described 3rd PMOS connect, the drain electrode of described 3rd PMOS is connected with the source electrode of a described PMOS and described 2nd PMOS respectively, the grid of a described PMOS connects the negative pole of described input signal, the drain electrode of a described PMOS is connected with the first end of described active pull-up circuit, the grid of described 2nd PMOS connects the positive pole of described input signal, the drain electrode of described 2nd PMOS is as the output of described one-level differential amplifier circuit, be connected with the second end of described active pull-up circuit, 3rd end ground connection of described active pull-up circuit.

Preferably, described first active pull-up circuit specifically comprises a NMOS and the 2nd NMOS, wherein:

The drain electrode of a described NMOS is as the first end of described active pull-up circuit, the grid of a described NMOS is connected with the grid of its drain electrode and described 2nd NMOS respectively, the source ground of a described NMOS, the drain electrode of described 2nd NMOS as the second end of described active pull-up circuit, the source ground of described 2nd NMOS.

Preferably, described symmetric difference amplifying circuit specifically comprises the 4th PMOS, the 5th PMOS, the 6th PMOS, the 3rd NMOS and the 4th NMOS, wherein:

The source electrode of described 6th PMOS is connected with described power supply, the grid of described 6th PMOS is connected with described bias voltage, the drain electrode of described 6th PMOS is connected with the source electrode of described 4th PMOS and the source electrode of described 5th PMOS respectively, the grid of described 4th PMOS is as described first input end, be connected with the output of described one-level differential amplifier circuit, the drain electrode of described 4th PMOS is connected with the drain electrode of described 3rd NMOS, the grid of described 5th PMOS is as the second input of described symmetric difference amplifying circuit, the output producing circuit with described symmetric signal is connected, the drain electrode of described 5th PMOS is connected with the drain electrode of described 4th NMOS, the grid of described 3rd NMOS is connected with the first input end of its drain electrode and the symmetrical output amplifier of described secondary respectively, the source ground of described 3rd NMOS, the grid of described 4th NMOS is connected with the second input of its drain electrode and the symmetrical output amplifier of described secondary respectively, the source ground of described 4th NMOS.

Preferably, described symmetric signal produces circuit and specifically comprises the 7th PMOS, the 8th PMOS and the 5th NMOS, wherein:

The source electrode of described 7th PMOS is connected with described power supply, the grid of described 7th PMOS is connected with described bias voltage, the drain electrode of described 7th PMOS is connected with the source electrode of described 8th PMOS, the grid of described 8th PMOS produces the input of circuit as described symmetric signal, be connected with zeroing voltage, the drain electrode of described 8th PMOS produces the output of circuit as described symmetric signal, be connected with the second input of described symmetric difference amplifying circuit and the drain electrode of described 5th NMOS respectively, the grid of described 5th NMOS is connected with its drain electrode, the source ground of described 5th NMOS, wherein, the breadth length ratio of described 7th PMOS is 1/2 of the breadth length ratio of described 3rd PMOS, the breadth length ratio of a described PMOS equals the breadth length ratio of described 8th PMOS, the breadth length ratio of a described NMOS equals the breadth length ratio of described 5th NMOS.

Preferably, the symmetrical output amplifier of described secondary specifically comprises the 9th PMOS, the tenth PMOS, the 6th NMOS and the 7th NMOS, wherein:

The source electrode of described 9th PMOS is connected with described power supply, the grid of described 9th PMOS is connected with the grid of its drain electrode and described tenth PMOS respectively, the drain electrode of described 9th PMOS is connected with the drain electrode of described 6th NMOS, the grid of described 6th NMOS is as the first input end of the symmetrical output amplifier of described secondary, the source ground of described 6th NMOS, the source electrode of described tenth PMOS is connected with described power supply, the drain electrode of described tenth PMOS is as the output of the symmetrical output amplifier of described secondary, be connected with the drain electrode of described 7th NMOS, the grid of described 7th NMOS is as the second input of the symmetrical output amplifier of described secondary, the source ground of described 7th NMOS.

The low imbalance operational amplifier of one provided by the invention, at the symmetric difference amplifying circuit introducing symmetry with it below of the one-level differential amplifier circuit of low imbalance operational amplifier.Such one-level differential amplifier circuit is ensureing under enough gains, eliminate by the symmetric difference amplifying circuit of symmetric design with it the offset voltage that the asymmetry due to one-level differential amplifier circuit causes, thus make low imbalance operational amplifier not only reach larger gain but also offset voltage has carried out effectively suppressing.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in prior art and embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the structural representation of a kind of low imbalance operational amplifier provided by the invention;

Fig. 2 is the structural representation of the low imbalance operational amplifier of another kind provided by the invention;

Wherein, in Fig. 2, P1-the one PMOS, P2 the-the 2nd PMOS, P3-the 3rd PMOS, P4 the-the 4th PMOS, P5 the-the 5th PMOS, P6-the 6th PMOS, P7 the-the 7th PMOS, P8 the-the 8th PMOS, P9-the 9th PMOS, P10 the-the tenth PMOS, N1 the-the one NMOS, N2-the 2nd NMOS, N3 the-the 3rd NMOS, N4 the-the 4th NMOS, N5-the 5th NMOS, N6 the-the 6th NMOS, N7 the-the 7th NMOS.

Embodiment

Core of the present invention is to provide a kind of low imbalance operational amplifier, at the symmetric difference amplifying circuit introducing symmetry with it below of the one-level differential amplifier circuit of low imbalance operational amplifier.Such one-level differential amplifier circuit is ensureing under enough gains, eliminate by the symmetric difference amplifying circuit of symmetric design with it the offset voltage that the asymmetry due to one-level differential amplifier circuit causes, thus make low imbalance operational amplifier not only reach larger gain but also offset voltage has carried out effectively suppressing.

For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Embodiment one

Please refer to Fig. 1, Fig. 1 is the structural representation of a kind of low imbalance operational amplifier provided by the invention, and this low imbalance operational amplifier comprises:

One-level differential amplifier circuit 1, symmetric difference amplifying circuit 3, symmetric signal produce circuit 2 and the symmetrical output amplifier 4 of secondary, wherein:

The output of one-level differential amplifier circuit 1 is connected with the first input end of symmetric difference amplifying circuit 3, and one-level differential amplifier circuit 1 is for amplifying voltage by obtaining one-level after input signal amplification and export first input end to;

The output that second input and the symmetric signal of symmetric difference amplifying circuit 3 produce circuit 2 is connected; Wherein, symmetric signal produces circuit 2 for generating identical, the equal-sized symmetrical voltage of offset voltage polarity produced with one-level differential amplifier circuit 1, and exports symmetrical voltage to second input;

Be understandable that, " symmetry " of symmetric difference amplifying circuit 3 here has two layers of meaning, and one deck is the structure full symmetric of symmetric difference amplifying circuit 3 itself, and another layer of implication is that symmetric difference amplifying circuit 3 forms symmetry with one-level differential amplifier circuit 1.

Due to the dissymmetrical structure of one-level differential amplifier circuit 1, the one-level that one-level differential amplifier circuit 1 exports is amplified in voltage can comprise offset voltage, in order to offset voltage is eliminated, symmetric signal produces circuit 2 can generate identical with offset voltage polarity, an equal-sized symmetrical voltage, then this symmetrical voltage and one-level amplify two input signals of voltage as symmetric difference amplifying circuit 3, and the voltage that final symmetric difference amplifying circuit 3 exports can be offset voltage has been eliminated later voltage.

The output of symmetric difference amplifying circuit 3 is connected with the symmetrical output amplifier 4 of secondary, symmetric difference amplifying circuit 3 carries out symmetric difference amplification for input signal one-level being amplified to voltage and symmetrical voltage composition, obtain symmetric difference amplify voltage and export the symmetrical output amplifier 4 of secondary to, the symmetrical output amplifier 4 of secondary exports amplifying signal after amplifying voltage amplification to symmetric difference.

Be understandable that, because the existence of symmetric difference amplifying circuit 3, in order to not introduce new offset voltage, the symmetrical output amplifier 4 of secondary here is also symmetrical structure.

Embodiment two

Please refer to Fig. 2, Fig. 2 is the structural representation of the low imbalance operational amplifier of another kind provided by the invention, and this low imbalance operational amplifier is on the basis of embodiment one:

As preferably, one-level differential amplifier circuit 1 specifically comprises a PMOS, the 2nd PMOS, the 3rd PMOS and active pull-up circuit, wherein:

The source electrode of the 3rd PMOS is connected with power supply, grid and the bias voltage pole of the 3rd PMOS connect, the drain electrode of the 3rd PMOS is connected with the source electrode of a PMOS and the 2nd PMOS respectively, the grid of the one PMOS connects the negative pole of input signal, the drain electrode of the one PMOS is connected with the first end of active pull-up circuit, the grid of the 2nd PMOS connects the positive pole of input signal, the drain electrode of the 2nd PMOS is as the output of one-level differential amplifier circuit 1, be connected with the second end of active pull-up circuit, the 3rd end ground connection of active pull-up circuit.

As preferably, the first active pull-up circuit specifically comprises a NMOS and the 2nd NMOS, wherein:

The drain electrode of the one NMOS is as the first end of active pull-up circuit, the grid of the one NMOS is connected with the grid of its drain electrode and the 2nd NMOS respectively, the source ground of the one NMOS, the drain electrode of the 2nd NMOS as the second end of active pull-up circuit, the source ground of the 2nd NMOS.

Be understandable that, a PMOS and the 2nd PMOS forms differential amplification structure, and the 3rd PMOS is as current source for this one-level differential amplifier circuit 1 provides operating current, and a NMOS and the 2nd NMOS forms active pull-up circuit.

When circuit normally works, the input of differential amplification structure is loaded into small-signal, first or the 2nd PMOS source and drain on can produce one change electric current Δ I, the resistance of the active pull-up circuit formed due to a NMOS and the 2nd NMOS is very large, therefore the output of one-level differential amplifier circuit 1 has larger change in voltage, serves the effect of amplifying signal.According to the calculating Av=-gm2 (ro1//ro2) of gain (wherein, gm2 is the mutual conductance of the 2nd PMOS, ro1, ro2 are respectively the source and drain resistance of the 2nd PMOS and the second NMOS tube) can find out, the gain of one-level differential amplifier circuit 1 can reach very large.But this structure is due to the connection of first and second NMOS tube and Non-completety symmetry, cause when input signal is 0, what output signal can not be desirable is also 0, but has a voltage and exist, i.e. offset voltage.

As preferably, symmetric difference amplifying circuit 3 specifically comprises the 4th PMOS, the 5th PMOS, the 6th PMOS, the 3rd NMOS and the 4th NMOS, wherein:

The source electrode of the 6th PMOS is connected with power supply, the grid of the 6th PMOS is connected with bias voltage, the drain electrode of the 6th PMOS is connected with the source electrode of the 4th PMOS and the source electrode of the 5th PMOS respectively, the grid of the 4th PMOS is as first input end, be connected with the output of one-level differential amplifier circuit 1, the drain electrode of the 4th PMOS is connected with the drain electrode of the 3rd NMOS, the grid of the 5th PMOS is as the second input of symmetric difference amplifying circuit 3, the output producing circuit 2 with symmetric signal is connected, the drain electrode of the 5th PMOS is connected with the drain electrode of the 4th NMOS, the grid of the 3rd NMOS is connected with the first input end of its drain electrode and the symmetrical output amplifier 4 of secondary respectively, the source ground of the 3rd NMOS, the grid of the 4th NMOS is connected with the second input of its drain electrode and the symmetrical output amplifier 4 of secondary respectively, the source ground of the 4th NMOS.

Be understandable that, the 3rd NMOS here and the 4th NMOS adopts " diode " connection to form support structures, and the 6th PMOS is as current source.

The symmetric difference amplifying circuit 3 can finding out this one-level is full symmetrics, and such structure effectively can suppress the generation of offset voltage.According to the calculating Av '=-gm1* (1/gm2) of gain (wherein, gm1, gm2 are respectively the mutual conductance of the 5th PMOS and the 4th NMOS tube) can find out, the gain comparing this grade of one-level differential amplifier circuit 1 obviously reduces, but can obtain larger gain from one-level differential amplifier circuit 1, the object of symmetric difference amplifying circuit 3 mainly eliminates the impact of offset voltage.The grid of the 5th PMOS accesses the signal symmetrical with the grid of the 4th PMOS, and the grid input signal of the 5th PMOS produces circuit 2 by symmetric signal and produces.

As preferably, symmetric signal produces circuit 2 and specifically comprises the 7th PMOS, the 8th PMOS and the 5th NMOS, wherein:

The source electrode of the 7th PMOS is connected with power supply, the grid of the 7th PMOS is connected with bias voltage, the drain electrode of the 7th PMOS is connected with the source electrode of the 8th PMOS, the grid of the 8th PMOS produces the input of circuit 2 as symmetric signal, be connected with zeroing voltage, the drain electrode of the 8th PMOS produces the output of circuit 2 as symmetric signal, be connected with the second input of symmetric difference amplifying circuit 3 and the drain electrode of the 5th NMOS respectively, the grid of the 5th NMOS is connected with its drain electrode, the source ground of the 5th NMOS, wherein, the breadth length ratio of the 7th PMOS is 1/2 of the breadth length ratio of the 3rd PMOS, the breadth length ratio of the one PMOS equals the breadth length ratio of the 8th PMOS, the breadth length ratio of the one NMOS equals the breadth length ratio of the 5th NMOS.

Can find out, the circuit structure that symmetric signal produces the circuit structure of circuit 2 and left one side of something of one-level differential amplifier circuit 1 is symmetrical, and the breadth length ratio of the 7th PMOS is 1/2 of the breadth length ratio of the 3rd PMOS, the breadth length ratio of the one PMOS equals the breadth length ratio of the 8th PMOS, and the breadth length ratio of a NMOS equals the breadth length ratio of the 5th NMOS.8th PMOS is amplifier tube, and the 5th NMOS tube is load, and the 7th PMOS is current source.The grid of the 8th PMOS produces the input of circuit 2 as symmetric signal, be connected with zeroing voltage, generate symmetrical voltage as required, make the input signal of the 5th PMOS and offset voltage symmetry (symmetry here refers to that polarity is identical, size is identical) in the input signal of the 4th PMOS, because symmetric signal produces the feature of circuit 2 full symmetric, can by asymmetric due to one-level differential amplifier circuit 1 and offset voltage that is that cause is eliminated.

As preferably, the symmetrical output amplifier 4 of secondary specifically comprises the 9th PMOS, the tenth PMOS, the 6th NMOS and the 7th NMOS, wherein:

The source electrode of the 9th PMOS is connected with power supply, the grid of the 9th PMOS is connected with the grid of its drain electrode and the tenth PMOS respectively, the drain electrode of the 9th PMOS is connected with the drain electrode of the 6th NMOS, the grid of the 6th NMOS is as the first input end of the symmetrical output amplifier 4 of secondary, the source ground of the 6th NMOS, the source electrode of the tenth PMOS is connected with power supply, the drain electrode of the tenth PMOS is as the output of the symmetrical output amplifier 4 of secondary, be connected with the drain electrode of the 7th NMOS, the grid of the 7th NMOS is as the second input of the symmetrical output amplifier 4 of secondary, the source ground of the 7th NMOS.

The symmetrical output amplifier 4 of secondary is the output stage of low imbalance operational amplifier, adopt simple common source amplification circuit structure, the left-half of the symmetrical output amplifier 4 of secondary is identical with right half part, and object realizes the full symmetric of symmetrical output amplifier 4 structure of secondary.7th NOMS is amplifier tube, and the tenth PMOS is current source, and the drain electrode of the 7th NMOS is connected with the drain electrode of the tenth PMOS and as output.

Low imbalance operational amplifier provided by the invention effectively can suppress the imbalance brought due to circuit structure problem, the offset influence brought by technological reason cannot be avoided, but total imbalance is made up of these two parts, therefore the offset voltage of low imbalance operational amplifier can be effectively suppressed.

The low imbalance operational amplifier of one provided by the invention, at the symmetric difference amplifying circuit introducing symmetry with it below of the one-level differential amplifier circuit of low imbalance operational amplifier.One-level differential amplifier circuit can provide very large gain, and symmetric difference amplifying circuit, owing to adopting the circuit structure design of full symmetric, effectively inhibits the offset voltage phenomenon that operational amplifier exports, improves the precision of operational amplifier.

In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.

Also it should be noted that, in this manual, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.

To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims

1. a low imbalance operational amplifier, is characterized in that, comprises one-level differential amplifier circuit, symmetric difference amplifying circuit, symmetric signal generation circuit and the symmetrical output amplifier of secondary, wherein:

2. low imbalance operational amplifier as claimed in claim 1, is characterized in that, described one-level differential amplifier circuit specifically comprises a PMOS, the 2nd PMOS, the 3rd PMOS and active pull-up circuit, wherein:

3. low imbalance operational amplifier as claimed in claim 2, is characterized in that, described first active pull-up circuit specifically comprises a NMOS and the 2nd NMOS, wherein:

4. low imbalance operational amplifier as claimed in claim 3, is characterized in that, described symmetric difference amplifying circuit specifically comprises the 4th PMOS, the 5th PMOS, the 6th PMOS, the 3rd NMOS and the 4th NMOS, wherein:

5. low imbalance operational amplifier as claimed in claim 4, is characterized in that, described symmetric signal produces circuit and specifically comprises the 7th PMOS, the 8th PMOS and the 5th NMOS, wherein:

6. low imbalance operational amplifier as claimed in claim 5, is characterized in that, the symmetrical output amplifier of described secondary specifically comprises the 9th PMOS, the tenth PMOS, the 6th NMOS and the 7th NMOS, wherein: