CN102130053B - Method for making integrated amplifier of N-channel junction field effect transistor (JFET) - Google Patents

Abstract

The invention relates to a method for making an integrated amplifier of an N-channel JEFT junction field effect transistor (JEFT). The method comprises the steps of making single P+ isolation areas on a Si wafer and making grid electrodes, source electrodes and drain electrodes in the P+ isolation areas and is characterized in that more than two independent P+ isolation areas are made on the Si wafer, an N+ isolation area is made on the periphery of each P+ isolation area, and the grid electrode, the source electrode and the drain electrode are made in each P+ isolation area. In the invention, an integrated N-channel JEFT design is adopted; and by a double-isolation technology of making the N+ isolation areas and the P+ isolation areas, the method has the advantages that: (1) circuit leakage is thoroughly eliminated and mutual interference among all independent working units are removed by adopting the double-isolation technology; (2) integration of the amplifier of the N-channel JEFT is realized; and (3) space occupied by an integrated circuit is reduced, the temperature performance of the circuit is ensured to a greater extent, the noise is reduced, the limit frequency is improved, lower power consumption is ensured, the anti-irradiation capability is strengthened, and the integrated amplifier serving as an integrated operational amplifier of an input electrode has higher speed, wider bandwidth and higher input impedance.

Description

A kind of manufacture method of N raceway groove JFET integrated amplifier

Technical field

The invention belongs to semiconductor process techniques field, relate to a kind of N ditch JFET integrated amplifier manufacturing process technology for the preposition amplification of low noise.

Background technology

N raceway groove JFET pipe is a kind of field effect transistor that the utmost point is comprised of pn of controlling, and work depends on unique a kind of charge carrier---the motion in electronics or hole.This device is because its good performance is in industrial quarters extensive use.Yet the N raceway groove JFET pipe that at present industry is used is all discrete device, adopting the amplifier that a plurality of discrete devices form is very difficult controlling noise and reducing in power consumption, it not only affect allomeric function and also the space that takies larger.Through retrieval, not yet find that there is the report of integrated N raceway groove JFET pipe.

Summary of the invention

Object of the present invention is just to provide a kind of manufacture method of N ditch JFET integrated amplifier.

To achieve these goals, the present invention has adopted following technical scheme:

A kind of manufacture method of N raceway groove JFET integrated amplifier, comprise: on Si sheet, make the single step with P+ isolated area, and the step of making grid, source, drain electrode in this P+ isolated area, it is characterized in that: on Si sheet, produce at least two P+ isolated areas, in each P+ isolated area periphery, make again a N+ isolated area, then in each P+ isolated area, make grid, source, drain electrode.The essence of technique scheme is on a Si sheet, to make a plurality of N raceway groove JFET amplifiers, makes a plurality of N raceway groove JFET amplifiers form integrated device.

According to above-mentioned basic technical scheme, can there is following further technical scheme:

(1) buried regions oxidation, at silicon face growth one deck SiO ₂oxide layer;

(2) photoetching of P+ buried regions, utilizes photoetching technique, obtains one group of quantity at plural P+ buried regions figure;

(3) pre-oxidation, the thick high-quality SiO of each growth 20nm of P+ buried regions graphical window place opening in corrosion ₂oxide layer;

(4) buried regions boron injects, and utilizes ion implantation technique to mix finite concentration boron impurity in each P+ buried regions district;

(5) buried regions annealing, utilizes High temperature diffusion technology, and the boron impurity that each P+ buried regions district is injected carries out diffusion profile;

(6) P-epitaxial growth, at the silicon chip surface growth one deck P-epitaxial loayer (the single crystalline Si material of P type) after buried regions annealing;

(7) P+ isolation oxidation, at P-epi-layer surface growth one deck SiO ₂oxide layer is sheltered as Impurity Diffusion

(8) P+ isolation photoetching, utilizes photoetching technique to form the P+ isolation pattern corresponding with each P+ buried regions district;

(9) P+ isolated area note boron, utilizes ion implantation technique, in each P+ isolated area, injects finite concentration boron impurity;

(10) P+ isolated area annealing main diffusion, utilizes High temperature diffusion technique, and the boron impurity injecting is advanced to the certain junction depth of diffusion, realizes PN junction isolation, then removes SiO ₂masking film;

(11) deposit LTO, is removing masking film silicon chip surface, utilizes the silicon dioxide of LPCVD equipment deposit one deck 1000nm ± 100nm;

(12) photoetching of N+ isolated area, utilizes photoetching technique, forms the N+ isolated area figure corresponding to each P+ buried regions district (beyond buried regions district);

(13) N+ isolated area phosphorus precoating, utilizes oxide-diffused technology, will in each N+ isolated area, mix phosphorus impurities;

(14) main diffusion of N+ isolated area, utilizes diffusion technique, and the phosphorus impurities of precoating is advanced to certain junction depth, realizes PN junction isolation;

(15) N-(low concentration N mixes) channel region photoetching, utilizes photoetching technique, and each P+ buried regions district is formed to N-channel region figure;

(16) N-channel region phosphorus injects, and utilizes ion implantation technique, in each N-raceway groove graph area, mixes a certain amount of phosphorus impurities;

(17) the main expansion in N-channel region, utilizes High temperature diffusion technology, and the phosphorus impurities that each N-channel region is injected advances certain junction depth, forms conducting channel;

(18) photoetching of N+ source-drain area, utilizes photoetching technique, in each N-channel region, forms source-drain area figure;

(19) source-drain area note phosphorus, utilizes ion implantation technique, injects the phosphorus impurities of certain metering at each source-drain area;

(20) oxidation of N+ source-drain area advances, and utilizes High temperature diffusion technology, and the phosphorus impurities oxide-diffused of injection is distributed again;

(21) photoetching of P+ grid region, utilizes photoetching technique, between leak in source, forms grid region figure;

(22) P+ grid region note boron, utilizes ion implantation technique, injects the boron impurity of certain metering in grid region;

(23) oxidation of P+ grid region advances, and utilizes High temperature diffusion technology, and the boron impurity oxide-diffused of injection is distributed again;

(24) subsequent handling, aluminium etching, alloy, makes aluminium pressure point and silicon form good ohmic contact, completes the making of integrated JFET device.

The present invention has adopted integrated N raceway groove JFET design, N+ isolated area by producing in manufacture method, P+ isolated area two every technology, tool has the following advantages: (1) has adopted two isolation technologies, thoroughly eliminate the possibility of circuit electric leakage, eliminated each mutually crosstalking between unit that work alone.(2) realized the integrated of N ditch JFET amplifier.(3) dwindled the space that integrated circuit occupies, guaranteed to a greater extent the temperature performance of circuit, reduced noise, its integrated transporting discharging as the input utmost point has higher speed and wider bandwidth and higher input impedance, improved limiting frequency, guarantee less power consumption, strengthened the ability of anti-irradiation.

The N ditch JFET integrated amplifier PCM device parameters index of preparing is as follows:

N ditch JFET manages (the breadth length ratio W/L=200/8=25 of device)

The disconnected VP=-0.50～-1.0V of folder voltage

Saturation current IDSS=0.075mA～0.2mA (Vds=10V, Vgs=0V)

Source drain breakdown voltage BVDS >=15V.

Accompanying drawing explanation

Fig. 1, N ditch JFET integrated amplifier process chart;

Fig. 2-1-prepares schematic diagram for each main technological steps of N ditch JFET integrated amplifier in Fig. 2-24;

Fig. 3 is N ditch JFET integrated amplifier cross-sectional view.

Embodiment

Below in conjunction with accompanying drawing, most preferred embodiment of the present invention is further described,

Fig. 1 has provided the technological process of production of N ditch JFET integrated amplifier, and the processing step providing in conjunction with Fig. 2-1-Fig. 2-24 prepares schematic diagram, and the present invention is described specifically:

1) substrate is selected:

Substrate is chosen as (111) 4 cun of silicon wafer of N-type, resistivity 4-7 Ω .cm, thickness 500 μ m.

2) clean

Silicon chip need carry out chemical cleaning, and chemical reagent is the concentrated sulfuric acid and hydrogen peroxide.Sulfuric acid is strong oxidizer, in the process of cleaning, can generate natural oxidizing layer at silicon chip surface, therefore needs to adopt hydrofluoric acid corrosion, and high purity deionized water is rinsed, nitrogen protection centrifugal drying.

The proportioning of chemical reagent and ambient temperature:

Sulfuric acid: hydrogen peroxide=3: 1 temperature is 115 ± 5 ℃

Hydrofluoric acid: water=1: 10 temperature are room temperature

Deionized water resistivity >=17M Ω .cm.

3) buried regions oxidation-referring to Fig. 2-1, the present embodiment is the integrated device of 4 N ditch JFET pipes, for convenience of description, only draws the cutaway view of one of them N ditch JFET device, below all identical.

Buried regions oxidation is by silicon chip one deck SiO that shows to grow ₂, it is to carry out in high temperature oxidation furnace, and oxidizing temperature is the key parameter of growth oxide layer, and the accurate control of temperature will affect thickness evenness, and temperature is controlled at 1100 ± 1 ℃.

Oxidation is the method for oxidation that adopts dry oxygen+wet oxygen+dry oxygen.Dry oxygen refers to that dry oxygen directly sends in oxidation furnace, and dry-oxygen oxidation can obtain fine and close oxide layer.Wet oxygen is that oxygen carries water vapour and enters in oxidation furnace, and the growth rate of wet-oxygen oxidation is fast.Both are in conjunction with forming preferably oxidation technology condition.Oxygen flow 4L/min, 95 ± 1 ℃ of wet oxygen coolant-temperature gages.

Oxidization time: 10 minutes (dry oxygen)+150 minutes (wet oxygen)+10 minute (dry oxygen).

Oxidated layer thickness: 1000 ± 50nm.

Oxygen flow: 4L/min.

4) P+ buried regions photoetching---referring to Fig. 2-2, at SiO ₂the figure that on layer, photoetching designs, photoetching technique is known technology, mainly passes through following steps:

The photoetching of a.P+ buried regions,

Even glue: select positive photoresist.For guaranteeing the adhesiveness of photoresist and silicon chip, elder generation carries out tackified finish at silicon chip surface with HMDS, spin coating then, thick 1.0 ± 0.1 μ m of glue.

Front baking: the silicon chip that has applied photoresist is put into and filled nitrogen baking oven, and temperature setting is set to 90 ± 5 ℃, the time is 30 ± 2min (hot plate 1min).

Exposure: carry out the exposure of figure alignment with lay photoetching mask plate on mask aligner.Alignment precision is ± 0.05 μ m.

Develop: developer solution adopts the aqueous solution of Tetramethylammonium hydroxide, and proportioning is Tetramethylammonium hydroxide: water=1: 9; 20 ± 1 ℃ of development temperatures; Developing time 1 ± 0.1min.Deionized water rinsing centrifugal drying, deionized water resistivity >=17M Ω .cm.

Rear baking: the silicon chip after developing is put into and filled nitrogen baking oven, 120 ± 5 ℃ of temperature, the time is 30 ± 2min (hot plate 2～4min).

B, P+ buried regions etching

Adopt the method for wet etching, the region SiO2 corrosion that needs are injected is clean; Hydrofluoric acid: ammonium fluoride=1: 6; Etching time is 9 ± 0.2min.Deionized water rinsing centrifugal drying, deionized water resistivity >=17M Ω .cm.

C, remove photoresist

With sulfuric acid, remove photoresist, proportioning is sulfuric acid: hydrogen peroxide=3: 1; 120 ± 5 ℃ of temperature, the time is 15 ± 1min.Deionized water rinsing centrifugal drying, deionized water resistivity >=17M Ω .cm.

5) pre-oxidation---referring to Fig. 2-3, at the Si sheet exposing, show the SiO2 layer of regrowth layer:

Buried regions needs injection zone silicon chip surface in order to protect before injecting, the quality oxide layer of growth layer.Wafer sulfuric acid at 115 ℃ boils 15 minutes, and deionized water rinsing is clean; Hydrofluoric acid: water=1: 10 rinsings 10 seconds, deionized water rinsing centrifugal drying; Be oxidized 920 ± 1 ℃ of furnace temperature and pass into dry oxygen 35 ± 1min, oxygen flow 4L/min.

6) buried regions boron injection-referring to Fig. 2-4, note boron in the figure of photoetching,

Utilize ion implantation technique, the B11+ impurity that implantation dosage is 3.2E14; Implantation Energy is 100Kev.

7) buried regions annealing-referring to Fig. 2-5,

At oxide-diffused furnace temperature, be under 800 ℃～1180 ℃～800 ℃ conditions, (nitrogen+little oxygen) heats up and minute nitrogen+30, minute oxygen+600, stablize+20 minutes nitrogen+5 minute oxygen+nitrogen (being cooled to 800 ℃) to adopt 50 minutes, make the boron impurity injecting be distributed to again certain junction depth, square resistance is about 165 ± 10 Ω/square, and oxidated layer thickness is 150 ± 2nm.

8) P-extension---referring to Fig. 2-6,

Utilize HCL polishing etch silicon 80～150nm, growth parameter(s) is ρ: 4～5 Ω .cm; The P-epitaxial loayer of w:12～14um.

9) P+ isolation oxidation-referring to Fig. 2-7,

P+ isolation oxidation is also the method that adopts dry-oxygen oxidation.In furnace temperature, be under 920 ± 1 ℃ of conditions, to adopt the SiO2 oxide layer of 35 minutes dry oxide growth 20 ± 2nm.

10) P+ isolation photoetching-referring to Fig. 2-8,

Utilize photoetching technique, obtain the figure of P+ isolation.

11) P+ isolated area note boron---referring to Fig. 2-9,

Utilize ion implantation technique, the B11+ impurity that implantation dosage is 8E15; Implantation Energy is 40Kev.

12) P+ isolation annealing---referring to Fig. 2-10,

At oxide-diffused furnace temperature, be under 800 ℃～1180 ℃～800 ℃ conditions, (nitrogen+little oxygen) heats up and minute nitrogen+15, minute oxygen+50, stablize+20 minutes nitrogen+5 minute oxygen+nitrogen (being cooled to 800 ℃) to adopt 50 minutes, the boron impurity that makes to inject distributes and is connected (touching) with P+ buried regions, and oxidated layer thickness is 75 ± 1nm.

13) deposit LTO---referring to Fig. 2-11,

After the SIO2 of the silicon chip surface through P+ isolation annealing is eroded with hydrofluoric acid, utilize the loose silicon dioxide of LPCVD equipment low-temperature epitaxy 1000 ± 100nm, because temperature is lower both less on the impact of inside circuit Impurity Distribution, played masking action.

14) N+ isolated area photoetching-referring to Fig. 2-12,

Utilize the figure of photoetching technique acquisition N+ isolated area, and by the silicon dioxide etching in isolated area clean (reticle alignment P+ buried regions version herein).

15) N+ isolated area phosphorus precoating-referring to Fig. 2-13,

This operation is utilized High temperature diffusion technology, to in the isolated area of photoetching, utilize under the hot conditions of 1050 ± 1 ℃: 10 minutes (oxygen+nitrogen)+80 minute (oxygen+nitrogen+PCLO3)+10 minute oxygen, phosphorus source is diffused into isolated area surface, ShiN+ district forms certain junction depth and distributes, and square resistance is 3～6 Ω/square.

16) the main expansion of N+ isolated area---referring to Fig. 2-14,

This operation is closely connected with a upper procedure, the silicon chip extracting being painted with is in advance sent into the diffusion that heats up in main expansion stove at once, condition is: under 800 ℃～1180 ℃～800 ℃ conditions, adopt 50 minutes oxygen to heat up and minute nitrogen+30, stablize+10 minutes oxygen+480 minute oxygen+nitrogen (being cooled to 800 ℃), phosphorus impurities diffusion downwards in isolated area is connected with N_ substrate, thereby P_ epitaxial loayer is cut as P_ island independently, realize the isolation between device and device.

17) N channel region oxidation,

This operation under 1100 ± 1 ℃ of conditions, 5 minutes oxygen+30 minute (TCA+ oxygen)+5 minutes oxygen, growth one deck quality good oxide layer is as masking film, oxidated layer thickness 130～150nm; It is 0.2L/min that nitrogen carries TCA flow, and temperature is room temperature.

18) channel region photoetching-referring to Fig. 2-15;

Utilize photoetching technique to form channel region figure, and the region oxide layer corrosion that needs are injected clean (version of alignment N+ isolation herein).

19) channel region phosphorus injection-referring to Fig. 2-16,

Utilize ion implantation technique, the P31+ impurity that implantation dosage is 7E12; Implantation Energy is 80Kev.

20) the main expansion in N-channel region-referring to Fig. 2-17,

At oxide-diffused furnace temperature, be under 1000 ℃～1100 ℃～1000 ℃ conditions, + 5 minutes oxygen of (nitrogen+little oxygen) intensification is stablized minute oxygen+20 ,+5 minutes nitrogen+5 minute (TCA+ oxygen)+5 minutes oxygen+nitrogen (being cooled to 1000 ℃) to adopt 25 minutes, the phosphorus impurities injecting is distributed again, form the N_ channel region of certain depth.

21) N+ source-drain area photoetching-referring to Fig. 2-18,

Utilize photoetching technique to form source region and drain region figure, and will need the oxide layer corrosion clean (alignment N-channel region version herein) of injection zone.

22) source, drain region note phosphorus-referring to Fig. 2-19,

Utilize ion implantation technique, the P31+ impurity that implantation dosage is 4.5E15; Implantation Energy is 50Kev.

23) N+ source-drain area oxidation propelling-referring to Fig. 2-20,

In oxide-diffused furnace temperature, be under 920 ± 1 ℃ of conditions, adopt 5 minutes stable+5 minutes oxygen+30 minute (TCA+ the oxygen)+5 minutes oxygen of oxygen; Grow on the N+ thermal oxide layer of 60 ± 1nm.

24) P+ grid region photoetching-referring to Fig. 2-21,

Utilize photoetching technique to form the grid region figure of technotron, and its surface is needed to the region oxide layer etching clean (overlapping N+ source-drain area version herein) of injection.

25) P+ grid region note boron-referring to Fig. 2-22,

Utilize ion implantation technique, the B11+ impurity that implantation dosage is 4E15; Implantation Energy is 30Kev.

26) P+ grid region oxidation propelling-referring to Fig. 2-23,

Under 920 ± 1 ℃ of conditions of oxide-diffused stove, adopt the method for minute wet oxygen+10,10 minutes oxygen+30 minute oxygen, on P+ grid region, growth thickness is about the oxide layer of 85 ± 5nm, boron impurity annealing certain propelling of injection.

27) deposit LTO

Utilize LPCVD technology under 415 ± 1 ℃ of conditions, the comparatively loose silicon dioxide of low temperature deposition one deck 800 ± 50nm neither can cause larger impact to play again masking action simultaneously on circuit parameter under cryogenic conditions.

28) LTO density

In furnace temperature, be under 850 ± 1 ℃ of conditions, the loose silicon dioxide layer of LTO growth is carried out to densification, the temperature of 850 ℃ is very little on the electrical quantity impact of circuit simultaneously.

29) silicon nitride deposition

Utilize the silicon nitride film of LPCVD technology deposit 20 ± 1nm under 800 ± 1 ℃ of conditions as masking film.

30) contact hole version photoetching

Utilize photoetching technique to form the fairlead of circuit, use plasma dry etch silicon nitride and silicon dioxide, BOE (buffering silicon dioxide etching liquid) wet etching titanium dioxide.

31) annealing

Pretest device parameters (pinch-off voltage, saturation current and puncture voltage), selects high annealing condition (temperature 1000-1020 ℃, time, atmosphere), adjusts the parameter of device, makes it meet technical specification.

32) spatter fine aluminium

Sputter pure aluminium film, realizes certainly connecting and interconnection of circuit.

33) aluminium plate photoetching-referring to Fig. 2-24,

Utilize photoetching technique, form aluminum lead and pressure point.

34), passivation, utilize the silicon dioxide of PECVD deposition techniques 650 ± 10nm and the silicon nitride composite passivation film of 250 ± 10nm, in order to protective circuit.

35), alloy, under 420 ℃ of nitrogen atmospheres, carry out alloy annealing, 30 minutes alloy time, make to form good ohmic between aluminium and silicon and contact.

As shown in Figure 3 be the N ditch JFET integrated amplifier electrical connection schematic diagram of making, wherein comprise N1, N2, N3, tetra-N ditch JFET devices of N4, wherein two JFET pipes of N1, N3 select respectively four N-type area of isolation and two drain electrodes of any N-type area of isolation and N2, N4 pipe to join, as the power interface of circuit; Any P type area of isolation and the grid of the source electrode of N1, N3 pipe and N3 pipe join, as the earth terminal of circuit; Select any P type area of isolation and the grid of N1 pipe to join, as the input of circuit; The drain electrode of N1 pipe is connected with the source electrode of any P type isolated area and N2 pipe with the grid of N2, N4 pipe, as the inside pin connection of circuit; The source electrode of the drain electrode of N3 pipe and N4 pipe joins, as the output of circuit.

Claims (1)

1. the manufacture method of a N raceway groove JFET integrated amplifier, comprise: on Si sheet, make the single step with P+ isolated area, and the step of making grid, source, drain electrode in this P+ isolated area, on Si sheet epitaxy layer, produce two P+ isolated areas independently above, in each P+ isolated area periphery, make again a N+ isolated area, then in each P+ isolated area, make grid, source, drain electrode, it is characterized in that comprising the following steps:

(1) buried regions oxidation, at silicon chip surface growth one deck SiO ₂oxide layer;

(2) photoetching of P+ buried regions, utilizes photoetching technique, obtains one group of quantity at plural P+ buried regions figure;

(3) pre-oxidation, the thick SiO of each growth 20nm of P+ buried regions graphical window place opening in corrosion ₂oxide layer;

(4) buried regions boron injects, and utilizes ion implantation technique to mix boron impurity in each P+ buried regions district, the B11+ impurity that implantation dosage is 3.2E14, and Implantation Energy is 100Kev;

(5) buried regions annealing, utilizes High temperature diffusion technology, and the boron impurity that each P+ buried regions district is injected carries out diffusion profile;

(6) P-epitaxial growth, at the silicon chip surface growth one deck P-epitaxial loayer after buried regions annealing;

(7) P+ isolation oxidation, at P-epi-layer surface growth one deck SiO ₂oxide layer is as the masking film of Impurity Diffusion;

(8) P+ isolation photoetching, utilizes photoetching technique to form the P+ isolation pattern corresponding with each P+ buried regions district;

(9) P+ isolated area note boron, utilizes ion implantation technique, at each P+ isolated area B Implanted impurity, the B11+ impurity that implantation dosage is 8E15; Implantation Energy is 40Kev;

(10) P+ isolated area annealing main diffusion, utilizes High temperature diffusion technique, and the boron impurity injecting is advanced to diffusion 75 ± 1nm junction depth, forms P+ isolated area, then removes SiO ₂masking film;

(11) deposit LTO, is removing masking film silicon chip surface, utilizes the silicon dioxide of LPCVD equipment deposit one deck 1000nm ± 100nm;

(12) photoetching of N+ isolated area, utilizes photoetching technique, forms the N+ isolated area figure corresponding to each P+ isolated area;

(13) N+ isolated area phosphorus precoating, utilizes oxide-diffused technology, will in each N+ isolated area, mix phosphorus impurities;

(14) main diffusion of N+ isolated area, utilizes diffusion technique, advances diffusion to be connected with N-substrate the phosphorus impurities of precoating, forms N+ isolated area;

(15) photoetching of N--channel region, utilizes photoetching technique, and each P+ buried regions district is formed to N--channel region figure;

(16) N--channel region phosphorus injects, and utilizes ion implantation technique, in each N--raceway groove graph area, mixes phosphorus impurities, the P31+ impurity that implantation dosage is 7E12; Implantation Energy is 80Kev;

(17) the main expansion in N-channel region, utilizes High temperature diffusion technology, and the phosphorus impurities that each N-channel region is injected advances diffusion, forms N-conducting channel;

(18) photoetching of N+ source-drain area, utilizes photoetching technique, in each N-channel region, forms source-drain area figure;

(19) source-drain area note phosphorus, utilizes ion implantation technique, at each source-drain area, injects phosphorus impurities, the P31+ impurity that implantation dosage is 4.5E15; Implantation Energy is 50Kev;

(20) oxidation of N+ source-drain area advances, and utilizes High temperature diffusion technology, and the phosphorus impurities oxide-diffused of injection is distributed again;

(21) photoetching of P+ grid region, utilizes photoetching technique, between leak in source, forms grid region figure;

(22) P+ grid region note boron, utilizes ion implantation technique, at grid region B Implanted impurity, and the B11+ impurity that implantation dosage is 4E15; Implantation Energy is 30Kev;

(23) oxidation of P+ grid region advances, and utilizes High temperature diffusion technology, and the boron impurity oxide-diffused of injection is distributed again;

(24) subsequent handling, comprising: aluminium etching; Alloy, makes aluminium pressure point and silicon form ohmic contact, completes the making of integrated JFET device.