CN102915974B - Junction field-effect transistor (JFET) pipe compatible process with double pole and P-ditch aligning automatically - Google Patents
Junction field-effect transistor (JFET) pipe compatible process with double pole and P-ditch aligning automatically Download PDFInfo
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Abstract
The invention relates to a junction field-effect transistor (JFET) pipe compatible process with a double pole and a P-ditch aligning automatically. By means of grid region pre-oxidation, ditch region boron filling, grid region phosphorus filling and the annealing process, a method for manufacturing a double pole and grid self-aligning P-ditch JEFT compatible integrated amplifier is achieved. By means of the JEFT pipe compatible process, the shortcomings that a grid source/leakage overlapping parasitic capacitance formed by the existing non-self-aligning grid is large, a source end resistor and the drift region length are both large, and the device depends on graph dimension and dosage concentration of the ditch region and the drift region are overcome. The P-ditch JFET pipe process with the grid aligning automatically has the advantages of achieving self aligning of the grid region and the source/leak region, and reducing the drift region length of the grid source/leak overlapping parasitic capacitance and the source end resistance and the leakage end; and the P-ditch JEFT pipe is large in output dynamic resistance and, good in consistency of transconductance and punch-off voltage, and small in detuning and leakage current.
Description
Technical field
The invention belongs to semiconductor technology and manufacture field, particularly the P ditch JEFT pipe compatible technology of a kind of bipolar circuit and grid self-alignment structure.
Background technology
Greatly, source side resistance and drift region length are all bigger than normal, and device depends on dimension of picture and the doping content of channel region and drift region for the bipolar overlapping parasitic capacitance of grid source/drain formed with the non-self-aligned grid of P ditch autoregistration JFET pipe.One end and the grid of non-self-aligned grid drift region there will be some process deviations (such as photoetching CD, overlapping, etching CD etc.), all can affect the channel length of device, mainly affect larger by photoetching process and equipment.
Summary of the invention
Object of the present invention is exactly the defect that the overlapping parasitic capacitance of grid source/drain is large, manufacturing process deviation is large formed for solving existing non-self-aligned grid, the P ditch JEFT pipe compatible technology of a kind of bipolar circuit provided and grid self-alignment structure.
The technical solution used in the present invention is as follows:
A kind of bipolar with P ditch autoregistration JFET pipe compatible technology, comprise the following steps:
[1], buried regions oxidation---on substrate, grow layer of silicon dioxide buried regions;
[2], buried regions photoetching---photoetching N+ district figure on buried regions;
[3], buried regions arsenic injects--and at N+ district figure, utilize ion implantation technique to inject arsenic buried regions, arsenic implantation dosage is the arsenic impurities of 5E15, and Implantation Energy is 70Kev;
[4], arsenic buried regions annealing---form buried regions arsenic oxide layer after annealing, concrete annealing steps is as follows:
In oxide-diffused stove, temperature is that under 800 DEG C ~ 1180 DEG C ~ 800 DEG C conditions, gas time and pattern are: the N passing into 50min 800 DEG C time
2and O
2, be warming up to 1180 DEG C and keep stable, when 1180 DEG C, passing into 20minN successively
2, 5minO
2, 400minN
2, 30minO
2, finally pass into N
2be cooled to 800 DEG C, make the arsenic impurities of injection be distributed to certain junction depth again, the square resistance of arsenic buried regions arsenic is less than 18 Ω/square, and oxidated layer thickness is 230 ± 10nm;
[5], P+ district photoetching---bilateral symmetry position on substrate, makes the figure in P+ district respectively by lithography by photoetching process;
[6], P+ buried regions district note boron---utilize ion implantation technique to form P+ buried regions in P+ district, implantation dosage is the boron impurity of 3.4E14, and Implantation Energy is 60Kev;
[7], lower isolation annealing---annealed by substrate, P+ buried regions forms oxide layer, and annealing conditions is:
Under oxide-diffused furnace temperature is 920 DEG C ~ 1150 DEG C ~ 920 DEG C conditions, gas time and pattern are: 920 DEG C time, pass into 30 points of O successively
2, 30
pointn
2and O
2, the also 1150 DEG C of maintenances that heat up are stable, 1150 DEG C time, pass into 10minO successively
2, 40minN
2, 10minO
2, 10min wets O
2, 10minO
2, finally pass into N
2be cooled to 800 DEG C, make the boron impurity of injection be distributed to certain junction depth again;
[8], extension---utilize HCL polishing etch substrate silicon 50 ~ 100nm, oxide layer is above removed, then have the condition of hydrogen and hydrogen chloride gas in epitaxial furnace under, growth one deck single-crystal Si epitaxial layers, growth parameter(s) is ρ: (3.2 ~ 3.8) Ω .cm; W:(12.5 ~ 13.5) μm;
[9], isolation oxidation---on epitaxial loayer, grow layer of oxide layer, the condition that isolation oxidation technique adopts is: under furnace temperature is 1100 ± 1 DEG C of conditions, gas time and pattern are: pass into 10minO successively
2, 140min wets O
2, 10minO
2, the oxide layer of growth one deck 1000 ± 50nm;
[10], isolated area boron precoating---make isolated area figure by photoetching process and aim at P+ buried regions, isolated area is under furnace temperature is the condition of 920 DEG C ~ 1020 DEG C ~ 920 DEG C, and gas time and pattern are: pass into 35min N when 920 DEG C
2be warming up to 1020 DEG C, pass into 26min N
2and being cooled to 20 DEG C, boron source is diffused into isolated area surface, and the boron precoated shet forming the distribution of certain junction depth is aimed at P+ buried regions, and the square resistance of boron precoated shet is (16 ~ 18) Ω/square;
[11], main expansion is isolated---the substrate be painted with in advance by boron takes out to send in main expansion stove at once and carries out intensification diffusion, and condition is: under 800 DEG C ~ 1180 DEG C ~ 800 DEG C conditions, and gas time and pattern are 50 minutes O
2heat up and stablize+10minO
2+ 180minN
2+ 20minO
2+ N
2(being cooled to 800 DEG C), makes the diffusion downwards in isolation channel of the boron impurity of boron precoated shet be connected with P+ buried regions, thus makes
n-epitaxial loayer cuts as independently isolated island, realizes the PN junction isolation between device and device;
[12], base photoetching---in the substrate, utilize photoetching technique to form channel region figure, and the zone oxidation layer needing to inject is corroded clean;
[13], base boron injects---and the channel region in the substrate, utilize ion implantation technique to inject base boron, implantation dosage is 7E12's
boronimpurity, Implantation Energy is 80Kev;
[14], the main expansion in base---on base boron, grow oxide layer, under oxide-diffused furnace temperature is 920 DEG C ~ 1100 DEG C ~ 920 DEG C conditions, gas time and pattern are: pass into 10minO when 920 DEG C
2, and be warming up to 1100 DEG C, 1100 DEG C time, pass into 40minTCA and O successively
2, 10min O
2, 25minN
2, finally pass into N
2be cooled to 920 DEG C, the boron impurity of injection is distributed diffusion again, form the base of certain depth;
[15], emitter region photoetching---in the both sides of base boron, utilize photoetching technique to form emitter region figure, and by clean for the oxide layer corrosion in this region;
[16], emitter region note phosphorus---in emitter region, utilize ion implantation technique to inject emitter region phosphorus, implantation dosage is the P31+ impurity of 1E16, and Implantation Energy is 60Kev;
[17], the main expansion in emitter region---under oxide-diffused stove furnace temperature is 1100 ± 1 DEG C of conditions, gas time and pattern are: pass into 5min O successively
2, 23minTCA and O
2, 5min O
2; Emission layer phosphorus covers by the thermal oxide layer that N+ emitter region phosphorus 16 grows 100 ± 10nm;
[18], channel region photoetching---in the substrate, utilize photoetching technique to form channel region figure;
[19], grid region pre-oxidation---utilize thermal oxidation technology conditioned growth thin oxide layer, be used as the masking layer of channel region and grid region injection;
[20], channel region note boron---in channel region, utilize ion implantation technique to inject raceway groove boron impurity layer, boron impurity layer is connected with base, and boron impurity implantation dosage is the impurity of 7E12, and Implantation Energy is 80Kev;
[21], the main expansion in channel region---utilize oxide-diffused process, the boron impurity of injection is carried out propelling diffusion, and repair process is carried out to substrate surface damage structure cell;
[22], grid region is injected---and utilize ion implantation technique, boron impurity injects phosphorus impurities;
[23], grid region annealing---utilize oxide-diffused process, the phosphorus impurities of injection is carried out propelling diffusion, phosphorus impurities forms oxide layer, and repair process is carried out to silicon chip surface damage structure cell;
[24], deposited silicon nitride---the silicon nitride film masking layer of deposit one deck 35 ~ 40nm in the oxide layer of substrate;
[25], annealing---utilize high-temperature annealing process to be optimized debugging to PJFET pipe and bipolar NPN pipe, PNP pipe etc., make its device parameters reach device layout value;
[26], fairlead photoetching---utilize photoetching technique to form fairlead figure, and by clean for the oxide layer corrosion in fairlead region;
[27], aluminium is spattered---on substrate, sputter the pure aluminium film of one deck 1.2 ~ 1.5 μm, in fairlead, form certainly connecting and interconnection of aluminum lead realizing circuit;
[28], aluminium photoetching---utilize photoetching process, erode the nonuseable part of sputtering layer pure aluminium film, namely form aluminum lead;
[29], alloy annealing---under 500 DEG C of nitrogen, carry out alloy annealing, 30 minutes alloy time, make aluminium pressure point and silicon form good ohmic and contact.
The P ditch JEFT plumber skill tool of grid self-alignment structure of the present invention has the following advantages: (1) achieves grid region and source/drain region autoregistration, reduces the drift region length of the overlapping parasitic capacitance of grid source/drain and source side resistance and drain terminal.(2) grid self-alignment structure P ditch JEFT pipe exports that dynamic electric resistor is large, mutual conductance is good with pinch-off voltage consistency, imbalance and leakage current little.
Accompanying drawing explanation
Fig. 1-Figure 11 is each processing step flow chart of the present invention;
Figure 12 is existing non-self-aligned PJFET pipe cross-sectional view, and the phosphorus impurities 19 that grid region is injected is in boron impurity 18 non-self-aligned position.
Embodiment
First substrate is chosen as P type <111>4 cun of silicon wafer, resistivity (8-13) Ω .cm, thickness (525 ± 20) μm; Then clean substrate: silicon chip need carry out chemical cleaning, cleaning chemical reagent is the concentrated sulfuric acid, hydrogen peroxide and hydrofluoric acid.The concentrated sulfuric acid and hydrogen peroxide are strong oxidizer, can remove particle or the dust of silicon chip surface.Can generate natural oxidizing layer at silicon chip surface in the process of boiling down sulfuric acid, hydrofluoric acid rinse need be adopted to corrode, high purity deionized water is rinsed, nitrogen protection centrifugal drying.
The proportioning of chemical reagent and ambient temperature:
Sulfuric acid: hydrogen peroxide=3:1 temperature is (115 ± 5) DEG C
Hydrofluoric acid: water=1:30 temperature is room temperature
Deionized water resistivity >=18M Ω .cm.
One provided by the invention is bipolar with P ditch autoregistration JFET pipe compatible technology, comprises the following steps:
1, buried regions oxidation---as shown in Figure 1, silicon chip 1 grows layer of silicon dioxide buried regions 2.
Buried regions oxidation carries out in high temperature oxidation furnace.Oxidizing temperature is the key parameter of growth oxide layer, and the accurate control of temperature will affect thickness evenness, and temperature controls at 1100 ± 1 DEG C.
Oxidation adopts O
2+ wet O
2+ O
2gas mode be oxidized.O
2refer to that dry oxygen is directly sent in oxidation furnace, dry-oxygen oxidation can obtain the oxide layer of dense uniform.Wet O
2that oxygen carries water vapour and enters in oxidation furnace, wet O
2the growth rate of oxidation is fast.Both combine can form preferably oxidation process conditions.O
2flow 4L/min, wet O
2coolant-temperature gage (95 ± 1) DEG C.
Oxidization time: 10min (O
2)+150min (wet O
2)+10min (O
2).
Oxidated layer thickness: 1000 ± 50nm.
Oxygen flow: 4L/min.
2, buried regions photoetching---as shown in Figure 2, photoetching N+ district figure 3 on buried regions 2, lithography step is as follows:
Even glue: select positive photoresist.For ensureing the adhesiveness of photoresist and silicon chip, first carry out tackified finish at silicon chip surface HMDS, then spin coating, thick 1.5 ± 0.1 μm of glue.
Front baking: will apply on the silicon chip heat liberation board of photoresist, temperature be set to 100 ± 5 DEG C, and the time is 1min.
Exposure: carry out the exposure of figure alignment with lay photoetching mask plate on mask aligner.Alignment precision is ± 0.5 μm.
Development: development temperature (20 ± 1) DEG C; Developing time (1 ± 0.1) min.Deionized water rinsing centrifugal drying, deionized water resistivity >=18M Ω .cm.
Rear baking: put into by the silicon chip after development and fill nitrogen baking oven, temperature (120 ± 5) DEG C, the time is (30 ± 2) min.
3, buried regions arsenic injects--and as shown in Figure 3, in photoetching N+ district figure 3, utilize ion implantation technique to inject arsenic buried regions 4, arsenic implantation dosage is the arsenic impurities of 5E15, and Implantation Energy is 70Kev.
4, arsenic buried regions annealing---as shown in Figure 3, form buried regions arsenic oxide layer 5 after annealing, concrete annealing steps is as follows:
Under oxide-diffused furnace temperature is 800 DEG C ~ 1180 DEG C ~ 800 DEG C conditions, adopt 50min(N
2+ O
2) heat up and stablize+20minN
2+ 5minO
2+ 400minN
2+ 30minO
2+ N
2(being cooled to 800 DEG C), makes the arsenic impurities of injection be distributed to certain junction depth again, and the square resistance of buried regions arsenic 4 is less than 18 Ω/square, and oxidated layer thickness is (230 ± 10) nm.
Described oxygen and the flow of nitrogen are: 4L/min, described little O
2flow be: 0.2L/min, all identical below.
5, P+ district photoetching---as shown in Figure 4, bilateral symmetry position on substrate, make P+ district figure 6 respectively by lithography by photoetching process, concrete steps are as follows:
Even glue: select positive photoresist.For ensureing the adhesiveness of photoresist and silicon chip, first carry out tackified finish at silicon chip surface HMDS, then spin coating, thick 1.5 ± 0.1 μm of glue.
Front baking: be placed on hot plate by the silicon chip having applied photoresist, temperature is set to [100 ± 5] DEG C, and the time is 1min.
Exposure: carry out the exposure of figure alignment with lay photoetching mask plate on mask aligner.Alignment P+ buried regions figure, alignment precision is ± 0.5 μm.
Development: development temperature 20 ± 1 DEG C; Developing time 1 ± 0.1min.Deionized water rinsing centrifugal drying, deionized water resistivity >=18M Ω .cm.
Rear baking: put into by the silicon chip after development and fill nitrogen baking oven, temperature 120 ± 5 DEG C, the time is 30 ± 2min.
6, P+ buried regions district note boron---as shown in Figure 4, utilize ion implantation technique to form P+ buried regions 8 in P+ district, implantation dosage is the boron impurity of 3.4E14, and Implantation Energy is 60Kev.
7, lower isolation annealing---as shown in Figure 4, substrate is annealed, P+ buried regions 8 is formed oxide layer 7.
Under oxide-diffused furnace temperature is 920 DEG C ~ 1150 DEG C ~ 920 DEG C conditions, adopt 30 points of O
2+ 30
point(N
2+ O
2) heat up and stablize+10minO
2+ 40minN
2+ 10minO
2+ 10min wets O
2+ 10minO
2+ N
2(being cooled to 800 DEG C), makes the boron impurity of injection be distributed to certain junction depth again.
8, extension---as shown in Figure 5, utilize HCL polishing etch silicon 50 ~ 100nm(that the oxide layer 2,5 above Fig. 4 is removed), then grown epitaxial layer 9(grows one deck monocrystalline silicon have the condition of hydrogen and hydrogen chloride gas in epitaxial furnace under), growth parameter(s) is ρ: (3.2 ~ 3.8) Ω .cm; W:(12.5 ~ 13.5) μm.
9, isolation oxidation---as shown in Figure 6, epitaxial loayer 9 grows layer of oxide layer 10.
Isolation oxidation adopts 10minO under furnace temperature is 1100 ± 1 DEG C of conditions
2+ 140min wets O
2+ 10minO
2method growth (1000 ± 50) nm oxide layer.
10, isolated area boron precoating---as shown in Figure 6, make isolated area 11 figure (aiming at P+ buried regions 8), utilize the condition of 920 DEG C ~ 1020 DEG C ~ 920 DEG C in isolated area 11 under: 35min N by photoetching process
2heat up+26min N
2, boron source is diffused into isolated area 11 surface, and the boron precoated shet 12(forming certain junction depth distribution aims at P+ buried regions 8), the square resistance of boron precoated shet 12 is (16 ~ 18) Ω/square.
11, main expansion is isolated---as shown in Figure 6, the silicon chip extracting be painted with in advance by boron is sent in main expansion stove at once and is carried out intensification diffusion, and condition is: under 800 DEG C ~ 1180 DEG C ~ 800 DEG C conditions, adopts 50 minutes O
2heat up and stablize+10minO
2+ 180minN
2+ 20minO
2+ N
2(being cooled to 800 DEG C), makes boron impurity 12 diffusion downwards in isolation channel be connected with 8, thus makes
n-epitaxial loayer cuts as independently isolated island, realizes the PN junction isolation between device and device.
12, base photoetching, corrosion---in the middle of Fig. 7 substrate, utilize photoetching technique to form channel region 13 figure, and by clean for the zone oxidation layer corrosion needing to inject.
13, base boron injects---and the channel region 13 in the figure 7, utilize ion implantation technique to inject base boron 14, implantation dosage is 7E12's
boronimpurity, Implantation Energy is 80Kev.
14, the main expansion in base---as shown in Figure 8, on base boron 14, grow oxide layer 10, under oxide-diffused furnace temperature is 920 DEG C ~ 1100 DEG C ~ 920 DEG C conditions, adopt 10minO
2+ 40min (TCA+O
2)+10min O
2+ 25minN
2+ cooling N
2(to 920 DEG C), make the boron impurity of injection distribute diffusion again, form the base 14 of certain depth.
15, emitter region photoetching, corrosion---as shown in Figure 8, in the both sides of base boron 14, utilize photoetching technique to form emitter region 15 figure, and by clean for the oxide layer corrosion in this region.
16, emitter region note phosphorus---as shown in Figure 8, in emitter region 15, utilize ion implantation technique to inject emitter region phosphorus 16, implantation dosage is the P31+ impurity of 1E16, and Implantation Energy is 60Kev.
17, the main expansion in emitter region---as shown in Figure 9, under oxide-diffused furnace temperature is (1100 ± 1) DEG C condition, adopt 5min O
2+ 23min(TCA+ O
2)+5min O
2; Emission layer phosphorus 16 covers by the thermal oxide layer 10 that N+ grows (100 ± 10) nm.
18, channel region photoetching---as shown in Figure 9, in the substrate, utilize photoetching technique to form channel region 17 figure.
19, grid region pre-oxidation---as shown in Figure 9, utilize thermal oxidation technology conditioned growth thin oxide layer, be used as the masking layer of channel region and grid region injection.
20, channel region note boron---as shown in Figure 9, in channel region 17, utilize ion implantation technique to inject raceway groove boron impurity layer 18, boron impurity layer 18 is connected with base 14, and boron impurity implantation dosage is 7E12, and Implantation Energy is 80Kev.
21, the main expansion in channel region---as shown in Figure 10, utilize oxide-diffused process, the boron impurity 18 of injection is carried out propelling diffusion, and repair process is carried out to silicon chip surface damage structure cell.
22, grid region is injected---and as shown in Figure 10, utilize ion implantation technique, boron impurity 18 injects phosphorus impurities 19.
23, grid region annealing---as shown in Figure 10, utilize oxide-diffused process, the phosphorus impurities 19 of injection is carried out propelling diffusion, phosphorus impurities 19 is formed oxide layer 10, and repair process is carried out to silicon chip surface damage structure cell.
24, deposited silicon nitride---as shown in figure 11, the silicon nitride film masking layer 20 of deposit one deck (35 ~ 40) about nm on substrate.
25, anneal---utilize high-temperature annealing process to be optimized debugging to PJFET pipe and bipolar NPN pipe, PNP pipe etc., make its device parameters reach device layout value.
26, fairlead photoetching-as shown in figure 11, utilize photoetching technique to form fairlead figure, and by clean for the oxide layer corrosion in fairlead region.
27, spatter aluminium-as shown in figure 11, substrate sputters the pure aluminium film of one deck (1.2 ~ 1.5) μm, by certainly connecting and interconnection of aluminum lead realizing circuit in fairlead.
28, aluminium photoetching-as shown in figure 11, utilize photoetching process, erode the nonuseable part of sputtering layer pure aluminium film, namely form aluminum lead 21.
29, alloy annealing---under 500 DEG C of nitrogen, carry out alloy annealing, 30 minutes alloy time, make aluminium pressure point and silicon form good ohmic and contact.
Utilize above-mentioned technology, for preparing is bipolar as follows with autoregistration PJEFT integrated amplifier PCM device parameters index:
The electrical quantity of autoregistration PJEFT pipe is: Vp (0.7 ~ 1.1) V, V (BR)
dS>=30V, Idss (28 ~ 38) μ A(V
gS=0V, V
dS=10V).
The main electric parameters of NPN pipe is :=80 ~ 150 (Ib=1uA, Vce=5V), BVceo >=45V (Iceo=0.1mA), BVbco >=45V (Icbo=0.1mA), Bvebo:(6.5 ~ 7.5) V (Iebo=0.1mA);
The main electric parameters of Semi-active suspension is: β >=20 (Ib=1uA, Vce=-5V), BVceo >=45 (Iceo=0.1mA), BVebo >=45(Iebo=0.1mA), BVcbo >=45(Icbo=0.1mA);
The main electric parameters of longitudinal P NP pipe is: β >=20 (Ib=1uA, Vce=-5V), BVceo >=45V (Iceo=0.1mA);
BVebo≥60V(Iebo=0.1mA)、BVcbo≥60V?(Icbo=0.1mA)；
Base resistance is: R=(200 ± 40) Ω/.
Claims (1)
1. bipolar with a P ditch autoregistration JFET pipe compatible technology, comprise the following steps:
[1], buried regions oxidation: at substrate (1) upper growth layer of silicon dioxide buried regions (2);
[2], buried regions photoetching: in upper photoetching N+ district figure (3) of buried regions (2);
[3], buried regions arsenic injects: in N+ district figure (3), utilize ion implantation technique to inject arsenic buried regions (4), arsenic implantation dosage is 5E15/cm
2arsenic impurities, Implantation Energy is 70Kev;
[4], arsenic buried regions annealing: form buried regions arsenic oxide layer (5) after annealing, concrete annealing steps is as follows:
In oxide-diffused stove, temperature is that under 800 DEG C ~ 1180 DEG C ~ 800 DEG C conditions, gas time and pattern are: the N passing into 50min 800 DEG C time
2and O
2, be warming up to 1180 DEG C and keep stable, when 1180 DEG C, passing into 20minN successively
2, 5minO
2, 400minN
2, 30minO
2, finally pass into N
2be cooled to 800 DEG C, make the arsenic impurities of injection be distributed to certain junction depth again, the square resistance of arsenic buried regions arsenic 4 is less than 18 Ω/square, and oxidated layer thickness is 230 ± 10nm;
[5], P+ district photoetching: bilateral symmetry position on substrate, makes the figure of P+ district (6) respectively by lithography by photoetching process;
[6], P+ buried regions district note boron: utilize ion implantation technique to form P+ buried regions (8) in P+ district, implantation dosage is 3.4E14/cm
2boron impurity, Implantation Energy is 60Kev;
[7], lower isolation annealing: annealed by substrate, P+ buried regions (8) is formed oxide layer (7), and annealing conditions is:
Under oxide-diffused furnace temperature is 920 DEG C ~ 1150 DEG C ~ 920 DEG C conditions, gas time and pattern are: 920 DEG C time, pass into 30 points of O successively
2, 30
pointn
2and O
2, the also 1150 DEG C of maintenances that heat up are stable, 1150 DEG C time, pass into 10minO successively
2, 40minN
2, 10minO
2, 10min wets O
2, 10minO
2, finally pass into N
2be cooled to 800 DEG C, make the boron impurity of injection be distributed to certain junction depth again;
[8], extension: utilize HCL polishing etch substrate silicon 50 ~ 100nm, oxide layer is above removed, then have the condition of hydrogen and hydrogen chloride gas in epitaxial furnace under, grow one deck single-crystal Si epitaxial layers (9), growth parameter(s) is ρ: 3.2 ~ 3.8 Ω .cm; W:12.5 ~ 13.5 μm;
[9], isolation oxidation: grow layer of oxide layer (10) on epitaxial loayer (9), the condition that isolation oxidation technique adopts is: under furnace temperature is 1100 ± 1 DEG C of conditions, gas time and pattern are: pass into 10minO successively
2, 140min wets O
2, 10minO
2, the oxide layer (10) of growth one deck 1000 ± 50nm;
[10], isolated area boron precoating: make isolated area (11) figure by photoetching process and aim at P+ buried regions (8), isolated area (11) is under furnace temperature is the condition of 920 DEG C ~ 1020 DEG C ~ 920 DEG C, and gas time and pattern are: pass into 35min N when 920 DEG C
2be warming up to 1020 DEG C, pass into 26min N
2and being cooled to 20 DEG C, boron source is diffused into isolated area (11) surface, the boron precoated shet (12) forming the distribution of certain junction depth is aimed at P+ buried regions (8), and the square resistance of boron precoated shet (12) is (16 ~ 18) Ω/square;
[11], main expansion is isolated: the substrate be painted with in advance by boron takes out to send in main expansion stove at once and carries out intensification diffusion, and condition is: under 800 DEG C ~ 1180 DEG C ~ 800 DEG C conditions, gas time and pattern are: when 800 DEG C, pass into 50 minutes O
2be warming up to 1180 DEG C and keep stable, 1180 DEG C time, passing into 10minO successively
2, 180minN
2, 20minO
2, finally pass into N
2and be cooled to 800 DEG C, the diffusion downwards in isolation channel of the boron impurity of boron precoated shet (12) is connected with P+ buried regions (8), thus makes
n-epitaxial loayer cuts as independently isolated island, realizes the PN junction isolation between device and device;
[12], base photoetching: in the substrate, utilize photoetching technique to form channel region (13) figure, and the zone oxidation layer needing to inject is corroded clean;
[13], base boron injects: the channel region (13) in the substrate, utilize ion implantation technique to inject base boron (14), implantation dosage is 7E12/cm
2's
boronimpurity, Implantation Energy is 80Kev;
[14], the main expansion in base: grow oxide layer (10) on base boron (14), under oxide-diffused furnace temperature is 920 DEG C ~ 1100 DEG C ~ 920 DEG C conditions, gas time and pattern are: pass into 10minO when 920 DEG C
2, and be warming up to 1100 DEG C, 1100 DEG C time, pass into 40minTCA and O successively
2, 10min O
2, 25minN
2, finally pass into N
2be cooled to 920 DEG C, the boron impurity of injection is distributed diffusion again, form the base boron (14) of certain depth;
[15], emitter region photoetching: in the both sides of base boron (14), utilize photoetching technique to form emitter region (15) figure, and by clean for the oxide layer corrosion in this region;
[16], emitter region note phosphorus: in emitter region (15), utilize ion implantation technique to inject emitter region phosphorus (16), implantation dosage is 1E16/cm
2p31+ impurity, Implantation Energy is 60Kev;
[17], the main expansion in emitter region: under oxide-diffused stove furnace temperature is 1100 ± 1 DEG C of conditions, gas time and pattern are: pass into 5min O successively
2, 23minTCA and O
2, 5min O
2; Emission layer phosphorus (16) covers by the thermal oxide layer (10) that N+ emitter region phosphorus 16 grows 100 ± 10nm;
[18], channel region photoetching: in the substrate, utilize photoetching technique to form channel region (17) figure;
[19], grid region pre-oxidation: utilize thermal oxidation technology conditioned growth oxide layer, be used as the masking layer of channel region and grid region injection;
[20], channel region note boron: in channel region (17), utilize ion implantation technique to inject raceway groove boron impurity layer (18), boron impurity layer (18) is connected with base boron (14), and boron impurity implantation dosage is 7E12/cm
2, Implantation Energy is 80Kev;
[21], the main expansion in channel region: utilize oxide-diffused process, the boron impurity layer (18) injected is carried out propelling diffusion, and repair process is carried out to substrate surface damage structure cell;
[22], grid region is injected: utilize ion implantation technique, boron impurity layer (18) injects phosphorus impurities (19);
[23], grid region annealing: utilize oxide-diffused process, the phosphorus impurities (19) injected is carried out propelling diffusion, phosphorus impurities (19) is formed oxide layer (10), and repair process is carried out to silicon chip surface damage structure cell;
[24], deposited silicon nitride: at the silicon nitride film masking layer (20) of the upper deposit one deck 35 ~ 40nm of the oxide layer (10) of substrate;
[25], annealing: utilize annealing process to PJFET pipe and bipolar NPN manages, PNP pipe is optimized debugging, make its device parameters reach device layout value;
[26], fairlead photoetching: utilize photoetching technique to form fairlead figure, and by clean for the oxide layer corrosion in fairlead region;
[27], spatter aluminium: the pure aluminium film sputtering one deck 1.2 ~ 1.5 μm on substrate, in fairlead, form certainly connecting and interconnection of aluminum lead realizing circuit;
[28], aluminium photoetching: utilize photoetching process, erode the nonuseable part of sputtering layer pure aluminium film, namely form aluminum lead (21);
[29], alloy annealing: carry out alloy annealing under 500 DEG C of nitrogen, 30 minutes alloy time, make aluminium pressure point and silicon form good ohmic and contact.
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| EP0823727A1 (en) * | 1996-07-10 | 1998-02-11 | STMicroelectronics S.A. | Process for making the extrinsic base of a NPN transistor in a bipolar high frequency technology |
| CN102130053A (en) * | 2010-12-03 | 2011-07-20 | 华东光电集成器件研究所 | Method for making integrated amplifier of N-channel junction field effect transistor (JFET) |
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| EP0823727A1 (en) * | 1996-07-10 | 1998-02-11 | STMicroelectronics S.A. | Process for making the extrinsic base of a NPN transistor in a bipolar high frequency technology |
| CN102130053A (en) * | 2010-12-03 | 2011-07-20 | 华东光电集成器件研究所 | Method for making integrated amplifier of N-channel junction field effect transistor (JFET) |
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