CN102122634A - Method for etching through hole and metal wire trench - Google Patents
Method for etching through hole and metal wire trench Download PDFInfo
- Publication number
- CN102122634A CN102122634A CN2010100227229A CN201010022722A CN102122634A CN 102122634 A CN102122634 A CN 102122634A CN 2010100227229 A CN2010100227229 A CN 2010100227229A CN 201010022722 A CN201010022722 A CN 201010022722A CN 102122634 A CN102122634 A CN 102122634A
- Authority
- CN
- China
- Prior art keywords
- layer
- etching
- hole
- stops
- stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for etching a through hole and a metal wire trench. The method comprises the following steps: depositing a through hole etching stop layer and a through hole dielectric layer on a semiconductor substrate, forming the through hole through etching, and filling copper in the through hole by utilizing an ECP (electro-chemical plating) process so as to form a copper layer; carrying out planarization; alternately depositing N stop layers and N oxide dielectric layers on the planarized through hole and through hole dielectric layer; depositing a dielectric antireflective coating (DARC) and a PR (photoresist) layer, and patterning the PR layer; taking the patterned PR layer as a mask to etch the DARC; and respectively carrying out a main etch (ME) process on the oxide dielectric layers, respectively carrying out an over etch (OE) process and a middle stop layer etch process on the middle stop layers, and finally carrying out the OE process on the first stop layer so as to form the ultra-thick metal wire trench. By utilizing the method, the phenomena that the oxide dielectric layers can not be fully eliminated, the etching depth in the stop layers exceeds the maximum permissible value and even the stop layers are punched can be prevented.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor components and devices, refer in particular to the lithographic method of a kind of through hole and metal wire groove.
Background technology
Through hole has important effect as the passage that is connected between multiple layer metal inter-level interconnects and device active region and the external circuitry in device architecture is formed.In order to guarantee the stability of device work, require the through hole behind the filled conductive material to have the favorable conductive characteristic, promptly resistance is the smaller the better, and this makes strictness control to via etch process become extremely important.
Along with the dense degree of device and the complexity of technology constantly increase, via etch process is had higher requirement.Deep-submicron size development along with integrated circuit, characteristic size (CD) diminishes gradually, after semiconductor fabrication process entered 65nm and even 45nm node technology, at super thick metal interconnecting wires and via process thereof, lithographic method adopted two stage lithographic methods mostly.
Fig. 1 is the flow chart of the lithographic method of through hole of the prior art and metal wire groove.Fig. 2 a～Fig. 2 e is the schematic diagram of the lithographic method of through hole and metal wire groove in the prior art.Shown in Fig. 1, Fig. 2 a～Fig. 2 e, the lithographic method of through hole of the prior art and metal wire groove comprises step as described below:
Shown in Fig. 2 a, in this step, at first on Semiconductor substrate 200, deposit via etch successively and stop layer 201 and through hole dielectric layer 202; Then, utilize photoetching technique on through hole dielectric layer 202, to define the opening figure of through hole, form through hole 210 by etching again; Then, for the through hole dielectric layer 202 of the sidewall of the copper metal that makes follow-up filling and through hole 210 has good adhesiveness, simultaneously in order to prevent that the copper metal from spreading in through hole dielectric layer 202, can deposit an adhesion barrier layer 203 earlier before filling the copper metal, this adhesion barrier layer 203 generally can be made of tantalum or tantalum nitride (Ta/TaN) composition; After this, on adhesion barrier layer 203, form the crystal seed layer 204 of copper, re-use ECP technology and in through hole 210, fill the copper metal, form copper layer 205.
Shown in Fig. 2 b, in this step, can carry out planarization, with unnecessary copper layer 205, crystal seed layer 204 and the adhesion barrier layer 203 on the surface of removing through hole dielectric layer 202 by CMP technology.
Shown in Fig. 2 c, in this step, can on through hole after the planarization and through hole dielectric layer, deposit successively and stop layer (a Stop Layer) 206, oxidation insulating layer (Oxide Dielectric Layer) 207, insulation antireflecting coating (DARC, Dielectric Antireflective Coating) 208 and PR layer 209.Wherein, above-mentioned layer, oxidation insulating layer and the insulation antireflecting coating of stopping to be generically and collectively referred to as super thick metal wire channel medium layer.Then, can carry out patterned process, after promptly photoresist layer 209 being exposed and developing, obtain the photoresist layer 209 of patterning according to the figure of required transfer printing to above-mentioned photoresist layer 209.
In addition, the above-mentioned main component that stops layer 206 can be a kind of or its combination in any in silicon nitride (SiN), carborundum (SiC), silicon oxide carbide (SiOC) or the carbonitride of silicium materials such as (SiNC), is SiN generally speaking; The main component of above-mentioned oxidation insulating layer 207 can be non-doped silicon glass (USG, Undoped Silicate Glass); Above-mentioned insulation antireflecting coating 208 is as light-absorption layer, and its main component is generally SiON.Above-mentioned stop layer 206 thickness be generally 1200 dusts (
), the thickness of oxidation insulating layer 207 is generally 34000
, the thickness of insulation antireflecting coating 208 is generally 600
Shown in Fig. 2 c, in this step, will be mask with the photoresist layer 209 of above-mentioned patterning, insulation antireflecting coating 208 is carried out etching, to form follow-up etching window of carrying out main etching.
Shown in Fig. 2 d, in this step, after finishing above-mentioned etching, will carry out main etching technology to the insulation antireflecting coating, promptly above-mentioned oxidation insulating layer 207 is carried out etching by etching mode commonly used (for example, Chang Yong dry etching etc.).
When oxidation insulating layer 207 being carried out etching by above-mentioned main etch process, in order to guarantee complete etching to oxidation insulating layer 207, to carry out over etching technology to stopping layer 206, promptly when using above-mentioned main etching technology to etch into to stop layer, to stop main etching technology, and use over etching technology to stopping the etching that layer 206 carries out certain depth, and removed fully with the oxidation insulating layer 207 that guarantees required etching, also need keep the certain thickness layer 206 that stops simultaneously.Shown in Fig. 2 e.
After finishing above-mentioned steps 106, can form required super thick metal wire groove.And in follow-up technology, can in above-mentioned formed super thick metal wire groove, fill corresponding metal, thereby form required super thick metal wire.
Above-described step is the execution mode under the perfect condition.And in practical situations, because the restriction of semiconductor technology precision, when carrying out main etching technology, be difficult to guarantee the average etching on the etching depth direction, thereby make in the time will finishing main etching technology, there is a certain distance in the etching depth at each position and inequality in the oxidation insulating layer 207 that is etched.Therefore, when etching depth the best part in the main etching technology has touched when stopping layer, the part of etching depth minimum also has certain distance from stopping layer, as shown in Figure 3.At this moment, because the etching depth the best part has touched and stopped layer, therefore need switch to etch process.In main etching technology, required etch material is mainly the oxide (Oxide) in the oxidation insulating layer 207, and in over etching technology, required etch material is mainly the silicon nitride (SiN) that stops in the layer 206.Therefore, the selection of employed Oxide/SiN is more inequality than (promptly to the etching speed of Oxide and ratio to the etching speed of SiN) in main etching technology and over etching technology.
As shown in Figure 3, establish when etching depth the best part in the main etching technology and contacted when stopping layer, the part of etching depth minimum is A from the distance that stops layer; And in over etching technology, need to guarantee certain loss and residual owing to stop layer, therefore in over etching technology, must be provided with one and stop the depth capacity B that layer can be etched.Hence one can see that, and in order to remove the oxidation insulating layer 207 of required etching before reaching B fully stopping the degree of depth to be etched of layer, the selection of the Oxide/SiN in over etching technology then must satisfy condition than S: S 〉=A/B.
In the prior art, because the restriction of semiconductor technology precision, and the thickness of oxidation insulating layer 207 is very big, for example, be generally 33000～35000 dusts (
), therefore the minimum value of above-mentioned A is generally 5000
, and wear (Punch Through) phenomenon the quarter that stops layer in order to prevent, the maximum of general B is set to 400 in the prior art
, so the selection of required Oxide/SiN must could be satisfied technological requirement more than or equal to 12.5: 1 than S in the over etching technology.But in the prior art, the maximum of the S that can reach in the over etching technology only is 6: 1.Therefore, in the over etching technology in the prior art, be no more than B if guarantee the maximum etch degree of depth that stops layer, then can make the required removal oxidation insulating layer of part not by complete etching, thereby cause the residual of oxidation insulating layer, follow-up technology is caused adverse influence, as shown in Figure 4; And if guarantee to remove fully the oxidation insulating layer of required removal, then can take place the etching depth that stops layer being surpassed the maximum B that is allowed, even stop the layer quarter wear phenomenon, as shown in Figure 5, thereby the electric property of formed semiconductor device is caused great adverse effect.
Summary of the invention
In view of this, the invention provides the lithographic method of a kind of through hole and metal wire groove, thus avoid removing fully required etching oxidation insulating layer phenomenon and the etching depth that stops layer being surpassed the maximum that is allowed or wears the phenomenon that stops layer quarter.
For achieving the above object, the technical scheme among the present invention is achieved in that
The lithographic method of a kind of through hole and metal wire groove, this method comprises:
The deposition via etch stops layer and through hole dielectric layer on Semiconductor substrate, forms through hole by etching, and uses the electrochemistry depositing process to fill the copper metal in through hole, forms the copper layer; Carry out planarization by CMP (Chemical Mechanical Polishing) process;
Alternating deposit N stops layer and N oxidation insulating layer successively on through hole after the planarization and through hole dielectric layer; Described N stops layer and comprises: be deposited on first on through hole after the planarization and the through hole dielectric layer stop layer and (N-1) the individual centre that is deposited between each oxidation insulating layer stop layer;
In the end deposition insulation antireflecting coating and photoresist layer on Chen Ji the oxidation insulating layer carry out patterned process to photoresist layer; Photoresist layer with patterning is a mask, etching insulation antireflecting coating;
Described each oxidation insulating layer is carried out main etching technology respectively, the described layer that stops in the middle of each is carried out over etching technology and centre respectively and stops a layer etching technics, stop layer to first at last and carry out over etching technology, form super thick metal wire groove.
This method also further comprises: preestablish described each and stop the thickness of layer and the thickness of each oxidation insulating layer.
The etching gas that is adopted in the described main etching technology is the fluorocarbons chemical gas.
Described fluorocarbons chemical gas is:
A kind of gas in octafluoroization three carbon, octafluoroization four carbon, hexafluoroization four carbon or hexafluoroization two carbon or the various combination of multiple gases.
The etching gas that described centre stops being adopted in layer etching technics is the mist of difluoromethane, oxygen and nitrogen.
The flow of described difluoromethane is: 30～50 standard ml/min;
The flow of described oxygen is: 40～60 standard ml/min;
The flow of described nitrogen is: 15～30 standard ml/min.
The thickness of described oxidation insulating layer is 16500
～17500
Described each middle thickness that stops layer equating; The thickness of a described N oxidation insulating layer equates.
Described first thickness that stops layer is 1100
～1300
The thickness that described centre stops layer is 400
～600
The lithographic method of a kind of through hole and metal wire groove is provided among the present invention in summary.In the lithographic method of described through hole and metal wire groove, since on through hole after the planarization and through hole dielectric layer successively alternating deposit N stop layer and N oxidation insulating layer, and in follow-up processing procedure, described each oxidation insulating layer is carried out main etching technology respectively, the described layer that stops in the middle of each is carried out over etching technology and centre respectively and stops a layer etching technics, stop layer to first at last and carry out over etching technology, thereby can in above-mentioned etching process, progressively dwindle distance between etching depth the best part and the etching depth least part, make and last one deck is being stopped layer (promptly first stops layer) when carrying out over etching technology, both can remove the oxidation insulating layer of required etching fully, again can so that to last one deck stop the layer etching depth be no more than corresponding numerical value, thereby avoid effectively removing fully required etching oxidation insulating layer phenomenon and first etching depth that stops layer being surpassed the maximum that is allowed or wears the phenomenon that stops layer quarter, improve the electric property of formed semiconductor device.
Description of drawings
Fig. 1 is the flow chart of the lithographic method of through hole of the prior art and metal wire groove.
Fig. 2 a～Fig. 2 e is the schematic diagram of the lithographic method of through hole and metal wire groove in the prior art.
Fig. 3 is the schematic diagram of main etching technology of the prior art.
Fig. 4 is the schematic diagram of residual oxidation insulating layer of the prior art.
Fig. 5 is the schematic diagram of wearing phenomenon quarter that stops layer of the prior art.
Fig. 6 is the flow chart of the lithographic method of through hole among the present invention and metal wire groove.
Fig. 7 a～Fig. 7 d is the schematic diagram of the lithographic method of through hole among the present invention and metal wire groove.
Fig. 8 is the schematic diagram of the main etching technology of second oxidation insulating layer among the present invention.
Fig. 9 is the schematic diagram that second centre that stops layer among the present invention stops layer etching technics.
Figure 10 is the schematic diagram of the main etching technology of first oxidation insulating layer among the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention express clearlyer, the present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Fig. 6 is the flow chart of the lithographic method of through hole among the present invention and metal wire groove.Fig. 7 a～Fig. 7 d is the schematic diagram of the lithographic method of through hole among the present invention and metal wire groove.Shown in Fig. 6, Fig. 7 a～Fig. 7 d, the lithographic method of through hole that is provided among the present invention and metal wire groove comprises step as described below:
Shown in Fig. 7 a, in this step, at first the deposition via etch stops layer 201 and through hole dielectric layer 202 on Semiconductor substrate 200; Then, utilize photoetching technique on through hole dielectric layer 202, to define the opening figure of through hole, form through hole 210 by etching again; Then, for the through hole dielectric layer 202 of the sidewall of the copper metal that makes follow-up filling and through hole 210 has good adhesiveness, simultaneously in order to prevent that the copper metal from spreading in through hole dielectric layer 202, can deposit an adhesion barrier layer 203 earlier before filling the copper metal, this adhesion barrier layer 203 generally can be made of the Ta/TaN composition; After this, on adhesion barrier layer 203, form the crystal seed layer 204 of copper, re-use ECP technology and in through hole 210, fill the copper metal, form copper layer 205.
Above-mentioned bonding barrier layer 203 is for strengthening Semiconductor substrate or lower metal material and the interior transition zone that is connected storeroom connection effect of through hole, and the main component on this bonding barrier layer 203 can be materials such as titanium (Ti), nickel (Ni) or aluminium copper.The main component of through hole dielectric layer 202 can be a kind of material in phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), fluorine silex glass (FSG) and the black diamond materials such as (BD) or the combination in any of multiple material.
Shown in Fig. 7 b, in this step, can carry out planarization, with unnecessary copper layer 205, crystal seed layer 204 and the adhesion barrier layer 203 on the surface of removing through hole dielectric layer 202 by CMP technology.
In this step, will be on through hole after the planarization and through hole dielectric layer successively alternating deposit N stop layer and N oxidation insulating layer, wherein, N is the natural number more than or equal to 2.For example, can on through hole after the planarization and through hole dielectric layer, deposit first earlier and stop layer, stop deposition first oxidation insulating layer on the layer first then; Then deposit second and stop layer, stop deposition second oxidation insulating layer on the layer second again; Deposit N and stop layer, stop deposition N oxidation insulating layer on the layer at N more at last.Hence one can see that, last deposit still for oxidation insulating layer.In addition, above-mentioned first thickness that stops layer equating with the layer thickness that stops of the prior art, and the above-mentioned N that deposits gross thickness that stops layer and N oxidation insulating layer is more than or equal to one that is deposited in prior art gross thickness that stops a layer and an oxidation insulating layer.Wherein, for the convenience of narrating, can stop individual other the layer (promptly second stop layer～N stop layer) that stops of layer (N-1) and all be referred to as middle stop layer (MSL, a MiddleStop Layer) except that described first above-mentioned.Therefore, above-mentioned N stops layer and comprises: be deposited on first on through hole after the planarization and the through hole dielectric layer stop layer and (N-1) the individual centre that is deposited between each oxidation insulating layer stop layer.Therefore, in an embodiment of the present invention, can set in advance the value of N according to practical situations, and preestablish described each stop the layer (comprise first stop the layer and each in the middle of stop the layer) thickness and the thickness of each oxidation insulating layer.The thickness that stops layer in the middle of each can be equal to each other, also can be unequal; The thickness of a described N oxidation insulating layer can be equal to each other, also can be unequal.
With N=2 is example, shown in Fig. 7 c, in this step, can deposit first earlier on through hole after the planarization and through hole dielectric layer and stop layer 7061, and then deposit first oxidation insulating layer 7071; Then deposit second and stop layer 7062, stop deposition second oxidation insulating layer 7072 on the layer 7062 second again.Be respectively T1, T2, Y1 and Y2 if described first stops layer 7061, second thickness that stops layer 7062, first oxidation insulating layer 7071 and second oxidation insulating layer 7072; If the thickness that stops layer 206 of the prior art shown in Fig. 2 (c) is T, the thickness of oxidation insulating layer 207 is Y, then in an embodiment of the present invention, above-mentioned T1 can be less than or equal to T, T2 is then less than T, Y1 and Y2 are then all less than Y, and T1, T2, Y1 and Y2 should satisfy condition: T1+T2+Y1+Y2 〉=T+Y.Further, in specific embodiments of the invention, also can preestablish the value of above-mentioned T1, T2, Y1 and Y2 according to practical situations.For example, can preestablish: Y1=Y2, and the span of Y1 and Y2 is: 16500
～17500
, the span of T1 is: 1100
～1300
, the span of T2 is: 400
～600
In addition, in specific embodiments of the invention, above-mentioned Y1 and Y2 also can be unequal, for example, and Y2＞Y1 or Y1＞Y2.
In addition, in an embodiment of the present invention, the value of above-mentioned N can also be 3,4,5 ... Deng greater than 2 natural number, and embodiment and execution mode during above-mentioned N=2 of N when getting other value is similar, does not repeat them here.
In addition, above-mentioned first main component that stops layer and stop layer in the middle of each can be SiN, and the main component of above-mentioned each oxidation insulating layer can be non-doped silicon glass (USG, Undoped SilicateGlass).
Shown in Fig. 7 c, in this step, will go up at the oxidation insulating layer (i.e. N oxidation insulating layer) of above-mentioned last deposition and continue deposition insulation antireflecting coating 208 and PR layer 209.Then, can carry out patterned process, after promptly PR layer 209 being exposed and developing, obtain the PR layer 209 of patterning according to the figure of required transfer printing to above-mentioned PR layer 209.
Step 605 is a mask with the photoresist layer of patterning, etching insulation antireflecting coating.
Shown in Fig. 7 c, in this step, will be mask with the photoresist layer 209 of above-mentioned patterning, insulation antireflecting coating 208 is carried out etching, to form follow-up etching window of carrying out main etching.
In this step, after finishing above-mentioned etching, will earlier carry out main etching technology, again N be stopped that layer carries out over etching technology and the centre stops a layer etching technics the N oxidation insulating layer to the insulation antireflecting coating; Then (N-1) oxidation insulating layer is carried out main etching technology, again (N-1) stopped layer and carry out over etching technology and the centre stops a layer etching technics; Then first oxidation insulating layer is carried out main etching technology, stop layer to first more at last and carry out over etching technology, to form required super thick metal wire groove.
In an embodiment of the present invention, can carry out main etching technology to each above-mentioned oxidation insulating layer by etching mode commonly used (for example, Chang Yong dry etching etc.); The etching gas that is adopted is generally the fluorocarbons chemical gas, for example, and octafluoroization three carbon (C
3F
8), octafluoroization four carbon (C
4F
8), hexafluoroization four carbon (C
4F
6) or hexafluoroization two carbon (C
2F
6) in a kind of gas or the various combination of multiple gases, can also use fluoroform (CHF
3).In specific embodiments of the invention, employed etching gas is generally hexafluoroization two carbon (C
2F
6) and the mist of corresponding assist gas (for example, oxygen, carbon monoxide etc.).
In addition, also can stop layer (comprise stop in the middle of each layer and first stop layer) to above-mentioned each and carry out over etching technology by etching mode commonly used (for example, Chang Yong dry etching etc.).The etching gas that is adopted can be: C
3F
8, C
4F
8, C
4F
6Or C
2F
6In a kind of gas or the various combination of multiple gases, also can use CHF
3In specific embodiments of the invention, employed etching gas is generally C
2F
6And the mist of corresponding assist gas (for example, oxygen, argon gas etc.).At this moment, the selection ratio of Oxide/SiN was generally 2: 1～6: 1, therefore, in above-mentioned over etching technology, with make the part of etching depth minimum to the etching speed of oxidation insulating layer greater than the etching depth the best part to stopping the etching speed of layer, thereby can dwindle distance between the part of etching depth the best part and etching depth minimum.
In addition, also can stop a layer etching technics to stopping layer carrying out the centre in the middle of above-mentioned each by etching mode commonly used (for example, Chang Yong dry etching etc.).The etching gas that is adopted can be: difluoromethane (CH
2F
2), oxygen (O
2) and nitrogen (N
2) mist.Wherein, CH
2F
2Flow be: 30～50 standard ml/min (sccm, Standard Cubic Centimeter per Minute), O
2Flow be: 40～60sccm, N
2Flow be: 15～30sccm.At this moment, the selection of Oxide/SiN ratio was generally 1: 2～1: 4.Therefore, stop in layer etching technics in above-mentioned centre, to make etching speed that the part of etching depth minimum stops layer to the centre, thereby can further dwindle the distance between the part of etching depth the best part and etching depth minimum greater than the etching speed of etching depth the best part to oxidation insulating layer.
Wherein, when stating main etching technology in the use and carrying out etching, contact when stopping layer (stop in the middle of comprising layer and first stop layer) accordingly, will stop main etching technology automatically and switch to over etching technology when the etching depth the best part rigidly connects; And when using over etching technology to carry out etching, when the part of etching depth minimum rigidly connects when contacting corresponding centre and stopping layer, will stop over etching technology automatically and switch in the middle of stop a layer etching technics; And when stopping layer etching technics in use and carrying out etching, finished when the centre stopped the etching of layer when the most shallow part of etching depth, stop layer etching technics in the middle of will stopping automatically and switch to the main etching technology of next round; The rest may be inferred, until finish to first stop the layer over etching technology, form required super thick metal wire groove.
Because the above-mentioned thickness that deposits the thickness of each oxidation insulating layer much smaller than oxidation insulating layer of the prior art, therefore, in each main etching technology, when rigidly connecting to contact, the etching depth the best part stops layer, thereby when switching to over etching technology, the part of etching depth minimum from stop the layer distance also much smaller than distance A of the prior art.Therefore, as long as each suitable middle thickness that stops layer being set, can be under the situation of the selection ratio that uses less Oxide/SiN, dwindle the distance between the part of above-mentioned etching depth the best part and etching depth minimum by follow-up over etching technology, and stop further to dwindle in layer etching technics distance between the part of above-mentioned etching depth the best part and etching depth minimum in follow-up centre.Therefore, in an embodiment of the present invention, when stopping layer when beginning to carry out over etching technology to first, the part of etching depth minimum from first distance that stops layer also much smaller than distance A of the prior art, even thereby make and compare S in the selection of using less Oxide/SiN
0(for example, S
0=6: under the situation 1), still can guarantee in the oxidation insulating layer of removing required etching fully, the first maximum etching depth that stops layer being no more than this first stopping the layer depth capacity B that can be etched, thereby can avoid effectively removing fully required etching oxidation insulating layer phenomenon and first etching depth that stops layer being surpassed the maximum B that is allowed or wears the phenomenon that stops layer quarter, improve the electric property of formed semiconductor device, also be convenient to carry out next step treatment process simultaneously.
With N=2 is example, shown in Fig. 7 d, will earlier carry out main etching technology to second oxidation insulating layer 7072, stops to second that layer 7062 carries out over etching technology and the centre stops a layer etching technics again; Then first oxide isolated is carried out main etching technology for 7071 layers, stop layer 7061 to first more at last and carry out over etching technology.Wherein, if establish Y1=Y2, and the span of Y1 and Y2 is: 16500
～17500
, the span of T1 is: 1100
～1300
, then touching second when stopping layer when etching depth the best part in the main etching technology of second oxidation insulating layer, the part of etching depth minimum will be 2500 from second distance A 2 that stops layer
About, as shown in Figure 8.At this moment, if follow-up second selection that stops the Oxide/SiN in the over etching technology of layer is set to 6: 1 than S2, then only need described second thickness that stops layer being set to 400
～600
, can in the over etching technical process, dwindle the distance between the part of above-mentioned etching depth the best part and etching depth minimum greatly; And if the selection ratio that second centre that stops layer being stopped the Oxide/SiN in layer etching technics is set to 1: 4, then also can stop further to dwindle in layer etching technics distance between the part of above-mentioned etching depth the best part and etching depth minimum in the centre, even can make this distance become 0, as shown in Figure 9.Therefore, in the main etching technology to first oxidation insulating layer, when the etching depth the best part touches first when stopping layer, the part of etching depth minimum will be much smaller than 5000 from first distance A 1 that stops layer
, generally will be 2500
About, as shown in figure 10.Therefore, even follow-up first selection that stops the Oxide/SiN in the over etching technology of layer (for example is set to bigger value than S2,6: 1), still can guarantee in the oxidation insulating layer of removing required etching fully, the first maximum etching depth that stops layer being no more than this first stopping the layer depth capacity B that can be etched or can not carve and wear first phenomenon that stops layer.
In addition, in an embodiment of the present invention, when the value of N be other greater than 2 natural number the time, can be according to actual application environment, the thickness that above-mentioned centre is stopped layer being provided with forr a short time, also can be provided with forr a short time (for example, 2 or 4) to each selection ratio of Oxide/SiN that stops in the over etching technology of layer, thereby can adapt to various practical situations above-mentioned.Concrete method to set up does not repeat them here.
In summary, surpass the maximum that is allowed even carve and wear the problem that stops layer at the problem of the existing oxidation insulating layer that can't remove required etching fully in the prior art and to the etching depth that stops layer, proposed the lithographic method of above-mentioned through hole and metal wire groove in an embodiment of the present invention.In the lithographic method of this through hole and metal wire groove, by being set, one or more centres stop layer in original oxidation insulating layer, and setting will be set thickness and the position that set centre stops layer as required, thereby can in the etching process of through hole and metal wire groove, progressively dwindle the distance between etching depth the best part and the etching depth least part, make and last one deck is being stopped layer (be above-mentioned first stop layer) when carrying out over etching technology, both can remove the oxidation insulating layer of required etching fully, again can so that to last one deck stop the layer etching depth be no more than the maximum that is allowed, thereby avoid effectively removing fully required etching oxidation insulating layer phenomenon and first etching depth that stops layer being surpassed the maximum that is allowed or wears the phenomenon that stops layer quarter, improved the electric property of formed semiconductor device.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the lithographic method of through hole and metal wire groove, this method comprises:
The deposition via etch stops layer and through hole dielectric layer on Semiconductor substrate, forms through hole by etching, and uses the electrochemistry depositing process to fill the copper metal in through hole, forms the copper layer; Carry out planarization by CMP (Chemical Mechanical Polishing) process;
Alternating deposit N stops layer and N oxidation insulating layer successively on through hole after the planarization and through hole dielectric layer; Described N stops layer and comprises: be deposited on first on through hole after the planarization and the through hole dielectric layer stop layer and (N-1) the individual centre that is deposited between each oxidation insulating layer stop layer;
In the end deposition insulation antireflecting coating and photoresist layer on Chen Ji the oxidation insulating layer carry out patterned process to photoresist layer; Photoresist layer with patterning is a mask, etching insulation antireflecting coating;
Described each oxidation insulating layer is carried out main etching technology respectively, the described layer that stops in the middle of each is carried out over etching technology and centre respectively and stops a layer etching technics, stop layer to first at last and carry out over etching technology, form super thick metal wire groove.
2. method according to claim 1 is characterized in that, this method also further comprises:
Preestablish described each and stop the thickness of layer and the thickness of each oxidation insulating layer.
3. method according to claim 1 and 2 is characterized in that:
The etching gas that is adopted in the described main etching technology is the fluorocarbons chemical gas.
4. method according to claim 3 is characterized in that, described fluorocarbons chemical gas is:
A kind of gas in octafluoroization three carbon, octafluoroization four carbon, hexafluoroization four carbon or hexafluoroization two carbon or the various combination of multiple gases.
5. method according to claim 1 and 2 is characterized in that:
The etching gas that described centre stops being adopted in layer etching technics is the mist of difluoromethane, oxygen and nitrogen.
6. method according to claim 5 is characterized in that:
The flow of described difluoromethane is: 30～50 standard ml/min;
The flow of described oxygen is: 40～60 standard ml/min;
The flow of described nitrogen is: 15～30 standard ml/min.
7. method according to claim 1 and 2 is characterized in that:
The thickness of described oxidation insulating layer is
8. method according to claim 1 and 2 is characterized in that:
Described each middle thickness that stops layer equating; The thickness of a described N oxidation insulating layer equates.
9. method according to claim 8 is characterized in that:
Described first thickness that stops layer is
The thickness that described centre stops layer is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022722 CN102122634B (en) | 2010-01-08 | 2010-01-08 | Method for etching through hole and metal wire trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022722 CN102122634B (en) | 2010-01-08 | 2010-01-08 | Method for etching through hole and metal wire trench |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102122634A true CN102122634A (en) | 2011-07-13 |
| CN102122634B CN102122634B (en) | 2013-04-24 |
Family
ID=44251152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010022722 Active CN102122634B (en) | 2010-01-08 | 2010-01-08 | Method for etching through hole and metal wire trench |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102122634B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199058A (en) * | 2013-04-19 | 2013-07-10 | 中微半导体设备(上海)有限公司 | Method for etching through hole |
| US10510558B2 (en) | 2016-05-27 | 2019-12-17 | Boe Technology Group Co., Ltd. | Electronic device, thin film transistor, array substrate and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004530287A (en) * | 2000-12-26 | 2004-09-30 | ハネウェル・インターナショナル・インコーポレーテッド | Method for eliminating the reaction between photoresist and OSG |
| US20090061619A1 (en) * | 2007-08-31 | 2009-03-05 | Sang-Il Hwang | Method of fabricating metal line |
| CN101459125A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
-
2010
- 2010-01-08 CN CN 201010022722 patent/CN102122634B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004530287A (en) * | 2000-12-26 | 2004-09-30 | ハネウェル・インターナショナル・インコーポレーテッド | Method for eliminating the reaction between photoresist and OSG |
| US20090061619A1 (en) * | 2007-08-31 | 2009-03-05 | Sang-Il Hwang | Method of fabricating metal line |
| CN101459125A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199058A (en) * | 2013-04-19 | 2013-07-10 | 中微半导体设备(上海)有限公司 | Method for etching through hole |
| CN103199058B (en) * | 2013-04-19 | 2015-04-08 | 中微半导体设备(上海)有限公司 | Method for etching through hole |
| US10510558B2 (en) | 2016-05-27 | 2019-12-17 | Boe Technology Group Co., Ltd. | Electronic device, thin film transistor, array substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102122634B (en) | 2013-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW441015B (en) | Dual-damascene interconnect structures and methods for fabricating same | |
| US6083822A (en) | Fabrication process for copper structures | |
| TW437040B (en) | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics | |
| KR20050027133A (en) | Semiconductor device manufacturing method | |
| TW201735254A (en) | Semiconductor structure and manufacturing method thereof | |
| TW201322334A (en) | Method for forming air gap interconnection structure | |
| KR101842903B1 (en) | Method for forming air gap interconnect structure | |
| EP1107308A1 (en) | Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer | |
| TW200411336A (en) | Method for fabricating semiconductor device using ArF photolithography capable of protecting tapered profile of hard mask | |
| TW567530B (en) | Manufacturing method semiconductor integrated circuit including simultaneous formation of via hole reaching metal wiring and concave groove in interlayer film and semiconductor integrated circuit manufactured with the manufacturing method | |
| TWI251898B (en) | Damascene process for fabricating interconnect layers in an integrated circuit | |
| KR100466310B1 (en) | Method for manufacturing Metal-Insulator-Metal capacitor | |
| CN102122634B (en) | Method for etching through hole and metal wire trench | |
| CN101192513A (en) | Metal-insulator-metal capacitor and its manufacture process | |
| CN104851835B (en) | Metal interconnection structure and forming method thereof | |
| CN102034733A (en) | Interconnecting structure and forming method thereof | |
| CN102339790A (en) | Manufacture method of semiconductor device | |
| US6294471B1 (en) | Method of eliminating dishing effect in polishing of dielectric film | |
| CN102044471A (en) | Interconnecting structure and forming method thereof | |
| CN102969270A (en) | Semiconductor device and production method thereof | |
| CN1266748C (en) | Etching process for shaping semiconductor embedded structure | |
| JP2004031616A (en) | Polishing slurry, polishing process and method for manufacturing semiconductor device | |
| CN102005409A (en) | Preparation method of dual damascene structure | |
| KR100371835B1 (en) | Method for forming a line of semiconductor device | |
| CN106971973B (en) | Semiconductor device, manufacturing method thereof and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121122 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121122 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |