CN102122634B - Method for etching through hole and metal wire trench - Google Patents
Method for etching through hole and metal wire trench Download PDFInfo
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- CN102122634B CN102122634B CN 201010022722 CN201010022722A CN102122634B CN 102122634 B CN102122634 B CN 102122634B CN 201010022722 CN201010022722 CN 201010022722 CN 201010022722 A CN201010022722 A CN 201010022722A CN 102122634 B CN102122634 B CN 102122634B
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Abstract
The invention discloses a method for etching a through hole and a metal wire trench. The method comprises the following steps: depositing a through hole etching stop layer and a through hole dielectric layer on a semiconductor substrate, forming the through hole through etching, and filling copper in the through hole by utilizing an ECP (electro-chemical plating) process so as to form a copper layer; carrying out planarization; alternately depositing N stop layers and N oxide dielectric layers on the planarized through hole and through hole dielectric layer; depositing a dielectric antireflective coating (DARC) and a PR (photoresist) layer, and patterning the PR layer; taking the patterned PR layer as a mask to etch the DARC; and respectively carrying out a main etch (ME) process on the oxide dielectric layers, respectively carrying out an over etch (OE) process and a middle stop layer etch process on the middle stop layers, and finally carrying out the OE process on the first stop layer so as to form the ultra-thick metal wire trench. By utilizing the method, the phenomena that the oxide dielectric layers can not be fully eliminated, the etching depth in the stop layers exceeds the maximum permissible value and even the stop layers are punched can be prevented.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor components and devices, refer in particular to the lithographic method of a kind of through hole and metal wire trench.
Background technology
Through hole has important effect as the passage that is connected between multiple layer metal inter-level interconnects and device active region and the external circuitry in device architecture forms.In order to guarantee the stability of device work, require the through hole behind the filled conductive material to have good conductive characteristic, namely resistance is the smaller the better, and this is so that become extremely important to the strict control of via etch process.
Along with the dense degree of device and the complexity of technique constantly increase, via etch process is had higher requirement.Deep-submicron size development along with integrated circuit, characteristic size (CD) diminishes gradually, after semiconductor fabrication process entered 65nm and even 45nm node technique, for super thick metal interconnecting wires and via process thereof, lithographic method adopted two stage lithographic methods mostly.
Fig. 1 is the flow chart of the lithographic method of through hole of the prior art and metal wire trench.Fig. 2 a～Fig. 2 e is the schematic diagram of the lithographic method of through hole and metal wire trench in the prior art.Shown in Fig. 1, Fig. 2 a～Fig. 2 e, the lithographic method of through hole of the prior art and metal wire trench comprises step as described below:
Shown in Fig. 2 a, in this step, at first on Semiconductor substrate 200, deposit successively via etch stop-layer 201 and through hole dielectric layer 202; Then, utilize photoetching technique to define the opening figure of through hole at through hole dielectric layer 202, form through hole 210 by etching again; Then, for the through hole dielectric layer 202 of the sidewall of the copper metal that makes follow-up filling and through hole 210 has good adhesiveness, simultaneously in order to prevent that the copper metal is to the 202 interior diffusions of through hole dielectric layer, can deposit first an adhesion barrier layer 203 before filling the copper metal, this adhesion barrier layer 203 generally can be made of tantalum or tantalum nitride (Ta/TaN) composition; After this, the crystal seed layer 204 at adhesion barrier layer 203 formation copper re-uses ECP technique at through hole 210 interior filling copper metals, forms copper layer 205.
Shown in Fig. 2 b, in this step, can carry out planarization by CMP technique, with unnecessary copper layer 205, crystal seed layer 204 and the adhesion barrier layer 203 on the surface of removing through hole dielectric layer 202.
Shown in Fig. 2 c, in this step, can on the through hole after the planarization and through hole dielectric layer, deposit successively stop-layer (Stop Layer) 206, oxidation insulating layer (Oxide Dielectric Layer) 207, insulation antireflecting coating (DARC, Dielectric Antireflective Coating) 208 and PR layer 209.Wherein, above-mentioned stop-layer, oxidation insulating layer and insulation antireflecting coating are generically and collectively referred to as super thick metal wire trench dielectric layer.Then, can carry out patterned process to above-mentioned photoresist layer 209, after namely according to the figure of required transfer printing photoresist layer 209 being exposed and developing, obtain the photoresist layer 209 of patterning.
In addition, the main component of above-mentioned stop-layer 206 can be a kind of or its combination in any in the materials such as silicon nitride (SiN), carborundum (SiC), silicon oxide carbide (SiOC) or carbonitride of silicium (SiNC), is SiN generally speaking; The main component of above-mentioned oxidation insulating layer 207 can be non-doped silicon glass (USG, Undoped Silicate Glass); Above-mentioned insulation antireflecting coating 208 is as light-absorption layer, and its main component is generally SiON.The thickness of above-mentioned stop-layer 206 be generally 1200 dusts (
), the thickness of oxidation insulating layer 207 is generally 34000
, the thickness of insulation antireflecting coating 208 is generally 600
Shown in Fig. 2 c, in this step, will take the photoresist layer 209 of above-mentioned patterning as mask, carry out etching to insulation antireflecting coating 208, to form follow-up etching window of carrying out main etching.
Shown in Fig. 2 d, in this step, after finishing above-mentioned etching to the insulation antireflecting coating, will carry out main etching technique, namely by etching mode commonly used (dry etching of for example, commonly using etc.) above-mentioned oxidation insulating layer 207 is carried out etching.
When by above-mentioned main etch process oxidation insulating layer 207 being carried out etching, in order to guarantee the complete etching to oxidation insulating layer 207, to carry out over etching technique to stop-layer 206, namely when using above-mentioned main etching technique to etch into stop-layer, to stop main etching technique, and use over etching technique that stop-layer 206 is carried out the etching of certain depth, and be completely removed with the oxidation insulating layer 207 that guarantees required etching, also need keep simultaneously certain thickness stop-layer 206.Shown in Fig. 2 e.
After finishing above-mentioned steps 106, can form required super thick metal wire trench.And in follow-up technique, can in above-mentioned formed super thick metal wire trench, fill corresponding metal, thereby form required super thick metal wire.
Above-described step is the execution mode under the perfect condition.And in practical situations, because the restriction of semiconductor technology precision, when carrying out main etching technique, be difficult to guarantee the average etching on the etching depth direction, thereby so that in the time will finishing main etching technique, the etching depth at each position is not identical in the oxidation insulating layer 207 that is etched, and has a certain distance.Therefore, when the etching depth the best part had touched stop-layer in the main etching technique, the part of etching depth minimum also had certain distance from stop-layer, as shown in Figure 3.At this moment, because the etching depth the best part has touched stop-layer, therefore need to switch to etch process.In main etching technique, the material of required etching is mainly the oxide (Oxide) in the oxidation insulating layer 207, and in over etching technique, the material of required etching is mainly the silicon nitride (SiN) in the stop-layer 206.Therefore, the selection of employed Oxide/SiN is more not identical than (namely to the etching speed of Oxide and ratio to the etching speed of SiN) in main etching technique and over etching technique.
As shown in Figure 3, establish when the etching depth the best part has contacted stop-layer in the main etching technique, the part of etching depth minimum is A from the distance of stop-layer; And in over etching technique, because stop-layer need to guarantee certain loss and residual, therefore in over etching technique, the depth capacity B that a stop-layer can be etched must be set.Hence one can see that, and for the degree of depth that is etched at stop-layer reaches the oxidation insulating layer 207 of removing required etching before the B fully, the selection of the Oxide/SiN in over etching technique then must satisfy condition than S: S 〉=A/B.
In the prior art, because the restriction of semiconductor technology precision, and the thickness of oxidation insulating layer 207 is very large, for example, be generally 33000～35000 dusts (
), therefore the minimum value of above-mentioned A is generally 5000
, and in order to wear (Punch Through) phenomenon the quarter that prevents stop-layer, the maximum of general B is set to 400 in the prior art
, so the selection of required Oxide/SiN must could be satisfied technological requirement more than or equal to 12.5: 1 than S in the over etching technique.But in the prior art, the maximum of the S that can reach in the over etching technique only is 6: 1.Therefore, in the over etching technique in the prior art, be no more than B if guarantee the maximum etch degree of depth of stop-layer, then can so that the required removal oxidation insulating layer of part not by complete etching, thereby cause the residual of oxidation insulating layer, follow-up technique is caused adverse influence, as shown in Figure 4; And if guarantee to remove fully the oxidation insulating layer of required removal, then can occur the etching depth of stop-layer is surpassed the maximum B that allows, even the quarter that stop-layer occurs wear phenomenon, as shown in Figure 5, thereby the electric property of formed semiconductor device is caused great adverse effect.
Summary of the invention
In view of this, the invention provides the lithographic method of a kind of through hole and metal wire trench, thus avoid removing fully required etching oxidation insulating layer phenomenon and the etching depth of stop-layer surpassed the maximum that allows or the phenomenon of wearing stop-layer quarter.
For achieving the above object, the technical scheme among the present invention is achieved in that
The lithographic method of a kind of through hole and metal wire trench, the method comprises:
At Semiconductor substrate deposition via etch stop-layer and through hole dielectric layer, form through hole by etching, and use the electrochemistry depositing process in through hole, to fill the copper metal, form the copper layer; Carry out planarization by CMP (Chemical Mechanical Polishing) process;
Successively alternating deposit N stop-layer and N oxidation insulating layer on the through hole after the planarization and through hole dielectric layer; A described N stop-layer comprises: be deposited on through hole after the planarization and the first stop-layer on the through hole dielectric layer and (N-1) the individual middle stop-layer that is deposited between each oxidation insulating layer;
In the end deposition insulation antireflecting coating and photoresist layer on the oxidation insulating layer of deposition carry out patterned process to photoresist layer; Take the photoresist layer of patterning as mask, etching insulation antireflecting coating;
Described each oxidation insulating layer is carried out respectively main etching technique, described each middle stop-layer is carried out respectively over etching technique and middle stop-layer etching technics, at last the first stop-layer is carried out over etching technique, form super thick metal wire trench.
The method also further comprises: preset the thickness of described each stop-layer and the thickness of each oxidation insulating layer.
The etching gas that adopts in the described main etching technique is the fluorocarbons chemical gas.
Described fluorocarbons chemical gas is:
A kind of gas in C3F8, octafluoroization four carbon, hexafluoroization four carbon or hexafluoroization two carbon or the various combination of multiple gases.
The etching gas that adopts in the stop-layer etching technics in the middle of described is the mist of difluoromethane, oxygen and nitrogen.
The flow of described difluoromethane is: 30～50 standard ml/min;
The flow of described oxygen is: 40～60 standard ml/min;
The flow of described nitrogen is: 15～30 standard ml/min.
The thickness of described oxidation insulating layer is 16500
～17500
The thickness of described each middle stop-layer equates; The thickness of a described N oxidation insulating layer equates.
The thickness of described the first stop-layer is 1100
～1300
The thickness of stop-layer is 400 in the middle of described
～600
The lithographic method of a kind of through hole and metal wire trench is provided among the present invention in summary.In the lithographic method of described through hole and metal wire trench, since on the through hole after the planarization and through hole dielectric layer successively alternating deposit N stop-layer and N oxidation insulating layer, and in follow-up processing procedure, described each oxidation insulating layer is carried out respectively main etching technique, described each middle stop-layer is carried out respectively over etching technique and middle stop-layer etching technics, at last the first stop-layer is carried out over etching technique, thereby can in above-mentioned etching process, progressively dwindle distance between etching depth the best part and the etching depth least part, so that to last one deck stop-layer (i.e. the first stop-layer) when carrying out over etching technique, both can remove the oxidation insulating layer of required etching fully, again can be so that the etching depth of last one deck stop-layer be no more than corresponding numerical value, thereby effectively avoid removing fully required etching oxidation insulating layer phenomenon and the etching depth of the first stop-layer surpassed the maximum that allows or the phenomenon of wearing stop-layer quarter, improve the electric property of formed semiconductor device.
Description of drawings
Fig. 1 is the flow chart of the lithographic method of through hole of the prior art and metal wire trench.
Fig. 2 a～Fig. 2 e is the schematic diagram of the lithographic method of through hole and metal wire trench in the prior art.
Fig. 3 is the schematic diagram of main etching technique of the prior art.
Fig. 4 is the schematic diagram of residual oxidation insulating layer of the prior art.
Fig. 5 is the schematic diagram of wearing phenomenon the quarter of stop-layer of the prior art.
Fig. 6 is the flow chart of the lithographic method of through hole among the present invention and metal wire trench.
Fig. 7 a～Fig. 7 d is the schematic diagram of the lithographic method of through hole and metal wire trench among the present invention.
Fig. 8 is the schematic diagram of the main etching technique of the second oxidation insulating layer among the present invention.
Fig. 9 is the schematic diagram of the middle stop-layer etching technics of the second stop-layer among the present invention.
Figure 10 is the schematic diagram of the main etching technique of the first oxidation insulating layer among the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention express clearlyer, the present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Fig. 6 is the flow chart of the lithographic method of through hole among the present invention and metal wire trench.Fig. 7 a～Fig. 7 d is the schematic diagram of the lithographic method of through hole and metal wire trench among the present invention.Shown in Fig. 6, Fig. 7 a～Fig. 7 d, the through hole that provides among the present invention and the lithographic method of metal wire trench comprise step as described below:
Step 601 at Semiconductor substrate deposition via etch stop-layer and through hole dielectric layer, forms through hole by etching, and uses ECP technique to fill the copper metal in through hole, forms the copper layer.
Shown in Fig. 7 a, in this step, at first at Semiconductor substrate 200 deposition via etch stop-layer 201 and through hole dielectric layers 202; Then, utilize photoetching technique to define the opening figure of through hole at through hole dielectric layer 202, form through hole 210 by etching again; Then, for the through hole dielectric layer 202 of the sidewall of the copper metal that makes follow-up filling and through hole 210 has good adhesiveness, simultaneously in order to prevent that the copper metal is to the 202 interior diffusions of through hole dielectric layer, can deposit first an adhesion barrier layer 203 before filling the copper metal, this adhesion barrier layer 203 generally can be made of the Ta/TaN composition; After this, the crystal seed layer 204 at adhesion barrier layer 203 formation copper re-uses ECP technique at through hole 210 interior filling copper metals, forms copper layer 205.
Above-mentioned bonding barrier layer 203 is for strengthening the transition zone that is connected effect between the interior connecting material of Semiconductor substrate or lower metal material and through hole, and the main component on this bonding barrier layer 203 can be the materials such as titanium (Ti), nickel (Ni) or aluminium copper.The main component of through hole dielectric layer 202 can be a kind of material in the materials such as phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), fluorine silex glass (FSG) and black diamond (BD) or the combination in any of multiple material.
Step 602 is carried out planarization by CMP technique.
Shown in Fig. 7 b, in this step, can carry out planarization by CMP technique, with unnecessary copper layer 205, crystal seed layer 204 and the adhesion barrier layer 203 on the surface of removing through hole dielectric layer 202.
Step 603, successively alternating deposit N stop-layer and N oxidation insulating layer on the through hole after the planarization and through hole dielectric layer.
In this step, will be on the through hole after the planarization and through hole dielectric layer successively alternating deposit N stop-layer and N oxidation insulating layer, wherein, N is the natural number more than or equal to 2.For example, then the through hole after planarization and through hole dielectric layer deposition the first stop-layer deposits the first oxidation insulating layer at the first stop-layer first; Then deposit the second stop-layer, again at the second stop-layer deposition the second oxidation insulating layer; Deposit the N stop-layer, at last again at N stop-layer deposition N oxidation insulating layer.Hence one can see that, last deposit still for oxidation insulating layer.In addition, the thickness of above-mentioned the first stop-layer equates with stop-layer thickness of the prior art, and the gross thickness of the above-mentioned N that a deposits stop-layer and N oxidation insulating layer is more than or equal to a stop-layer that deposits in the prior art and the gross thickness of an oxidation insulating layer.Wherein, for the convenience of narrating, stop-layer (MSL, MiddleStop Layer) in the middle of individual other the stop-layer (i.e. the second stop-layer～N stop-layer) of above-mentioned (N-1) except described the first stop-layer all can being referred to as.Therefore, an above-mentioned N stop-layer comprises: be deposited on through hole after the planarization and the first stop-layer on the through hole dielectric layer and (N-1) the individual middle stop-layer that is deposited between each oxidation insulating layer.Therefore, in an embodiment of the present invention, can set in advance the value of N according to practical situations, and preset the thickness of described each stop-layer (comprising the first stop-layer and stop-layer in the middle of each) and the thickness of each oxidation insulating layer.Thickness of stop-layer can be equal to each other in the middle of each, also can be unequal; The thickness of a described N oxidation insulating layer can be equal to each other, also can be unequal.
Take N=2 as example, shown in Fig. 7 c, in this step, the through hole after planarization and through hole dielectric layer deposit the first stop-layer 7061 first, and then deposit the first oxidation insulating layer 7071; Then deposit the second stop-layer 7062, again at the second stop-layer 7062 depositions the second oxidation insulating layer 7072.If the thickness of described the first stop-layer 7061, the second stop-layer 7062, the first oxidation insulating layer 7071 and the second oxidation insulating layer 7072 is respectively T1, T2, Y1 and Y2; If the thickness of the stop-layer of the prior art 206 shown in Fig. 2 (c) is T, the thickness of oxidation insulating layer 207 is Y, then in an embodiment of the present invention, above-mentioned T1 can be less than or equal to T, T2 is then less than T, Y1 and Y2 are then all less than Y, and T1, T2, Y1 and Y2 should satisfy condition: T1+T2+Y1+Y2 〉=T+Y.Further, in specific embodiments of the invention, also can according to practical situations, preset the value of above-mentioned T1, T2, Y1 and Y2.For example, can preset: Y1=Y2, and the span of Y1 and Y2 is: 16500
～17500
, the span of T1 is: 1100
～1300
, the span of T2 is: 400
～600
In addition, in specific embodiments of the invention, above-mentioned Y1 and Y2 also can be unequal, for example, and Y2＞Y1 or Y1＞Y2.
In addition, in an embodiment of the present invention, the value of above-mentioned N can also be 3,4,5 ... Deng greater than 2 natural number, and embodiment and execution mode during above-mentioned N=2 of N when getting other value is similar, does not repeat them here.
In addition, the main component of the first above-mentioned stop-layer and each middle stop-layer can be SiN, and the main component of above-mentioned each oxidation insulating layer can be non-doped silicon glass (USG, Undoped SilicateGlass).
Step 604, in the end deposition insulation antireflecting coating and PR layer on the oxidation insulating layer of deposition carry out patterned process to the PR layer.
Shown in Fig. 7 c, in this step, will continue at the oxidation insulating layer (i.e. N oxidation insulating layer) of above-mentioned last deposition deposition insulation antireflecting coating 208 and PR layer 209.Then, can carry out patterned process to above-mentioned PR layer 209, after namely according to the figure of required transfer printing PR layer 209 being exposed and developing, obtain the PR layer 209 of patterning.
Step 605, take the photoresist layer of patterning as mask, etching insulation antireflecting coating.
Shown in Fig. 7 c, in this step, will take the photoresist layer 209 of above-mentioned patterning as mask, carry out etching to insulation antireflecting coating 208, to form follow-up etching window of carrying out main etching.
Step 606, each above-mentioned oxidation insulating layer is carried out respectively main etching technique, each above-mentioned middle stop-layer is carried out respectively over etching technique and middle stop-layer etching technics, at last the first stop-layer is carried out over etching technique, form super thick metal wire trench.
In this step, after finishing above-mentioned etching to the insulation antireflecting coating, will carry out main etching technique to the N oxidation insulating layer first, again the N stop-layer be carried out over etching technique and middle stop-layer etching technics; Then (N-1) oxidation insulating layer is carried out main etching technique, again (N-1) stop-layer is carried out over etching technique and middle stop-layer etching technics; Then the first oxidation insulating layer is carried out main etching technique, again the first stop-layer is carried out over etching technique at last, to form required super thick metal wire trench.
In an embodiment of the present invention, can carry out main etching technique to each above-mentioned oxidation insulating layer by etching mode commonly used (dry etching of for example, commonly using etc.); The etching gas that adopts is generally the fluorocarbons chemical gas, for example, and C3F8 (C
3F
8), octafluoroization four carbon (C
4F
8), hexafluoroization four carbon (C
4F
6) or hexafluoroization two carbon (C
2F
6) in a kind of gas or the various combination of multiple gases, can also use fluoroform (CHF
3).In specific embodiments of the invention, employed etching gas is generally hexafluoroization two carbon (C
2F
6) and the mist of corresponding assist gas (for example, oxygen, carbon monoxide etc.).
In addition, also can carry out over etching technique to each above-mentioned stop-layer (comprising each middle stop-layer and the first stop-layer) by etching mode commonly used (dry etching of for example, commonly using etc.).The etching gas that adopts can be: C
3F
8, C
4F
8, C
4F
6Or C
2F
6In a kind of gas or the various combination of multiple gases, also can use CHF
3In specific embodiments of the invention, employed etching gas is generally C
2F
6And the mist of corresponding assist gas (for example, oxygen, argon gas etc.).At this moment, the selection ratio of Oxide/SiN is generally 2: 1～and 6: 1, therefore, in above-mentioned over etching technique, with so that the part of etching depth minimum to the etching speed of oxidation insulating layer greater than the etching speed of etching depth the best part to stop-layer, thereby can dwindle distance between the part of etching depth the best part and etching depth minimum.
In addition, also can carry out centre stop-layer etching technics to each above-mentioned middle stop-layer by etching mode commonly used (dry etching of for example, commonly using etc.).The etching gas that adopts can be: difluoromethane (CH
2F
2), oxygen (O
2) and nitrogen (N
2) mist.Wherein, CH
2F
2Flow be: 30～50 standard ml/min (sccm, Standard Cubic Centimeter per Minute), O
2Flow be: 40～60sccm, N
2Flow be: 15～30sccm.At this moment, the selection of Oxide/SiN ratio be generally 1: 2～1: 4.Therefore, in above-mentioned middle stop-layer etching technics, with so that the part of etching depth minimum to the etching speed of middle stop-layer greater than the etching speed of etching depth the best part to oxidation insulating layer, thereby can further dwindle distance between the part of etching depth the best part and etching depth minimum.
Wherein, when stating in the use main etching technique and carrying out etching, when the etching depth the best part rigidly connects when contacting corresponding stop-layer (stop-layer and the first stop-layer in the middle of comprising), will automatically stop main etching technique and switch to over etching technique; And when using over etching technique to carry out etching, when the part of etching depth minimum rigidly connect contact corresponding in the middle of during stop-layer, will automatically stop over etching technique and switch in the middle of the stop-layer etching technics; And when the stop-layer etching technics carries out etching in use, when the most shallow part of etching depth has been finished etching to middle stop-layer, stop-layer etching technics in the middle of will automatically stopping and switching to the main etching technique of next round; The rest may be inferred, until finish the over etching technique to the first stop-layer, forms required super thick metal wire trench.
Because the above-mentioned thickness of each oxidation insulating layer that deposits is much smaller than the thickness of oxidation insulating layer of the prior art, therefore, in each main etching technique, when rigidly connecting, the etching depth the best part contacts stop-layer, thereby when switching to over etching technique, the part of etching depth minimum from the distance of stop-layer also much smaller than distance A of the prior art.Therefore, as long as the thickness of each suitable middle stop-layer is set, can be in the situation of the selection ratio that uses less Oxide/SiN, dwindle the distance between the part of above-mentioned etching depth the best part and etching depth minimum by follow-up over etching technique, and in follow-up middle stop-layer etching technics, further dwindle the distance between the part of above-mentioned etching depth the best part and etching depth minimum.Therefore, in an embodiment of the present invention, when the first stop-layer is begun to carry out over etching technique, the part of etching depth minimum from the distance of the first stop-layer also much smaller than distance A of the prior art, even thereby so that compare S in the selection of using less Oxide/SiN
0(for example, S
0=6: in the situation 1), still can guarantee in the oxidation insulating layer of removing required etching fully, maximum etching depth to the first stop-layer is no more than the depth capacity B that this first stop-layer can be etched, thereby can effectively avoid removing fully required etching oxidation insulating layer phenomenon and the etching depth of the first stop-layer surpassed the maximum B that allows or the phenomenon of wearing stop-layer quarter, improve the electric property of formed semiconductor device, also be convenient to carry out simultaneously next step treatment process.
Take N=2 as example, shown in Fig. 7 d, will carry out main etching technique to the second oxidation insulating layer 7072 first, again the second stop-layer 7062 is carried out over etching technique and middle stop-layer etching technics; Then 7071 layers of the first oxide isolateds are carried out main etching technique, again the first stop-layer 7061 is carried out over etching technique at last.Wherein, if establish Y1=Y2, and the span of Y1 and Y2 is: 16500
～17500
, the span of T1 is: 1100
～1300
, then when the etching depth the best part touches the second stop-layer in the main etching technique of the second oxidation insulating layer, the part of etching depth minimum will be 2500 from the distance A 2 of the second stop-layer
About, as shown in Figure 8.At this moment, if the follow-up selection to the Oxide/SiN in the over etching technique of the second stop-layer is set to 6: 1 than S2, then only need the thickness of described the second stop-layer to be set to 400
～600
, can in the over etching technical process, greatly dwindle the distance between the part of above-mentioned etching depth the best part and etching depth minimum; And if the selection ratio of the Oxide/SiN in the middle stop-layer etching technics of the second stop-layer is set to 1: 4, then also can in middle stop-layer etching technics, further dwindle the distance between the part of above-mentioned etching depth the best part and etching depth minimum, even can be so that this distance becomes 0, as shown in Figure 9.Therefore, in the main etching technique to the first oxidation insulating layer, when the etching depth the best part touched the first stop-layer, the part of etching depth minimum will be much smaller than 5000 from the distance A 1 of the first stop-layer
, generally will be 2500
About, as shown in figure 10.Therefore, even the follow-up selection to the Oxide/SiN in the over etching technique of the first stop-layer (for example is set to larger value than S2,6: 1), still can guarantee in the oxidation insulating layer of removing required etching fully, the maximum etching depth of the first stop-layer is no more than the depth capacity B that this first stop-layer can be etched or can not carves the phenomenon of wearing the first stop-layer.
In addition, in an embodiment of the present invention, when the value of N be other greater than 2 natural number the time, can be according to actual application environment, arrange the thickness of stop-layer in the middle of above-mentioned less, also can arrange littlely above-mentioned selection ratio to the Oxide/SiN in the over etching technique of each stop-layer (for example, 2 or 4), thereby can adapt to various practical situations.Concrete method to set up does not repeat them here.
In summary, surpass the maximum that allows even carve the problem of wearing stop-layer for the problem of the existing oxidation insulating layer that can't remove required etching fully in the prior art and to the etching depth of stop-layer, proposed in an embodiment of the present invention above-mentioned through hole and the lithographic method of metal wire trench.In the lithographic method of this through hole and metal wire trench, by one or more middle stop-layers are set in original oxidation insulating layer, and thickness and the position will set set middle stop-layer be set as required, thereby can in the etching process of through hole and metal wire trench, progressively dwindle the distance between etching depth the best part and the etching depth least part, so that to last one deck stop-layer (being the first above-mentioned stop-layer) when carrying out over etching technique, both can remove the oxidation insulating layer of required etching fully, again can be so that the etching depth of last one deck stop-layer be no more than the maximum that allows, thereby effectively avoid removing fully required etching oxidation insulating layer phenomenon and the etching depth of the first stop-layer surpassed the maximum that allows or the phenomenon of wearing stop-layer quarter, improved the electric property of formed semiconductor device.
The above is preferred embodiment of the present invention only, is not for limiting protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the lithographic method of a through hole and metal wire trench, the method comprises:
At Semiconductor substrate deposition via etch stop-layer and through hole dielectric layer, form through hole by etching, and use the electrochemistry depositing process in through hole, to fill the copper metal, form the copper layer; Carry out planarization by CMP (Chemical Mechanical Polishing) process;
Successively alternating deposit N stop-layer and N oxidation insulating layer on the through hole after the planarization and through hole dielectric layer; A described N stop-layer comprises: be deposited on through hole after the planarization and the first stop-layer on the through hole dielectric layer and (N-1) the individual middle stop-layer that is deposited between each oxidation insulating layer;
In the end deposition insulation antireflecting coating and photoresist layer on the oxidation insulating layer of deposition carry out patterned process to photoresist layer; Take the photoresist layer of patterning as mask, etching insulation antireflecting coating;
Described each oxidation insulating layer is carried out respectively main etching technique, described each middle stop-layer is carried out respectively over etching technique and middle stop-layer etching technics, at last the first stop-layer is carried out over etching technique, form super thick metal wire trench.
2. method according to claim 1 is characterized in that, the method also further comprises:
Preset the thickness of described each stop-layer and the thickness of each oxidation insulating layer.
3. method according to claim 1 and 2 is characterized in that:
The etching gas that adopts in the described main etching technique is the fluorocarbons chemical gas.
4. method according to claim 3 is characterized in that, described fluorocarbons chemical gas is:
A kind of gas in C3F8, octafluoroization four carbon, hexafluoroization four carbon or hexafluoroization two carbon or the various combination of multiple gases.
5. method according to claim 1 and 2 is characterized in that:
The etching gas that adopts in the stop-layer etching technics in the middle of described is the mist of difluoromethane, oxygen and nitrogen.
6. method according to claim 5 is characterized in that:
The flow of described difluoromethane is: 30～50 standard ml/min;
The flow of described oxygen is: 40～60 standard ml/min;
The flow of described nitrogen is: 15～30 standard ml/min.
7. method according to claim 1 and 2 is characterized in that:
The thickness of described oxidation insulating layer is
8. method according to claim 1 and 2 is characterized in that:
The thickness of described each middle stop-layer equates; The thickness of a described N oxidation insulating layer equates.
9. method according to claim 8 is characterized in that:
The thickness of described the first stop-layer is
The thickness of stop-layer is in the middle of described
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| CN105914134B (en) | 2016-05-27 | 2017-07-04 | 京东方科技集团股份有限公司 | Electronic device, thin film transistor (TFT) and array base palte and preparation method thereof |
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