CN1266748C - Etching process for shaping semiconductor embedded structure - Google Patents
Etching process for shaping semiconductor embedded structure Download PDFInfo
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- CN1266748C CN1266748C CN 03107403 CN03107403A CN1266748C CN 1266748 C CN1266748 C CN 1266748C CN 03107403 CN03107403 CN 03107403 CN 03107403 A CN03107403 A CN 03107403A CN 1266748 C CN1266748 C CN 1266748C
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Abstract
The present invention discloses a new etching method for shaping a semiconductor embedded structure, which comprises the following steps: the residual polymers and oxidation materials remaining on the surface of a hard cover layer by a breaking process, wherein the breaking process uses gases containing a fluorocarbon rate (CFx-based), such as Ar/O2/CF4, to slightly brush the top surface of the hard cover layer to remove the residual polymers and the oxidation materials. Subsequently, an etching process is carried out to etch the hard cover layer until the hard cover layer has the thickness of a certain thickness of the dielectric layer. Finally, the other etching process is carried out to etch the hard cover layer and the dielectric layer, and an embedded structure is formed in the dielectric layer, wherein the etching process uses mixed gases containing chlorine, such as mixed gases containing Cl2 /O2.
Description
(1) technical field
The formation manufacturing process of the relevant a kind of semiconductor mosaic texture of the present invention, and particularly relevant a kind of engraving method that forms the semiconductor mosaic texture.
(2) background technology
Because the integration of the semiconductor element of integrated circuit increases day by day, when making the surface of chip can't provide enough areas to make required intraconnections, for complexed metal oxide semiconductor (Metal OxideSemiconductor; MOS) transistor dwindles the intraconnections demand that increased of back, and two-layer above metal level design is gradually the mode that becomes the essential employing of many integrated circuits institute just.In addition, in the manufacturing process of deep-sub-micrometer, because the integration of integrated circuit constantly increases, therefore adopt the comprehensive architecture of multiple layer inner connection line (Multi-levelinterconnects) at present mostly, and often with inner metal dielectric layer (Inter-Metal Dielectric; IMD) as the dielectric material of isolating each metal interconnecting.Wherein be used for connecting the lead of two metal layers up and down, on semi-conductor industry, be called interlayer hole connector (Via Plug).Usually the opening that forms in dielectric layer if expose base members in the intraconnections, then is called contact hole (contact hole).
The method of known manufacturing interlayer hole and intraconnections has two kinds, and wherein a kind of is that interlayer hole and intraconnections are finished in two steps suddenly, promptly forms dielectric layer above metal level, then forms photoresist layer (Photoresist above dielectric layer; PR), utilize etching technique to finish interlayer hole then, and utilize sedimentation in this interlayer hole deposits conductive material to finish the making of interlayer hole, deposit and form metal level afterwards, deposit inner metal dielectric layer at last again.Tradition forms the manufacturing process of metal interconnecting, is to make interlayer hole and metal interconnecting with twice development manufacturing process respectively, therefore the step that needs loaded down with trivial details deposition and pattern to form.Yet, the semiconductor fabrication process below deep-sub-micrometer (Sub-quarter micron), (Layout) is more complicated because of the multilayer interconnection layout, causes the pattern that is difficult to form metal interconnecting.Therefore, develop again at present another kind of inserted in link structures (Damascene interconnect structure).According to the characteristic on the manufacturing process, can be divided into single-layer type (Single type), doublet type (Dual type) and self-aligned type (Self-aligned type).Damascene (Damascene) is the irrigation canals and ditches that etch metal interconnecting earlier for a kind of in dielectric layer, insert metal again and be used as the method for intraconnections, this method can make that the manufacturing process of metal interconnecting need not etched step, introduces in the semiconductor element and copper etc. can be difficult for etched metal.Therefore making intraconnections in deep-sub-micrometer is the mode of the best with this method.
Traditional dual-metal inserting manufacturing process comprises two kinds of patterns and forms, and the one, dark pattern (Deeppatterns) forms, that is forms the formation (Via-first) of interlayer hole; Another is that shallow pattern forms (Shallowpatterns) or line pattern forms (Line patterns), that is forms the formation (Trench-first) of groove.For the manufacturing of deep-sub-micrometer element, in dual damascene process etching manufacturing process, use usually to have the photoresistance and the nonmetal/metal hard mask layer of lower etching photoresistance wavelength.In traditional dual pattern structure manufacturing technology, if directly using having, the slurry of cmp manufacturing process carries out polish process on the dielectric layer of low-k, then will in the cmp manufacturing process of this kind copper, produce the problem that a large amount of carbon residues is caused easily, therefore, being used to cover on the dielectric layer with low-k with the wherein dielectric layer as the grinding stop layer of cmp manufacturing process is to be silicon carbide layer, and it is the defective in order to prevent that the cmp manufacturing process from being produced mainly.The manufacturing process that forms with groove is an example, and it is to carry out the etching of part interlayer hole after hard mask layer pattern forms, and the structure of dual damascene then forms during groove is etched simultaneously.Yet owing to can produce oxidation on the surface of silicon carbide layer, especially true in the stack structure of two hard mask layers of oxide and carborundum, this will cause the difficulty of etching silicon carbide layer.
(3) summary of the invention
For overcoming the formation method of traditional mosaic texture, many shortcomings that it produced the purpose of this invention is to provide a kind of formation method of new damascene manufacturing process, so that promote the productive rate and the yield of follow-up manufacturing process.
According to above-described purpose, the present invention discloses a kind of etching manufacturing process of new formation mosaic texture.At first, provide one to have the Semiconductor substrate of one first dielectric layer, form one first hard mask layer and one second hard mask layer on it in regular turn on first dielectric layer, wherein, first hard mask layer is the grinding stop layer as subsequent chemistry mechanical lapping manufacturing process (CMP).Then, form and form one first photoresist layer on second hard mask layer.Then, by first photoresist layer as an etching mask carry out one first etching manufacturing process with eating thrown first hard mask layer and second hard mask layer till a predetermined thickness of first hard mask layer, and form one and have first of first pattern and be opened on first hard mask layer.After removing first photoresist layer, carry out abolishing manufacturing process and residue in the polymer residue material and the oxidation material on first hard mask layer and the second hard mask layer surface, wherein, abolish manufacturing process and be to use gas (CFx-based) with fluorocarbons with removal, for example, Ar/O
2/ CF
4, the top surface that washes away first hard mask layer and second hard mask layer slightly is to remove residual polymer residue material and oxidation material.Subsequently, form one second dielectric layer on second hard mask layer and fill up first opening, wherein, second dielectric layer is to be anti-reflecting layer (anti-reflection coating; ARC) or bottom anti-reflection layer (BARC).Secondly, form and form one second photoresist layer on second dielectric layer, and by second photoresist layer as an etching mask carry out one second etching manufacturing process with eating thrown second dielectric layer and first hard mask layer till a predetermined thickness of first dielectric layer, and form one and have second of second pattern and be opened in first dielectric layer.After removing second photoresist layer and second dielectric layer, by second hard mask layer as etching mask carry out one the 3rd etching manufacturing process with eating thrown first hard mask layer and first dielectric layer till the exposure Semiconductor substrate, wherein, the 3rd etching manufacturing process is to slow down the etch-rate of first opening by first hard mask layer, and the 3rd etching manufacturing process is to use the mist with chlorine and oxygen, for example, has Cl
2/ O
2Mist, this 3rd etching worker artistic skill is by Cl
2Mixing ratio adjust etching selectivity, that is, Cl
2Mixing ratio high more, then the etching selectivity of first hard mask layer and second hard mask layer is also high more.At last, remove second hard mask layer to form dual-damascene structure in first dielectric layer.
The present invention is with the etch hard mask layer and form mosaic texture by two step etching manufacturing process, this two steps etching manufacturing process is to comprise to abolish a step (Breakthrough step) and an etching step, wherein, abolish step and be to use gas (CFx-based) with fluorocarbons, for example, Ar/O
2/ CF
4, the top surface that washes away hard mask layer slightly is to remove residual polymer residue material and oxidation material; Etching step is to use the mist that contains chlorine, for example, has Cl
2/ O
2Mist, with etch hard mask layer in advance and part dielectric layer up to form one be opened in the dielectric layer till, afterwards, again by this structure formation mosaic texture.So the present invention can improve yield and the productive rate on the manufacturing process effectively.Therefore, the present invention can meet economically benefit and the usability on the industry, and this method can be applicable in the technology of deep-sub-micrometer of semiconductor element.
Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable
Embodiment is elaborated.
(4) description of drawings
Figure 1A to Fig. 1 D is according in first preferred embodiment of the present invention, forms the manufacturing process profile of groove by two step etching manufacturing process;
Fig. 2 A to Fig. 2 E is according in second preferred embodiment of the present invention, forms the manufacturing process profile of mosaic texture by two step etching manufacturing process; With
Fig. 3 A to Fig. 3 E is according in the 3rd preferred embodiment of the present invention, forms the manufacturing process profile of mosaic texture by two step etching manufacturing process.
(5) embodiment
The present invention is in the formation method of this direction of inquiring into mosaic texture that is a kind of semiconductor fabrication process.In order to understand the present invention up hill and dale, detailed step or element will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that the technical staff had the knack of of semiconductor element.On the other hand, well-known manufacturing technology steps or element are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these detailed descriptions, the present invention can also be implemented among other the embodiment widely, and scope of the present invention do not limited, and it is to be as the criterion with appended claim institute restricted portion.
Shown in Fig. 1 D, in the first embodiment of the present invention, at first, provide semi-conductive substrate 100, form in regular turn on it silicon carbide layer 110 (for example, SiC) with one silica layer 120.Then, form and form a photoresist layer 130 on silicon oxide layer 120, and by photoresist layer 130 as an etching mask carry out one first etching manufacturing process 140 with etching silicon oxide layer 120 till the part surface that exposes silicon carbide layer 110, and form an opening 150 on silicon carbide layer 110.After removing photoresist layer 130, carry out abolishing manufacturing process 160 and residue in the polymer residue material and the oxidation material on silicon carbide layer 110 and silicon oxide layer 120 surfaces, in addition, abolish manufacturing process 160 and be to use gas (CFx-based) with fluorocarbons with removal, for example, Ar/O
2/ CF
4, the top surface that washes away silicon carbide layer 110 and silicon oxide layer 120 slightly is to remove residual polymer residue material and oxidation material.Subsequently, by silicon oxide layer 120 as etching mask carry out one second etching manufacturing process 170 with etching silicon carbide layer 110 till the surface that exposes Semiconductor substrate 100, wherein, the second etching manufacturing process 170 is to use the mist with chlorine and oxygen, for example, has Cl
2/ O
2Mist, and this second etching manufacturing process 170 can be by Cl
2Mixing ratio adjust etching selectivity, that is, Cl
2Mixing ratio high more, then the etching selectivity of 110 pairs of silicon oxide layers 120 of silicon carbide layer is also high more.At last, remove silicon oxide layer 120 to form a groove structure 180 on Semiconductor substrate 100.
Shown in figure 2A to Fig. 2 E, in the second embodiment of the present invention, at first, provide semi-conductive substrate 200, formation one has the first dielectric layer 210A of low-k on it.Then, form one first hard mask layer 220, a metal level 230 and one second hard mask layer 240 in regular turn on the first dielectric layer 210A, wherein, first hard mask layer 220 is the grinding stop layers as subsequent chemistry mechanical lapping manufacturing process, and the material of first hard mask layer 220 comprises carborundum, for example, SiC, and the material of second hard mask layer 240 comprises oxide.Then, form one first photoresist layer 250A on second hard mask layer 240, and by the first photoresist layer 250A as an etching mask carry out one first etching manufacturing process 260A with eating thrown second hard mask layer 240, metal level 230 and first hard mask layer 220 till one first predetermined thickness of first hard mask layer 220, and form one and have the first opening 270A of first pattern on first hard mask layer 220, wherein, first pattern is to be a shallow pattern or a channel patterns.After removing the first photoresist layer 250A, carry out abolishing manufacturing process 280 residues in first hard mask layer 220 and second hard mask layer, 240 surfaces with removal polymer residue material and oxidation material, in addition, abolish manufacturing process 280 and be to use gas (CFx-based) with fluorocarbons, for example, Ar/O
2/ CF
4, the top surface that washes away first hard mask layer 220 and second hard mask layer 240 slightly is to remove residual polymer residue material and oxidation material.Subsequently, form one second dielectric layer 210B on second hard mask layer 240 and fill up the first opening 270A, wherein, the second dielectric layer 210B is anti-reflecting layer (anti-reflection coating; ARC) or bottom anti-reflection layer (BARC).Afterwards, form and form one second photoresist layer 250B on the second dielectric layer 210B, and by the second photoresist layer 250B as an etching mask carry out one second etching manufacturing process 260B with the eating thrown second dielectric layer 210B and first hard mask layer 220 till one second predetermined thickness of the first dielectric layer 210A, form one simultaneously and have the second opening 270B of second pattern in the first dielectric layer 210A, wherein, second pattern is to be a dark pattern or an interlayer hole pattern.After removing the second photoresist layer 250B and the second dielectric layer 210B, by second hard mask layer 240 as etching mask carry out one the 3rd etching manufacturing process 260C with eating thrown first hard mask layer 220 and the first dielectric layer 210A till exposure Semiconductor substrate 200, and the 3rd etching manufacturing process 260C is the etch-rate that slows down the first opening 270A by first hard mask layer 220, wherein, the 3rd etching manufacturing process 260C is to use the mist with chlorine and oxygen, for example, has Cl
2/ O
2Mist, and this 3rd etching manufacturing process 260C can be by Cl
2Mixing ratio adjust etching selectivity, that is, Cl
2Mixing ratio high more, then the etching selectivity of first hard mask layer 220 and second hard mask layer 240 is also high more.At last, remove second hard mask layer 240 to form dual-damascene structure 290 in first dielectric layer 210.It should be noted that in the present embodiment metal level 230 can be contained in the stack structure of second hard mask layer 240, so the formation of metal level 230 is not to have its necessity, needs determine it whether to form with the demand on the manufacturing process.
Shown in figure 3A to Fig. 3 E, in the third embodiment of the present invention, at first, provide semi-conductive substrate 300, formation one has the dielectric layer 310 of low-k on it.Then, form one first hard mask layer 320, a metal level 330 and one second hard mask layer 340 in regular turn on dielectric layer 310, wherein, first hard mask layer 320 is the grinding stop layers as subsequent chemistry mechanical lapping manufacturing process, and the material of first hard mask layer 320 comprises carborundum, for example, SiC, and the material of second hard mask layer 340 comprises oxide.Then, form and form one first photoresist layer 350A on second hard mask layer 340, and by the first photoresist layer 350A as an etching mask carry out one first etching manufacturing process 360A with eating thrown second hard mask layer 340, metal level 330, first hard mask layer 320 and dielectric layer 310 till one first predetermined thickness of dielectric layer 310, and form one and have the first opening 370A of first pattern on dielectric layer 310, wherein, first pattern is to be a dark pattern or an interlayer hole pattern.After removing the first photoresist layer 350A, form and form one second photoresist layer 350B on second hard mask layer 340, and by the second photoresist layer 350B as an etching mask carry out one second etching manufacturing process 360B with etching second hard mask layer 340, metal level 330 and first hard mask layer 320 till one second predetermined thickness of first hard mask layer 320, and form one and have the second opening 370B of second pattern on first hard mask layer 320, wherein, second pattern is to be a shallow pattern or a channel patterns.After removing the second photoresist layer 350B, carry out abolishing manufacturing process 380 and residue in the polymer residue material and the oxidation material on above-mentioned overall structure surface, in addition, abolish manufacturing process 380 and be to use gas (CFx-based) with fluorocarbons with removal, for example, Ar/O
2/ CF
4, the top surface that washes away first hard mask layer 320 and second hard mask layer 340 slightly is to remove residual polymer residue material and oxidation material.Subsequently, by second hard mask layer 340 as etching mask carry out one the 3rd etching manufacturing process 360C with etching first hard mask layer 320 and dielectric layer 310 till exposing Semiconductor substrate 300, and the 3rd etching manufacturing process 360C is the etch-rate that slows down the second opening 370B by first hard mask layer 320, wherein, the 3rd etching manufacturing process 360C is to use the mist with chlorine and oxygen, for example, has Cl
2/ O
2Mist, and this 3rd etching manufacturing process 360C can adjust etching selectivity by the mixing ratio of Cl2, that is, Cl
2Mixing ratio high more, then the etching selectivity of first hard mask layer 320 and second hard mask layer 340 is also high more.At last, remove second hard mask layer 340 to form dual-damascene structure 390 in dielectric layer 310.It should be noted that in the present embodiment metal level 330 can be contained in the stack structure of second hard mask layer 340, so the formation of metal level 330 is not to have its necessity, determines it whether to form with the demand on the manufacturing process.
As mentioned above, in an embodiment of the present invention, the present invention can by abolish manufacturing process remove in advance on the hard mask layer residual polymer residue material and oxidation material, to be easy to the etch hard mask layer.In addition, the present invention also can be opened in the dielectric layer top surface to avoid micro loading effect (micro-loading effect) by being pre-formed one, and the present invention uses the mist with chlorine and oxygen to carry out the etching manufacturing process, can obtain higher etching selectivity by this, for example, carborundum can reach the etching selectivity of silica and be about 5: 1.Certainly, the present invention also may be used on the etching manufacturing process of any semiconductor element except on the formation manufacturing process that may be used in metal damascene structure.And to form the method for dual-damascene structure, development is used in about damascene manufacturing process aspect not yet so far by two step etching manufacturing process in the present invention.For the manufacturing process of deep-sub-micrometer, this method is the formation manufacturing process of a preferable feasible mosaic texture.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement in other embodiment widely.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from that the equivalence finished under the disclosed spirit changes or equivalence is replaced, and all should be included in the following claim institute restricted portion.
Claims (20)
1. the formation method of a groove structure is characterized in that, comprises the following step:
Semi-conductive substrate is provided;
Form a silicon carbide layer and one silica layer in regular turn on this Semiconductor substrate;
Define a photoresist layer and on this silicon oxide layer, think etching mask;
This silicon oxide layer of etching and forms one and is opened on this silicon carbide layer till the part surface that exposes this silicon carbide layer;
Remove this photoresist layer;
Carry out abolishing manufacturing process and wash away polymer residue material and the oxidation material that residues in this silicon carbide layer and this silicon oxide layer surface with removal slightly by the gas that use has fluorocarbons, wherein this polymer residue material is the residual of this photoresist layer, and this oxidation material forms for this silicon carbide layer and this silicon oxide layer surface oxidation;
By this silicon oxide layer as etching mask carry out an etching manufacturing process with this silicon carbide layer of etching till the surface that exposes this Semiconductor substrate; With
Remove this silicon oxide layer to form a groove structure on this Semiconductor substrate.
2. the formation method of groove structure as claimed in claim 1 is characterized in that, described gas with fluorocarbons is for having Ar/O
2/ CF
4Mist.
3. the formation method of groove structure as claimed in claim 1 is characterized in that, described etching manufacturing process is to use the mist with chlorine and oxygen.
4. the formation method of groove structure as claimed in claim 3, it is characterized in that, described etching manufacturing process is to adjust etching selectivity by the mixing ratio of chlorine, and the mixing ratio of chlorine is high more, and then this silicon carbide layer is also high more to the etching selectivity of this silicon oxide layer.
5. the formation method of a mosaic texture is characterized in that, comprises the following step:
Semi-conductive substrate is provided, has one first dielectric layer on it;
Form one first hard mask layer and one second hard mask layer in regular turn on this first dielectric layer;
Define one first photoresist layer and on this second hard mask layer, think etching mask;
This second hard mask layer of etching and this first hard mask layer and form one and have first of first pattern and be opened on this first hard mask layer till one first predetermined thickness of this first hard mask layer;
Remove this first photoresist layer;
Carry out abolishing manufacturing process and wash away polymer residue material and the oxidation material that residues in this first hard mask layer and this second hard mask layer surface with removal slightly by the gas that use has fluorocarbons, wherein this polymer residues is the residual of this first photoresist layer, and this oxide forms for this first hard mask layer and this second hard mask layer surface oxidation;
Form one second dielectric layer on this second hard mask layer and fill up this first opening;
Define one second photoresist layer and on this second dielectric layer, think etching mask;
This second dielectric layer of etching and this first hard mask layer are till one second predetermined thickness of this first dielectric layer, form one simultaneously and have second of second pattern and be opened in this first dielectric layer, this second opening is positioned at this first opening below and is connected with this first opening;
Remove this second photoresist layer;
Remove this second dielectric layer;
By this second hard mask layer as etching mask carry out an etching manufacturing process with this first hard mask layer of eating thrown and this first dielectric layer till this Semiconductor substrate of exposure; With
Remove this second hard mask layer to form a mosaic texture in this first dielectric layer.
6. the formation method of mosaic texture as claimed in claim 5 is characterized in that, the material of described first hard mask layer is a carborundum.
7. the formation method of mosaic texture as claimed in claim 5 is characterized in that, the material of described second hard mask layer is the silica material.
8. the formation method of mosaic texture as claimed in claim 5 is characterized in that, described first pattern is to be a shallow pattern, and second pattern is to be a dark pattern.
9. the formation method of groove structure as claimed in claim 5 is characterized in that, described gas with fluorocarbons is to have Ar/O
2/ CF
4Gas.
10. the formation method of groove structure as claimed in claim 5 is characterized in that, described etching manufacturing process is to slow down the etch-rate of this first opening by this first hard mask layer.
11. the formation method of groove structure as claimed in claim 5 is characterized in that, described etching manufacturing process is to use the mist with chlorine and oxygen.
12. the formation method of groove structure as claimed in claim 11, it is characterized in that, described etching manufacturing process is to adjust etching selectivity by the mixing ratio of chlorine, and the mixing ratio of chlorine is high more, and then this first hard mask layer is also high more to the etching selectivity of this second hard mask layer.
13. the formation method of a mosaic texture is characterized in that, comprises the following step:
Semi-conductive substrate is provided, has a dielectric layer on it;
Form one first hard mask layer and one second hard mask layer in regular turn on this dielectric layer;
Define one first photoresist layer and on this second hard mask layer, think etching mask;
This second hard mask layer of etching, this first hard mask layer and this dielectric layer and form one and have first of first pattern and be opened on this dielectric layer till one first predetermined thickness of this dielectric layer;
Remove this first photoresist layer;
Define one second photoresist layer and on this second hard mask layer, think etching mask;
This second hard mask layer of etching and this first hard mask layer are till one second thickness of this first hard mask layer, and form one and have second of second pattern and be opened on this first hard mask layer, this second opening is positioned at this first opening below and is connected with this first opening;
Remove this second photoresist layer;
Carrying out abolishing manufacturing process washes away to remove residual polymer residue material and oxidation material slightly by the gas that use has fluorocarbons, wherein this polymer residue material is the residual of this first photoresist layer, and this oxidation material forms for this first hard mask layer and this second hard mask layer surface oxidation;
By this second hard mask layer as etching mask carry out an etching manufacturing process with this first hard mask layer of etching and this dielectric layer till this Semiconductor substrate of exposure; With
Remove this second hard mask layer to form a mosaic texture in this dielectric layer.
14. the formation method of mosaic texture as claimed in claim 13 is characterized in that, the material of described first hard mask layer is a silicon carbide material.
15. the formation method of mosaic texture as claimed in claim 13 is characterized in that, the material of described second hard mask layer is the silica material.
16. the formation method of mosaic texture as claimed in claim 13 is characterized in that, described first pattern is to be a dark pattern, and second pattern is to be a shallow pattern.
17. the formation method of mosaic texture as claimed in claim 13 is characterized in that, described gas with fluorocarbons is to have Ar/O
2/ CF
4Mist.
18. the formation method of mosaic texture as claimed in claim 13 is characterized in that, described etching manufacturing process is to slow down the etch-rate of this second opening by this first hard mask layer.
19. the formation method of mosaic texture as claimed in claim 13 is characterized in that, described etching manufacturing process is to use the mist with chlorine and oxygen.
20. the formation method of mosaic texture as claimed in claim 19, it is characterized in that, described etching manufacturing process is to adjust etching selectivity by the mixing ratio of chlorine, and the mixing ratio of chlorine is high more, and then this first hard mask layer is also high more to the etching selectivity of this second hard mask layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107403 CN1266748C (en) | 2003-03-12 | 2003-03-12 | Etching process for shaping semiconductor embedded structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107403 CN1266748C (en) | 2003-03-12 | 2003-03-12 | Etching process for shaping semiconductor embedded structure |
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| CN1531034A CN1531034A (en) | 2004-09-22 |
| CN1266748C true CN1266748C (en) | 2006-07-26 |
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| CN100361275C (en) * | 2004-10-12 | 2008-01-09 | 联华电子股份有限公司 | Etching method of preparation, and pattermizing method of preparation |
| CN104979281A (en) * | 2015-05-25 | 2015-10-14 | 上海华力微电子有限公司 | Contact hole forming method |
| CN107808822A (en) * | 2017-09-29 | 2018-03-16 | 上海华虹宏力半导体制造有限公司 | The lithographic method of contact hole |
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