CN1531034A - Etching process for shaping semiconductor embedded structure - Google Patents
Etching process for shaping semiconductor embedded structure Download PDFInfo
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- CN1531034A CN1531034A CNA031074030A CN03107403A CN1531034A CN 1531034 A CN1531034 A CN 1531034A CN A031074030 A CNA031074030 A CN A031074030A CN 03107403 A CN03107403 A CN 03107403A CN 1531034 A CN1531034 A CN 1531034A
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Abstract
The present invention discloses a new etching method for forming a damascene structure. The invention comprises: performing an estimating process to estimate the residual polymer and oxide remaining on the surface of the mask, wherein a CFx-based gas, such as Ar/O2/CF4 is used to erode slightly the top surface of the mask to estimate the residual polymer and oxide; thereafter, performing an etching process to etch the mask with a predetermined thickness up to a dielectric layer; and finally performing another etching process to etch the mask and the dielectric layer and form a damascene structure in the dielectric layer, wherein a mixing gas containing chlorine, such as the mixing gas containing Cl2/O2, is used in the etching process.
Description
(1) technical field
The formation processing procedure of the relevant a kind of semiconductor mosaic texture of the present invention, and particularly relevant a kind of engraving method that forms the semiconductor mosaic texture.
(2) background technology
Because the integration of the semiconductor element of integrated circuit increases day by day, when making the surface of chip can't provide enough areas to make required intraconnections, for complexed metal oxide semiconductor (Metal OxideSemiconductor; MOS) transistor dwindles the intraconnections demand that increased of back, and two-layer above metal level design is gradually the mode that becomes the essential employing of many integrated circuits institute just.In addition, in the processing procedure of deep-sub-micrometer, because the integration of integrated circuit constantly increases, therefore adopt the comprehensive architecture of multiple layer inner connection line (Multi-levelinterconnects) at present mostly, and often with inner metal dielectric layer (Inter-Metal Dielectric; IMD) as the dielectric material of isolating each metal interconnecting.Wherein be used for connecting the lead of two metal layers up and down, on semi-conductor industry, title be interlayer hole connector (Via Plug).Usually the opening that forms in dielectric layer, if expose base members in the intraconnections, that then claim is contact hole (contact hole).
The method of known manufacturing interlayer hole and intraconnections has two kinds, and wherein a kind of is that interlayer hole and intraconnections are finished in two steps suddenly, promptly forms dielectric layer above metal level, then forms photoresist layer (Photoresist above dielectric layer; PR), utilize etching technique to finish interlayer hole then, and utilize sedimentation in this interlayer hole deposits conductive material to finish the making of interlayer hole, deposit and form metal level afterwards, deposit inner metal dielectric layer at last again.Tradition forms the processing procedure of metal interconnecting, is to make interlayer hole and metal interconnecting with twice micro-photographing process respectively, therefore the step that needs loaded down with trivial details deposition and pattern to form.Yet, the manufacture of semiconductor below deep-sub-micrometer (Sub-quartermicron), (Layout) is more complicated because of the multilayer interconnection layout, causes the pattern that is difficult to form metal interconnecting.Therefore, develop again at present another kind of inserted in link structures (Damasceneinterconnect structure).According to the characteristic on the processing procedure, can be divided into single-layer type (Single type), doublet type (Dual type) and self-aligned type (Self-aligned type).Damascene (Damascene) is the irrigation canals and ditches that etch metal interconnecting earlier for a kind of in dielectric layer, insert metal again and be used as the method for intraconnections, this method can make that the processing procedure of metal interconnecting need not etched step, introduces in the semiconductor element and copper etc. can be difficult for etched metal.Therefore making intraconnections in deep-sub-micrometer is the mode of the best with this method.
Traditional dual-metal inserting processing procedure comprises two kinds of patterns and forms, and the one, dark pattern (Deep patterns) forms, that is forms the formation (Via-first) of interlayer hole; Another is that shallow pattern forms (Shallowpatterns) or line pattern forms (Line patterns), that is forms the formation (Trench-first) of groove.For the manufacturing of deep-sub-micrometer element, in the double-insert process etch process, use photoresistance and nonmetal/metal mask usually with lower etching photoresistance wavelength.In traditional dual-damascene structure processing procedure, if directly using having, the slurry of cmp processing procedure carries out polish process on the dielectric layer of low-k, then will in the cmp processing procedure of this kind copper, produce the problem that a large amount of carbon residues is caused easily, therefore, being used to cover on the dielectric layer with low-k with the wherein dielectric layer as the grinding stop layer of cmp processing procedure is to be the carbon silicide layer, and it is the defective in order to prevent that the cmp processing procedure from being produced mainly.The processing procedure that forms with groove is an example, and it is to carry out the etching of part interlayer hole after the mask pattern forms, and the structure of dual damascene then forms during groove is etched simultaneously.Yet owing to can produce oxidation on the surface of carbon silicide layer, especially true in the stack structure of two masks of oxide and carbon silicide, this will cause the difficulty of etching carbon silicide layer.
(3) summary of the invention
For overcoming the formation method of traditional mosaic texture, many shortcomings that it produced the purpose of this invention is to provide a kind of formation method of new damascene processing procedure, so that promote the productive rate and the yield of successive process.
According to above-described purpose, the present invention discloses a kind of etch process of new formation mosaic texture.At first, provide one to have the semiconductor substrate of one first dielectric layer, form one first mask and one second mask on it in regular turn on first dielectric layer, wherein, first mask is the grinding stop layer as subsequent chemistry mechanical lapping processing procedure (CMP).Then, form and form one first photoresist layer on second mask.Then, by first photoresist layer as an etch mask carry out one first etch process with eating thrown first mask and second mask till a predetermined thickness of first mask, and form one and have first of first pattern and be opened on first mask.After removing first photoresist layer, carry out abolishing processing procedure and residue in the polymer residue material and the oxidation material on first mask and the second mask surface with removal, wherein, abolish processing procedure and be to use gas (CFx-based) with carbon fluorine ratio, for example, Ar/O
2/ CF
4, the top surface that washes away first mask and second mask slightly is to remove residual polymer residue material and oxidation material.Subsequently, form one second dielectric layer on second mask and fill up first opening, wherein, second dielectric layer is to be anti-reflecting layer (anti-reflection coating; ARC) or bottom anti-reflection layer (BARC).Secondly, form and form one second photoresist layer on second dielectric layer, and by second photoresist layer as an etch mask carry out one second etch process with eating thrown second dielectric layer and first mask till a predetermined thickness of first dielectric layer, and form one and have second of second pattern and be opened in first dielectric layer.After removing second photoresist layer and second dielectric layer, by second mask as etch mask carry out one the 3rd etch process with eating thrown first mask and first dielectric layer till the exposure semiconductor substrate, wherein, the 3rd etch process is the etch-rate that slows down first opening by first mask, and the 3rd etch process is to use chloride mist, for example, has Cl
2/ O
2Mist, this 3rd etch process can be by Cl
2Mixing ratio adjust etching selectivity, that is, Cl
2Mixing ratio high more, then the etching selectivity of first mask and second mask is also high more.At last, remove second mask to form dual-damascene structure in first dielectric layer.
The present invention is with the etching mask and form mosaic texture by two step etch process, this two steps etch process is to comprise to abolish a step (Breakthrough step) and an etching step, wherein, abolishes step and is to use the gas (CFx-based) with carbon fluorine ratio, for example, Ar/O
2/ CF
4, the top surface that washes away mask slightly is to remove residual polymer residue material and oxidation material; Etching step is to use the mist that contains chlorine, for example, has Cl
2/ O
2Mist, with etching mask in advance and part dielectric layer up to form one be opened in the dielectric layer till, afterwards, again by this structure formation mosaic texture.So the present invention can improve yield and the productive rate on the processing procedure effectively.Therefore, the present invention can meet economically benefit and the usability on the industry, and this method can be applicable in the technology of deep-sub-micrometer of semiconductor element.
Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable
Embodiment is elaborated.
(4) description of drawings
Figure 1A to Fig. 1 D is according in first preferred embodiment of the present invention, forms the processing procedure profile of groove by two step etch process;
Fig. 2 A to Fig. 2 E is according in second preferred embodiment of the present invention, forms the processing procedure profile of mosaic texture by two step etch process; With
Fig. 3 A to Fig. 3 E is according in the 3rd preferred embodiment of the present invention, forms the processing procedure profile of mosaic texture by two step etch process.
(5) embodiment
The present invention is in the formation method of this direction of inquiring into mosaic texture that is a kind of manufacture of semiconductor.In order to understand the present invention up hill and dale, detailed step or element will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that the technical staff had the knack of of semiconductor element.On the other hand, well-known fabrication steps or element are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these detailed descriptions, the present invention can also be implemented among other the embodiment widely, and scope of the present invention do not limited, and it is to be as the criterion with appended claim institute restricted portion.
Shown in Fig. 1 D, in the first embodiment of the present invention, at first, provide semiconductor ground 100, form in regular turn on it carbon silicide layer 110 (for example, SiC) with a silicon oxide layer 120.Then, form and form a photoresist layer 130 on silicon oxide layer 120, and by photoresist layer 130 as an etch mask carry out one first etch process 140 with etching silicon oxide skin(coating) 120 till the part surface that exposes carbon silicide layer 110, and form an opening 150 on carbon silicide layer 110.After removing photoresist layer 130, carry out abolishing processing procedure 160 and residue in the polymer residue material and the oxidation material on carbon silicide layer 110 and silicon oxide layer 120 surfaces, in addition, abolish processing procedure 160 and be to use gas (CFx-based) with carbon fluorine ratio with removal, for example, Ar/O
2/ CF
4, the top surface that washes away carbon silicide layer 110 and silicon oxide layer 120 slightly is to remove residual polymer residue material and oxidation material.Subsequently, by silicon oxide layer 120 as etch mask carry out one second etch process 170 with etching carbon silicide layer 110 till the surface that exposes semiconductor substrate 100, wherein, second etch process 170 is to use chloride mist, for example, has Cl
2/ O
2Mist, and this second etch process 170 can be by Cl
2Mixing ratio adjust etching selectivity, that is, Cl
2Mixing ratio high more, then the etching selectivity of 110 pairs of silicon oxide layers 120 of carbon silicide layer is also high more.At last, remove silicon oxide layer 120 to form a groove structure 180 on semiconductor substrate 100.
Shown in figure 2A to Fig. 2 E, in the second embodiment of the present invention, at first, provide semiconductor ground 200, formation one has the first dielectric layer 210A of low-k on it.Then, form one first mask 220, a metal level 230 and one second mask 240 in regular turn on the first dielectric layer 210A, wherein, first mask 220 is the grinding stop layers as subsequent chemistry mechanical lapping processing procedure, and the material of first mask 220 comprises the carbon silicide, for example, SiC, and the material of second mask 240 comprises oxide.Then, form one first photoresist layer 250A on second mask 240, and by the first photoresist layer 250A as an etch mask carry out one first etch process 260A with eating thrown second mask 240, metal level 230 and first mask 220 till one first predetermined thickness of first mask 220, and form one and have the first opening 270A of first pattern on first mask 220, wherein, first pattern is to be a shallow pattern or a channel patterns.After removing the first photoresist layer 250A, carry out abolishing processing procedure 280 and residue in the polymer residue material and the oxidation material on first mask 220 and second mask, 240 surfaces, in addition, abolish processing procedure 280 and be to use gas (CFx-based) with carbon fluorine ratio with removal, for example, Ar/O
2/ CF
4, the top surface that washes away first mask 220 and second mask 240 slightly is to remove residual polymer residue material and oxidation material.Subsequently, form one second dielectric layer 210B on second mask 240 and fill up the first opening 270A, wherein, the second dielectric layer 210B is anti-reflecting layer (anti-reflection coating; ARC) or bottom anti-reflection layer (BARC).Afterwards, form and form one second photoresist layer 250B on the second dielectric layer 210B, and by the second photoresist layer 250B as an etch mask carry out one second etch process 260B with the eating thrown second dielectric layer 210B and first mask 220 till one second predetermined thickness of the first dielectric layer 210A, form one simultaneously and have the second opening 270B of second pattern in the first dielectric layer 210A, wherein, second pattern is to be a dark pattern or an interlayer hole pattern.After removing the second photoresist layer 250B and the second dielectric layer 210B, by second mask 240 as etch mask carry out one the 3rd etch process 260C with eating thrown first mask 220 and the first dielectric layer 210A till exposure semiconductor substrate 200, and the 3rd etch process 260C is the etch-rate that slows down the first opening 270A by first mask 220, wherein, the 3rd etch process 260C is to use chloride mist, for example, has Cl
2/ O
2Mist, and this 3rd etch process 260C can be by Cl
2Mixing ratio adjust etching selectivity, that is, Cl
2Mixing ratio high more, then the etching selectivity of first mask 220 and second mask 240 is also high more.At last, remove second mask 240 to form dual-damascene structure 290 in first dielectric layer 210.It should be noted that in the present embodiment metal level 230 can be contained in the stack structure of second mask 240, so the formation of metal level 230 is not to have its necessity, needs determine it whether to form with the demand on the processing procedure.
Shown in figure 3A to Fig. 3 E, in the third embodiment of the present invention, at first, provide semiconductor ground 300, formation one has the dielectric layer 310 of low-k on it.Then, form one first mask 320, a metal level 330 and one second mask 340 in regular turn on dielectric layer 310, wherein, first mask 320 is the grinding stop layers as subsequent chemistry mechanical lapping processing procedure, and the material of first mask 320 comprises the carbon silicide, for example, SiC, and the material of second mask 340 comprises oxide.Then, form and form one first photoresist layer 350A on second mask 340, and by the first photoresist layer 350A as an etch mask carry out one first etch process 360A with eating thrown second mask 340, metal level 330, first mask 320 and dielectric layer 310 till one first predetermined thickness of dielectric layer 310, and form one and have the first opening 370A of first pattern on dielectric layer 310, wherein, first pattern is to be a dark pattern or an interlayer hole pattern.After removing the first photoresist layer 350A, form and form one second photoresist layer 350B on second mask 340, and by the second photoresist layer 350B as an etch mask carry out one second etch process 360B with etching second mask 340, metal level 330 and first mask 320 till one second predetermined thickness of first mask 320, and form one and have the second opening 370B of second pattern on first mask 320, wherein, second pattern is to be a shallow pattern or a channel patterns.After removing the second photoresist layer 350B, carry out abolishing processing procedure 380 and residue in the polymer residue material and the oxidation material on above-mentioned overall structure surface with removal, in addition, abolish processing procedure 380 and be to use gas (CFx-based) with carbon fluorine ratio, for example, Ar/O
2/ CF
4, the top surface that washes away first mask 320 and second mask 340 slightly is to remove residual polymer residue material and oxidation material.Subsequently, by second mask 340 as etch mask carry out one the 3rd etch process 360C with etching first mask 320 and dielectric layer 310 till exposing semiconductor substrate 300, and the 3rd etch process 360C is the etch-rate that slows down the second opening 370B by first mask 320, wherein, the 3rd etch process 360C is to use chloride mist, for example, has Cl
2/ O
2Mist, and this 3rd etch process 360C can adjust etching selectivity by the mixing ratio of Cl2, that is, Cl
2Mixing ratio high more, then the etching selectivity of first mask 320 and second mask 340 is also high more.At last, remove second mask 340 to form dual-damascene structure 390 in dielectric layer 310.It should be noted that in the present embodiment metal level 330 can be contained in the stack structure of second mask 340, so the formation of metal level 330 is not to have its necessity, determines it whether to form with the demand on the processing procedure.
As mentioned above, in an embodiment of the present invention, the present invention can by abolish processing procedure remove in advance on the mask residual polymer residue material and oxidation material, to be easy to the etching mask.In addition, the present invention also can be opened in the dielectric layer top surface to avoid micro loading effect (micro-loading effect) by being pre-formed one, and the present invention uses chloride mist to carry out etch process, can obtain higher etching selectivity by this, for example, the carbon silicide can reach the etching selectivity of Si oxide and be about 5: 1.Certainly, the present invention also may be used on the etch process of any semiconductor element except on the formation processing procedure that may be used in metal damascene structure.And to form the method for dual-damascene structure, development is used in about damascene processing procedure aspect not yet so far by two step etch process in the present invention.For the processing procedure of deep-sub-micrometer, this method is the formation processing procedure of a preferable feasible mosaic texture.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement in other embodiment widely.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from that the equivalence finished under the disclosed spirit changes or equivalence is replaced, and all should be included in the following claim institute restricted portion.
Claims (32)
1. the formation method of a groove structure is characterized in that, comprises the following step:
The semiconductor ground is provided;
Form a carbon silicide layer and a silicon oxide layer in regular turn on this semiconductor substrate;
This silicon oxide layer of etching and forms one and is opened on this carbon silicide layer till the part surface that exposes this carbon silicide layer;
Carry out abolishing processing procedure residues in this carbon silicide layer and this Si oxide laminar surface with removal polymer residue material and oxidation material;
By this silicon oxide layer as etch mask carry out an etch process with this carbon silicide layer of etching till the surface that exposes this semiconductor substrate; With
Remove this silicon oxide layer to form a groove structure on this semiconductor substrate.
2. the formation method of groove structure as claimed in claim 1 is characterized in that, the described processing procedure of abolishing is to wash away the top surface of this carbon silicide layer and this silicon oxide layer slightly to remove residual polymer residue material and oxidation material.
3. the formation method of groove structure as claimed in claim 1 is characterized in that, the described processing procedure of abolishing is to use the gas with carbon fluorine ratio.
4. the formation method of groove structure as claimed in claim 3 is characterized in that, described gas with carbon fluorine ratio also comprises and has Ar/O
2/ CF
4Mist.
5. the formation method of groove structure as claimed in claim 1 is characterized in that, described etch process is to use chloride mist.
6. the formation method of groove structure as claimed in claim 5 is characterized in that, described chloride mist also comprises the mist with chlorine and oxygen.
7. the formation method of groove structure as claimed in claim 5 is characterized in that, described etch process is to adjust etching selectivity by the mixing ratio of chlorine.
8. the formation method of groove structure as claimed in claim 7 is characterized in that, the mixing ratio of described chlorine is high more, and then this carbon silicide layer is also high more to the etching selectivity of this silicon oxide layer.
9. the formation method of a mosaic texture is characterized in that, comprises the following step:
The semiconductor ground is provided, has one first dielectric layer on it;
Form one first mask and one second mask in regular turn on this first dielectric layer;
This second mask of etching and this first mask and form one and have first of first pattern and be opened on this first mask till one first predetermined thickness of this first mask;
Carry out abolishing processing procedure residues in this first mask and this second mask surface with removal polymer residue material and oxidation material;
Form one second dielectric layer on this second mask and fill up this first opening;
This second dielectric layer of etching and this first mask form one simultaneously and have second of second pattern and be opened in this first dielectric layer till one second predetermined thickness of this first dielectric layer;
Remove this second dielectric layer;
By this second mask as etch mask carry out an etch process with this first mask of eating thrown and this first dielectric layer till this semiconductor substrate of exposure; With
Remove this second mask to form a mosaic texture in this first dielectric layer.
10. the formation method of mosaic texture as claimed in claim 9 is characterized in that, the material of described first mask comprises the carbon silicide.
11. the formation method of mosaic texture as claimed in claim 9 is characterized in that the material of described second mask comprises oxide.
12. the formation method of mosaic texture as claimed in claim 9 is characterized in that, described first pattern is to be a shallow pattern, and second pattern is to be a dark pattern.
13. the formation method of mosaic texture as claimed in claim 9 is characterized in that, the described processing procedure of abolishing is to wash away the top surface of this first mask and this second mask slightly to remove residual polymer residue material and oxidation material.
14. the formation method of groove structure as claimed in claim 9 is characterized in that, the described processing procedure of abolishing is to use the gas with carbon fluorine ratio.
15. the formation method of groove structure as claimed in claim 14 is characterized in that, described gas with carbon fluorine ratio also comprises and has Ar/O
2/ CF
4Mist.
16. the formation method of groove structure as claimed in claim 9 is characterized in that, described etch process is the etch-rate that slows down this first opening by this first mask.
17. the formation method of groove structure as claimed in claim 9 is characterized in that described etch process is to use chloride mist.
18. the formation method of groove structure as claimed in claim 17 is characterized in that, described chloride mist also comprises the mist with chlorine and oxygen.
19. the formation method of groove structure as claimed in claim 17 is characterized in that, described etch process is to adjust etching selectivity by the mixing ratio of chlorine.
20. the formation method of groove structure as claimed in claim 17 is characterized in that the mixing ratio of described chlorine is high more, then this first mask is also high more to the etching selectivity of this second mask.
21. the formation method of a mosaic texture is characterized in that, comprises the following step:
The semiconductor ground is provided, has a dielectric layer on it;
Form one first mask and one second mask in regular turn on this dielectric layer;
This second mask of etching, this first mask and this dielectric layer and form one and have first of first pattern and be opened on this dielectric layer till one first predetermined thickness of this dielectric layer;
This second mask of etching and this first mask and form one and have second of second pattern and be opened on this first mask till one second thickness of this first mask;
Carry out abolishing processing procedure to remove residual polymer residue material and oxidation material;
By this second mask as etch mask carry out an etch process with this first mask of etching and this dielectric layer till this semiconductor substrate of exposure; With
Remove this second mask to form a mosaic texture in this dielectric layer.
22. the formation method of mosaic texture as claimed in claim 21 is characterized in that the material of described first mask comprises the carbon silicide.
23. the formation method of mosaic texture as claimed in claim 21 is characterized in that the material of described second mask comprises oxide.
24. the formation method of mosaic texture as claimed in claim 21 is characterized in that, described first pattern is to be a dark pattern, and second pattern is to be a shallow pattern.
25. the formation method of mosaic texture as claimed in claim 21 is characterized in that, the described processing procedure of abolishing is to wash away the top surface of this first mask and this second mask slightly to remove residual polymer residue material and oxidation material.
26. the formation method of mosaic texture as claimed in claim 21 is characterized in that, the described processing procedure of abolishing is to use the gas with carbon fluorine ratio.
27. the formation method of mosaic texture as claimed in claim 26 is characterized in that, described gas with carbon fluorine ratio also comprises and has Ar/O
2/ CF
4Mist.
28. the formation method of mosaic texture as claimed in claim 21 is characterized in that, described etch process is the etch-rate that slows down this second opening by this first mask.
29. the formation method of mosaic texture as claimed in claim 21 is characterized in that described etch process is to use chloride mist.
30. the formation method of mosaic texture as claimed in claim 29 is characterized in that, described chloride mist also comprises the mist with chlorine and oxygen.
31. the formation method of mosaic texture as claimed in claim 29 is characterized in that, described etch process is to adjust etching selectivity by the mixing ratio of chlorine.
32. the formation method of mosaic texture as claimed in claim 29 is characterized in that the mixing ratio of described chlorine is high more, then this first mask is also high more to the etching selectivity of this second mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107403 CN1266748C (en) | 2003-03-12 | 2003-03-12 | Etching process for shaping semiconductor embedded structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107403 CN1266748C (en) | 2003-03-12 | 2003-03-12 | Etching process for shaping semiconductor embedded structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1531034A true CN1531034A (en) | 2004-09-22 |
| CN1266748C CN1266748C (en) | 2006-07-26 |
Family
ID=34282963
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03107403 Expired - Lifetime CN1266748C (en) | 2003-03-12 | 2003-03-12 | Etching process for shaping semiconductor embedded structure |
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361275C (en) * | 2004-10-12 | 2008-01-09 | 联华电子股份有限公司 | Etching method of preparation, and pattermizing method of preparation |
| CN104979281A (en) * | 2015-05-25 | 2015-10-14 | 上海华力微电子有限公司 | Contact hole forming method |
| CN107808822A (en) * | 2017-09-29 | 2018-03-16 | 上海华虹宏力半导体制造有限公司 | The lithographic method of contact hole |
-
2003
- 2003-03-12 CN CN 03107403 patent/CN1266748C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361275C (en) * | 2004-10-12 | 2008-01-09 | 联华电子股份有限公司 | Etching method of preparation, and pattermizing method of preparation |
| CN104979281A (en) * | 2015-05-25 | 2015-10-14 | 上海华力微电子有限公司 | Contact hole forming method |
| CN107808822A (en) * | 2017-09-29 | 2018-03-16 | 上海华虹宏力半导体制造有限公司 | The lithographic method of contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1266748C (en) | 2006-07-26 |
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