CN102005409A - Preparation method of dual damascene structure - Google Patents
Preparation method of dual damascene structure Download PDFInfo
- Publication number
- CN102005409A CN102005409A CN2009101949198A CN200910194919A CN102005409A CN 102005409 A CN102005409 A CN 102005409A CN 2009101949198 A CN2009101949198 A CN 2009101949198A CN 200910194919 A CN200910194919 A CN 200910194919A CN 102005409 A CN102005409 A CN 102005409A
- Authority
- CN
- China
- Prior art keywords
- dielectric materials
- materials layer
- dielectric
- layer
- dielectric material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a preparation method of a dual damascene structure. The method comprises the following steps: forming a first dielectric material layer and a second dielectric material layer on a substrate in turn, wherein the second dielectric material layer is covered on the first dielectric material layer and the hardness of the second dielectric material layer is higher than that of the first dielectric material layer; forming grooves and pores on the first dielectric material layer and the second dielectric material layer respectively, depositing metal material in the grooves and pores; removing excess metal material and the second dielectric material layer to ensure that the surface of the first dielectric material layer has thin second dielectric material layer or does not have the second dielectric material layer. By adopting the method of the invention, under the premise of not increasing the process complexity, the probability that the first dielectric material layer with low hardness is scratched or worn is reduced and the element can have good dielectric property, high stability and product yield and good transmission performance.
Description
Technical field
The present invention relates to semiconductor fabrication, especially relate to the manufacture method of dual-damascene structure.
Background technology
In very lagre scale integrated circuit (VLSIC) technology, along with the microminiaturization of element and the increase of integrated level, the number of lead constantly increases in the circuit, and the ghost effect that resistance in the lead (R) and electric capacity (C) are produced has caused serious transmission delay (RC Delay).In order to reduce transmission delay, people study and improve, for example aspect reducing resistance and reducing parasitic capacitance, because metallic copper has the ability of high-melting-point, low resistance and high anti-electron transfer, most at present metallic copper replacement metallic aluminiums commonly used in the past that adopt.Yet, because on the technology and the restriction of conductor resistance, further reducing parasitic capacitance value by the change on the geometry almost is difficult to, therefore, in the process of making the integrated circuit multilayer lead, people are more and more by adopting various materials with low-k (Low k), to realize the reduction of parasitic capacitance value.
When making the integrated circuit multilayer lead, that adopt usually is dual-damascene structure (DualDamascene).The manufacture method of dual-damascene structure probably can comprise: at first, with reference to figure 1, provide dielectric layer 101 on the semiconductor-based end 100, and dielectric layer 101 is carried out etching, define groove 102 and pore 103; Then, with reference to figure 2, form metal barrier 104, tantalum nitride (TaN) etc. for example is to prevent metal diffusing; Then, with reference to figure 3, plated metal 105; Then, with reference to figure 4, remove the metal outside the trench region.Wherein, form pore after forming groove earlier, or form groove after forming pore earlier, the manufacture method of dual-damascene structure can be divided into groove preferential (Trench First) or pore preferential (Via first) again.
At present, in the process of making described dielectric layer, the most widely used dielectric material with low-k is black diamond material (BD, Black Diamond).BD is a kind of advanced low-k materials based on the chemical vapor carbon deposition doped silicon oxide, and the scope of its dielectric constant k changes according to the doping of carbon.Yet generally speaking, the dielectric material with low-k mostly is organizes loose made from porous material, and hardness is lower.In BD; the ratio of doping carbon is many more, and the dielectric constant of BD is that the k value is just low more, but its hardness is correspondingly also just low more; for example; the k value is that the hardness of 2.7 BD will be lower than the hardness that the k value is 3.0 BD, therefore, and when the BD layer with low-k affords external force; when for example carrying out chemical mechanical milling tech; the particle of grinding agent can form the vestige that scrapes on BD surface, thereby might cause occurring between plain conductor phenomenon such as short circuit, and then influences the performance of device.
Application number is 02108497.1, name is called in " forming the method for stack type dielectric layer at the semiconductor-based end with metal pattern " and discloses a kind of method of making dielectric layer, by forming first dielectric layer at semiconductor-based basal surface, and above described first dielectric layer, form second dielectric layer, the dielectric constant of described second dielectric layer is greater than the dielectric constant of said first dielectric layer, the hardness of described second dielectric layer is greater than the thickness of the hardness of described first dielectric layer and described second dielectric layer thickness less than described first dielectric layer, repeat repeatedly piling up of described first dielectric layer and second dielectric layer, formed dielectric layer with high-k, thereby, avoided in follow-up drawing process, produced in the dielectric layer give vent to anger phenomenon with break.
Yet said method forms the dielectric layer structure that piles up, and causes dielectric constant to increase, and makes parasitic capacitance value raise, and has influenced the transmission performance of device.
Summary of the invention
Yet the technical problem that the present invention solves is to have the lower dielectric material of low-k hardness when forming dielectric layer, and its surface can form the vestige that scrapes, and influences the performance of device.
For solving the problems of the technologies described above, the invention provides a kind of process for making double lineage structure, comprise: in substrate, form first dielectric materials layer and second dielectric materials layer successively, wherein, described second dielectric materials layer covers described first dielectric materials layer, and the hardness of described second dielectric material is greater than the hardness of described first dielectric material; Respectively in described first dielectric materials layer and described second dielectric materials layer, form groove and pore, and in described groove and described pore deposit metallic material; When removing unnecessary metal material, remove the described first dielectric materials layer surface portion or whole described second dielectric materials layers.
Compared with prior art, the present invention has the following advantages: under the situation that does not increase process complexity, reduce the first little dielectric materials layer of hardness by the probability of scratch or wearing and tearing; Guarantee that device not only has excellent dielectric properties, also have high stability, high product yield and good transmission performance.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 to Fig. 4 is the cross-sectional view of process for making double lineage structure in the prior art;
Fig. 5 is the schematic flow sheet of a kind of execution mode of process for making double lineage structure of the present invention;
Fig. 6 is the schematic flow sheet of a step S1 shown in Figure 5 execution mode;
Fig. 7 to Figure 11 is respectively the cross-sectional view of a step S11-step S15 shown in Figure 6 execution mode;
Figure 12 is the schematic flow sheet of a step S2 shown in Figure 5 execution mode;
Figure 13 to Figure 15 is the cross-sectional view of a step S201 shown in Figure 12 execution mode;
Figure 16 is the cross-sectional view of a step S202 shown in Figure 12 execution mode;
Figure 17 to Figure 19 is the cross-sectional view of a step S203 shown in Figure 12 execution mode;
Figure 20 is the cross-sectional view of a step S204 shown in Figure 12 execution mode;
Figure 21 is the cross-sectional view of a step S205 shown in Figure 12 execution mode;
Figure 22 is the cross-sectional view of a step S3 shown in Figure 5 execution mode.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
The invention provides a kind of process for making double lineage structure, in same reative cell, on substrate material layer, form two-layer dielectric materials layer successively with different hardness, it is little and have first dielectric materials layer of low-k to make big second dielectric materials layer of hardness cover hardness, then, in the step of removing excess metal, remove the whole or most of of second dielectric materials layer, keep little and described first dielectric materials layer with low-k of hardness with as dielectric layer, thereby under the situation that does not increase process complexity, reduce the first little dielectric materials layer of hardness by the probability of scratch or wearing and tearing; And, dielectric layer has seldom even do not have the second dielectric material layer segment because comprising, therefore, can have than first dielectric material of low-k to obtain to have dielectric layer by selecting for use than low-k, thereby guarantee that device not only has excellent dielectric properties, also have high stability, high product yield and good transmission performance.
Below in conjunction with the drawings and specific embodiments, the execution mode of process for making double lineage structure of the present invention is further specified.
With reference to figure 5, in a kind of execution mode of process for making double lineage structure of the present invention, at least can comprise: step S1, in substrate, form first dielectric materials layer and second dielectric materials layer successively, wherein, described second dielectric materials layer covers described first dielectric materials layer, and the hardness of described second dielectric material is greater than the hardness of described first dielectric material; Step S2 respectively in described first dielectric materials layer and described second dielectric materials layer, forms groove and pore, and in described groove and described pore deposit metallic material; Step S3 when removing unnecessary metal material, removes the described first dielectric materials layer surface portion or whole described second dielectric materials layers simultaneously.
Specifically, with reference to figure 6, step S1 can comprise: step S11 provides Semiconductor substrate; Step S12 forms metal wiring layer at described Semiconductor substrate upper surface; Step S13 forms the barrier layer on described metal wiring layer; Step S14, upper surface forms first dielectric materials layer on described barrier layer; Step S15 in same reative cell, at the described first dielectric materials layer upper surface, forms second dielectric materials layer that covers described first dielectric materials layer, and the hardness of described second dielectric materials layer is greater than the hardness of described first dielectric materials layer.
Wherein, with reference to figure 7, in step S11, the Semiconductor substrate 200 that is provided can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
With reference to figure 8, in step S12, can adopt physical gas-phase deposition or electroplating technology on Semiconductor substrate 200, to form metal wiring layer 210.Wherein, metal wiring layer 210 can adopt one or more metal materials, for example can adopt in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper one or several.In specific embodiment, because metallic copper has the ability of high-melting-point, low-resistance coefficient and high anti-electron transfer, the material of metal wiring layer 210 can be copper.
With reference to figure 9, in step S13, can adopt chemical vapor deposition method, form barrier layer 220 at the metal line laminar surface, be used for the diffusion of barrier metal.Wherein, the material on described barrier layer 220 can be selected one or more in silicon nitride (SiN), silicon dioxide SiO2, carborundum (SiC), the fire sand (SiCN) for use.
With reference to Figure 10, in step S14, can adopt any technology in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald etc., 220 surfaces form first dielectric materials layer 230 on the barrier layer.Wherein, the material of first dielectric materials layer 230 can be black diamond material B D, and its dielectric constant is 2.7-2.9.
In specific embodiment, can adopt the medium chemical vapor depsotition equipment, the concrete technological parameter that forms first dielectric materials layer 230 can be: reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 4 holders are to 6 holders, interresponse time is 0.4 inch to 0.5 inch, maximum power is 380 watts to 420 watts, minimum power is 85 watts to 95 watts, the flow of oxygen is that per minute 850 standard cubic centimeters are to per minute 950 standard cubic centimeters, the flow of helium is that per minute 1800 standard cubic centimeters are to per minute 2200 standard cubic centimeters, the flow of prestox cyclisation tetrasiloxane (OMCTS) is 2.8 to 3.2 gram/per minutes, sedimentation time is 20 seconds to 25 seconds, and forming thickness is first dielectric materials layer 230 of 2500 dust to 3000 dusts.
With reference to Figure 11, in step S15, in same reaction chamber, can adopt any technology in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald etc., form second dielectric materials layer 240 on first dielectric materials layer, 230 surfaces.Wherein, the material of second dielectric materials layer 240 can be black diamond material B D, and its dielectric constant is 3.0-3.2.
In specific embodiment, when adopting chemical vapour deposition (CVD) to prepare first dielectric materials layer 230, can adopt same medium chemical vapor depsotition equipment, carry out the preparation of second dielectric materials layer 240, wherein, concrete technological parameter can be: reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 4 holders are to 6 holders, interresponse time is 0.33 inch to 0.37 inch, maximum power is 380 watts to 420 watts, minimum power is 85 watts to 95 watts, the flow of oxygen be per minute 850 standard cubic centimeters to per minute 950 standard cubic centimeters, the flow of helium be per minute 1400 standard cubic centimeters to per minute 1600 standard cubic centimeters, the flow of prestox cyclisation tetrasiloxane is 2.3 to 2.6 gram/per minutes, sedimentation time is 7.5 seconds to 8.5 seconds, and forming thickness is second dielectric materials layer 240 of 900 dust to 1100 dusts.
Next,, respectively in described first dielectric materials layer and described second dielectric materials layer, form groove and pore by step S2, and in described groove and described pore deposit metallic material
Wherein, can adopt the preferential mode of pore among the step S2, define pore earlier, define groove then; Or adopt the preferential mode of groove, and define groove earlier, then define pore.With the pore mode of priority is example, and with reference to Figure 12, step S2 specifically can comprise: step S201 defines pore; Step S202 forms first anti-reflecting layer in described pore; Step S203 defines groove; Step S204 removes described first anti-reflecting layer; Step S205 is at the surface deposition metal of described pore and described groove.
In a kind of specific embodiment, Figure 13 to Figure 15 shows the sectional structure chart of implementation step S201.
With reference to Figure 13, at first, at second dielectric materials layer, 240 surperficial spin coating photoresists; Then, by the exposure, with on the mask with the corresponding figure transfer of pore to described photoresist; Then, utilize developer solution that the photoresist of corresponding site is removed,, be used for defining the pore figure of dual-damascene structure to form the first photoresist figure 250.
Then, with reference to Figure 14, be mask with the first photoresist figure 250, etching second dielectric materials layer 240, first dielectric materials layer 230, barrier layer 220 form pore 251 until exposing metal wiring layer 210 successively.
Then, with reference to Figure 15, remove the first photoresist figure 250; Specifically, can adopt chemical reagent to remove technology or cineration technics, to remove the first photoresist figure 250.
Next, in the lump with reference to Figure 12 and Figure 16, execution in step S202, on second dielectric materials layer, 240 surfaces, spin coating makes first anti-reflecting layer 260 fill pore 251 and form level and smooth surface to form first anti-reflecting layer 260.
Then, in the lump with reference to Figure 12, Figure 17 to Figure 19, execution in step S203, wherein, Figure 17 to Figure 19 shows the sectional structure chart of implementation step S203.
With reference to Figure 17, at first, at first anti-reflecting layer, 260 surperficial spin coating photoresists; Then, by the exposure, with on the mask with the corresponding figure transfer of groove to described photoresist; Then, utilize developer solution that the photoresist of corresponding site is removed,, be used for defining the groove figure of dual-damascene structure to form the second photoresist figure 270.
Then, with reference to Figure 18, be mask with the second photoresist figure 270, etching first anti-reflecting layer 260, second dielectric materials layer 240, first dielectric materials layer 230 form groove 271 successively.
Then, with reference to Figure 19, remove the second photoresist figure 270; Specifically, can adopt chemical reagent to remove technology or cineration technics, to remove the second photoresist figure 270.
After forming groove and pore, in the lump with reference to Figure 12 and Figure 20, execution in step S204 specifically, can adopt cineration technics to remove first anti-reflecting layer 260, exposes second dielectric materials layer 240.
On this basis, in the lump with reference to Figure 12 and Figure 21, execution in step S205.Specifically, can pass through a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald, plated metal 280 in described pore and described groove, described metal can be one or several in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper.
In order to guarantee that described pore and described groove are filled up by metal, generally can deposit slightly more metals, thereby make the metal that is deposited exceed described pore or described groove, therefore, need after plated metal system, remove unnecessary metal usually.In the present invention, when removing excess metal, also need to remove described second dielectric materials layer, and control second dielectric material layer thickness of being removed, the described first dielectric material laminar surface is only had extremely hang down described second dielectric materials layer of thickness or do not have described second dielectric materials layer.
In one embodiment, in the lump with reference to figure 5 and Figure 22, in the concrete implementation of step S3, can be according to the thickness of second dielectric materials layer 240, adopt CMP (Chemical Mechanical Polishing) process, remove second dielectric materials layer 240, until the interface of second dielectric materials layer 240 and first dielectric materials layer 230.Because in process of lapping, abrasive particles is only polished to second dielectric materials layer, 240 surfaces on upper strata, do not injure first dielectric materials layer, 230 surfaces of lower floor, and second dielectric materials layer, 240 hardness are bigger, be not subject to abrasive particles influence and produce and scrape, therefore can guarantee that dielectric layer has level and smooth surface.In addition, because second dielectric materials layer 240 most of or all be removed, dielectric layer mainly or all is made up of first dielectric materials layer 230, has lower dielectric constant, and the feasible semiconductor device that is constituted has preferable performance.
In the above-mentioned various execution modes of process for making double lineage structure of the present invention, by forming two-layer dielectric materials layer with different hardness, make second dielectric materials layer cover first dielectric materials layer with less hardness with big hardness, and in the step of follow-up removal excess metal, removal has described second dielectric materials layer whole or most of of big hardness, thereby avoiding owing in the damage that metal removal technology is caused described first dielectric materials layer with less hardness, also do not have influence on the transmission performance of device.
Further, because follow-up removal technology to metal does not contact with described first dielectric materials layer, that is to say, yet even adopt the very low multiple dielectric material of the not high dielectric constant of hardness, can realize that also device has higher yield and stability, thereby break the dielectric material restriction that can't use of prior art low-k because hardness is too small.
On the other hand,, simplified actual mechanical process, saved production cost by second dielectric material that in same reaction chamber, forms first dielectric material and cover described first dielectric material.
Though the present invention by the preferred embodiment explanation as above, these preferred embodiments are not in order to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, should have the ability various corrections and additional are made in this preferred embodiment, and therefore, protection scope of the present invention is as the criterion with the scope of claims.
Claims (9)
1. process for making double lineage structure comprises:
Form first dielectric materials layer and second dielectric materials layer in substrate successively, wherein, described second dielectric materials layer covers described first dielectric materials layer, and the hardness of described second dielectric material is greater than the hardness of described first dielectric material;
In described first dielectric materials layer and described second dielectric materials layer, form groove and pore respectively,
And in described groove and described pore deposit metallic material;
When removing unnecessary metal material, remove the described first dielectric materials layer surface portion or whole described second dielectric materials layers.
2. process for making double lineage structure as claimed in claim 1 is characterized in that, it is 2.7-2.9 that described first dielectric material has dielectric constant, and it is 3.0-3.2 that described second dielectric material has dielectric constant.
3. process for making double lineage structure as claimed in claim 2 is characterized in that, described first dielectric material or described second dielectric material are the black diamond material.
4. process for making double lineage structure as claimed in claim 1 is characterized in that, described first dielectric materials layer and second dielectric materials layer of forming successively in substrate comprises:
Semiconductor substrate is provided;
Form metal wiring layer at described Semiconductor substrate upper surface;
On described metal wiring layer, form the barrier layer;
Upper surface forms first dielectric materials layer on described barrier layer;
In same reative cell,, form second dielectric materials layer that covers described first dielectric materials layer at the described first dielectric materials layer upper surface.
5. process for making double lineage structure as claimed in claim 4, it is characterized in that, describedly form first dielectric materials layer at the barrier layer upper surface and adopt chemical vapor deposition method, reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 4 holders are to 6 holders, interresponse time is 0.4 inch to 0.5 inch, maximum power is 380 watts to 420 watts, minimum power is 85 watts to 95 watts, the flow of oxygen is that per minute 850 standard cubic centimeters are to per minute 950 standard cubic centimeters, the flow of helium is that per minute 1800 standard cubic centimeters are to per minute 2200 standard cubic centimeters, the flow of prestox cyclisation tetrasiloxane is per minute 2.8 to 3.2 grams, and sedimentation time is 20 seconds to 25 seconds.
6. process for making double lineage structure as claimed in claim 5 is characterized in that, the thickness of described first dielectric materials layer is 2500 dust to 3000 dusts.
7. process for making double lineage structure as claimed in claim 4, it is characterized in that, described second dielectric materials layer employing chemical vapor deposition method that in same reative cell, forms described first dielectric materials layer of covering at the described first dielectric materials layer upper surface, reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 4 holders are to 6 holders, interresponse time is 0.33 inch to 0.37 inch, maximum power is 380 watts to 420 watts, minimum power is 85 watts to 95 watts, the flow of oxygen is that per minute 850 standard cubic centimeters are to per minute 950 standard cubic centimeters, the flow of helium is that per minute 1400 standard cubic centimeters are to per minute 1600 standard cubic centimeters, the flow of prestox cyclisation tetrasiloxane is per minute 2.3 to 2.6 grams, and sedimentation time is 7.5 seconds to 8.5 seconds.
8. process for making double lineage structure as claimed in claim 7 is characterized in that, the thickness of described second dielectric materials layer is 900 dust to 1100 dusts.
9. process for making double lineage structure as claimed in claim 1 is characterized in that, removes described second dielectric materials layer in the time of the unnecessary metal material of described removal and adopts CMP (Chemical Mechanical Polishing) process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910194919.8A CN102005409B (en) | 2009-08-31 | 2009-08-31 | Preparation method of dual damascene structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910194919.8A CN102005409B (en) | 2009-08-31 | 2009-08-31 | Preparation method of dual damascene structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102005409A true CN102005409A (en) | 2011-04-06 |
| CN102005409B CN102005409B (en) | 2014-01-08 |
Family
ID=43812656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910194919.8A Expired - Fee Related CN102005409B (en) | 2009-08-31 | 2009-08-31 | Preparation method of dual damascene structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102005409B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103105736A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Photolithography method and etching method |
| CN104576356A (en) * | 2013-10-22 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW516181B (en) * | 2001-12-31 | 2003-01-01 | Min Shr | Manufacturing method of semiconductor device dual damascene structure |
| US20050124151A1 (en) * | 2003-12-04 | 2005-06-09 | Taiwan Semiconductor Manufacturing Co. | Novel method to deposit carbon doped SiO2 films with improved film quality |
-
2009
- 2009-08-31 CN CN200910194919.8A patent/CN102005409B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103105736A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Photolithography method and etching method |
| CN104576356A (en) * | 2013-10-22 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method |
| CN104576356B (en) * | 2013-10-22 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of chemical mechanical grinding |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102005409B (en) | 2014-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20200235104A1 (en) | Cap Layer For Bit Line Resistance Reduction | |
| CN100372097C (en) | Method of selectively making uniform copper interconnect layer using plating technology | |
| US6503827B1 (en) | Method of reducing planarization defects | |
| CN102044475A (en) | Interconnecting structure and forming method thereof | |
| US6908863B2 (en) | Sacrificial dielectric planarization layer | |
| CN102054761A (en) | Semiconductor structure and method for forming dual-damascene structure | |
| US20200161180A1 (en) | Tall trenches for via chamferless and self forming barrier | |
| US20230361164A1 (en) | Metal-insulator-metal capacitor and methods of manufacturing | |
| CN101989570A (en) | Forming method of contact hole structure | |
| JP4987254B2 (en) | Manufacturing method of semiconductor device | |
| KR100385112B1 (en) | Process of manufacturing semiconductor device | |
| CN102005409B (en) | Preparation method of dual damascene structure | |
| CN100423226C (en) | Method for producing double embedded structure | |
| CN102054762B (en) | Semiconductor structure and method for forming dual-damascene structure | |
| CN102130036B (en) | Method for producing shallow trench isolating structure | |
| CN102054755A (en) | Interconnecting structure and formation method thereof | |
| TW200945491A (en) | Method for fabricating a semiconductor device | |
| CN102013410A (en) | Inductance element and forming method thereof | |
| CN101562147A (en) | Method for removing residual defects | |
| CN101996927A (en) | Multilayer interconnection structure and forming method thereof | |
| US11211254B2 (en) | Process for integrated circuit fabrication using a buffer layer as a stop for chemical mechanical polishing of a coupled dielectric oxide layer | |
| US20060157851A1 (en) | Semiconductor device and method for manufacturing the same | |
| CN102034733A (en) | Interconnecting structure and forming method thereof | |
| CN114121809A (en) | Methods for forming memory devices and associated devices and systems | |
| CN101996929A (en) | Forming method of dual-damascene structure and semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121029 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121029 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140108 Termination date: 20200831 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |