CN102117478A - Real-time processing method and system for batch image data - Google Patents
Real-time processing method and system for batch image data Download PDFInfo
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Abstract
The invention relates to a real-time processing method and system for batch image data. The method comprises the following steps of: performing signal conversion on data transmitted by an industrial filed to obtain valid signals of frames and rows, pixel clocks and 24-bit parallel image data, wherein four pixel points in the image data of each row form a group; latching four pixel point data of pixels of each group by using four 24-bit latches; and latching 96-bit valid data in the four 24-bit latches by using three 32-bit latches, transmitting the data to three 32-bit buffers for caching, uploading the data to the left port of a 32-bit double-port SRAM (Static Random Access Memory), reading the data of the whole row from the right port of the SRAM by an embedded controller, storing the data in a 32-bit SDRAM (Synchronous Dynamic Random Access Memory) to form a frame of image data, and processing the image data. The 24-bit data of the pixel points are recombined through a hardware circuit, so that the increment of 8-bit higher redundant data in the 32-bit memory is avoided, the data processing quantity of the image of each frame is reduced, the batch image processing efficiency is greatly improved, and real-time processing of the batch image data is realized.
Description
Technical field
The invention belongs to industrial control field, relate to the method and system that a kind of serial high speed image data in enormous quantities that industry spot is produced is handled in real time.
Background technology
In the different fine sorter of cotton, master controller needs to put in order frame data and is sent to host computer simultaneously when cotton view data in enormous quantities is handled in real time, so that adjust the vision facilities parameter, and the monitoring running status.Yet different fine sorter begins to adopt embedded controller as master controller at present.Unfortunately, many embedded controllers are difficult to handle in real time and Network Transmission after receiving every frame image data.This mainly is owing to following reason: the one, and embedded master controller mainly is to utilize the interframe time to carry out data processing and Network Transmission, and the time between picture frame is shorter, thereby handle with the time of Network Transmission shorter in real time; The 2nd, every frame image data amount is bigger, and processing and Network Transmission need spend the more time in real time.For this reason, the cotton sorter has adopted the method for taking out frame to solve this problem at present, but this method has not only influenced the control performance of system, nor is beneficial to real-time monitoring.
Therefore, need develop the real-time treatment circuit of view data in enormous quantities at this field, so that stay real-time processing and Network Transmission that time enough is used to finish view data.
The industrial camera of using in the present different fine sorter of cotton, such as German BASLER L304kc video camera, in the RGB method for expressing that uses at present, the RGB data of each pixel are all represented by 8 bits, need 24 bit data altogether, but different fine sorter need carry out Flame Image Process, control and Network Transmission in real time, thereby need to select 32 high-grade 8-digit microcontrollers as master controller, 32 RAM storer is kept in data line, and 32 SDRAM keeps in frame data.At not matching of view data figure place and storer and microcontroller figure place, in present disposal route, be that the most-significant byte of 32 bit memories is put 0, carry out access together with 24 bit image data then and handle.Though this method for designing has been simplified circuit, using the dma mode will to go view data when RAM copies to SDRAM, so because addressing continuously has increased by 8 redundant digits, view data is handled and the time of Network Transmission thereby increased.Deficiency at this method for designing, we have proposed a kind of hardware circuit design method, and the view data of 4 24 pixels of every reception is just formed 3 32 bit data with it, store then and transmit, view data is handled and the time of Network Transmission thereby reduced.
Summary of the invention
The real-time processing method and the system that the purpose of this invention is to provide a kind of batch images data, with solve existing method and system be difficult to the great amount of images data that receive handle in real time, the problem of control in real time and Network Transmission.
For achieving the above object, the real time processing system of batch images data of the present invention comprises:
Signal conversion module, the high speed serialization view data that is used for coming from industry spot is converted to 28 TTL/COMS level signals;
1 24 digit buffer is used to cushion the view data of 24 bit parallels;
4 24 latchs are used to latch 1 picture group image signal, so that handle by group; Wherein each 24 latch is used to latch 24 bit data signals of each pixel;
3 32 latchs are used to latch 96 bit data signals of every group of pixel;
3 32 digit buffers are used to control 32 bit image data writing to dual-port SRAM;
Frequency divider and 3 chronotrons are used to obtain required clock signal;
1 10 digit counter is used to obtain the low 10 bit address signals of dual-port SRAM;
1 32 dual-port SRAM is divided into bottom half, and last bottom half can be stored 1 row view data;
1 32 embedded controller is used for reading the data of 32 dual-port SRAM and data is handled;
1 SDRAM is used for temporary 1 frame image data;
24 bit image data of described signal conversion module output are imported in 24 digit buffers, the output terminal of this 24 digit buffer is connected into the input end of 4 24 latchs respectively, the corresponding respectively input end that is connected into 3 32 latchs of the output terminal of these 4 24 latchs, the corresponding respectively input end that is connected into 3 32 digit buffers of the output terminal of these 3 32 latchs, the output terminal of these 3 32 digit buffers all is connected into the left FPDP of 32 dual-port SRAM, the output terminal of these 32 dual-port SRAM is connected into the input end of embedded controller, and the output terminal of this embedded controller links to each other with the input end of SDRAM; The pixel clock of described signal conversion module output and frame, row useful signal are imported in the frequency divider respectively, the output terminal of this frequency divider is connected into the input end of 3 chronotrons respectively, the output terminal of one chronotron is connected into the input end of 10 digit counters, and the output terminal of this 10 digit counter is connected into the left address port of 32 dual-port SRAM.
Further, system also comprises 1 digit counter, is used to obtain the 10th bit address signal of dual-port SRAM, and the input end of this 1 digit counter is connected with frame, row useful signal, and output terminal is connected into the input end of 32 dual-port SRAM.
Further, described 3 chronotrons are respectively first, second, third chronotron, the output of described frequency divider is connected into first, second chronotron respectively, the output of first chronotron is connected into 4 24 latchs respectively, the output of described second chronotron is connected into the input end of 3 32 latchs respectively, the output of described second chronotron is through being connected into the input end of the 3rd chronotron after handling with door or door, the output of the 3rd chronotron is connected into the input end of 10 digit counters.
Further, described these 4 24 latchs are first, two, three, quad latch, described 3 32 latchs are first, two, three latchs, the corresponding respectively input end that is connected into 3 32 latchs of the output terminal of described 4 24 latchs is meant that the output terminal of the one 24 latch is connected into the input end of the one 32 latch, the output terminal of the 2 24 latch is connected into first respectively, the input end of 2 32 latchs, the output terminal of the 3 24 latch is connected into second, the input end of 3 32 latchs, the output terminal of the 4 24 latch is connected into the input end of the 3 32 latch.
The method of utilizing real time processing system to carry out the processing of batch images data in real time of the present invention may further comprise the steps:
(1) the signal conversion module view data and the synchronizing signal that will come from industry spot is converted to 28 TTL/COMS level signals, thereby obtains frame, row useful signal, pixel clock and 24 bit parallel view data simultaneously;
(2) when detecting frame, when the row useful signal exists simultaneously, pixel clock being carried out frequency division and time-delay, produce the latches signal, impact damper enable signal sum counter count pulse; When detect frame, the row useful signal exists, but when the row useful signal finished, 1 digit counter work changed the 10th bit address of SRAM, returns for (1) step; When not detecting the end of frame useful signal or frame useful signal or not detecting capable useful signal, returned for (1) step;
(3) 24 digit buffers buffering is through 24 bit image data of signal conversion module, per four pixels are one group, when 24 bit data of 4 pixels arrive, utilize latch signal, use 24 signals of four pixels in every group of 4 24 latches in turn;
(4) utilize latch signal, use 24 signals of each pixel in every group of 3 32 latches in turn;
(5) utilize the impact damper enable signal, in turn in metadata cache to 3 32 digit buffer with 3 32 latchs outputs;
(6) output of rolling counters forward pulse is imported as the left port address of 32 dual-port SRAM, the output of 3 32 digit buffers is imported as the left port data of 32 dual-port SRAM, thereby the output of 3 32 digit buffers is write among the dual-port SRAM;
(7) repeating step (1) is to (6), up to data line all being write among 32 dual-port SRAM;
(8) 32 embedded controllers are deposited to 32 SDRAM with dma mode reading of data from 32 dual-port SRAM, handle so that form frame data.
Further, the acquisition of latches signal is meant in the described step (2), in case detect effective frame useful signal and row useful signal, promptly pixel clock is carried out frequency division and time-delay, 4 frequency-dividing clocks that obtain 4 frequency-dividing clocks of time-delay 0 pixel period, 4 frequency-dividing clocks of time-delay 1 pixel period, 4 frequency-dividing clocks of time-delay 2 pixel period and 3 pixel period of delaying time are respectively in turn as the latch signal of 4 24 latchs; Obtain the latch signal of 4 frequency-dividing clocks of 4 frequency-dividing clocks of time-delay 1.5 pixel period, 4 frequency-dividing clocks of time-delay 2.5 pixel period and 3.5 pixel period of delaying time as 3 32 latchs; 4 frequency-dividing clocks of 4 frequency-dividing clocks of 1.5 pixel period of will delaying time simultaneously, time-delay 4 frequency-dividing clocks of 2.5 pixel period and 3.5 pixel period of delaying time are by priority encoder, and its three outputs are respectively as the enable signal of these 3 32 digit buffers; By with goalkeeper delay time 2.5 pixel period and the time-delay 3.5 pixel period 4 frequency-dividing clocks respectively with pixel clock with, obtain two in four times of pixel period, have two rising edges pulse signal, with above two with the output of signal mutually or, acquisition in four times of pixel period, have three rising edges pulse signal, and 0.5 pixel period of delaying time is as the input of 10 digit counters, thereby obtains the rolling counters forward pulse.
Further, in the described step (3) in every group of 4 24 latches 24 signals of four pixels specifically be, when 24 bit data of first pixel arrive, 4 frequency-dividing clocks that utilize time-delay 0 pixel period use 24 signals of the one 24 this pixel of latches as latch signal; When 24 bit data of second pixel arrived, 4 frequency-dividing clocks that utilize time-delay 1 pixel period used 24 signals of the 2 24 this pixel of latches as latch signal; When 24 bit data of the 3rd pixel arrived, 4 frequency-dividing clocks that utilize time-delay 2 pixel period used 24 signals of the 3 24 this pixel of latches as latch signal; When 24 bit data of the 4th pixel arrived, 4 frequency-dividing clocks that utilize time-delay 3 pixel period used 24 signals of the 4 24 this pixel of latches as latch signal.
Further, use in the described step (4) 24 signals of each pixel in every group of 3 32 latches to be meant, when two 24 latches first and second pixel numbers according to after, 4 sub-frequency clock signals of 1.5 pixel period latch 24 valid data of first pixel and the least-significant byte valid data of second pixel when using 32 latch utilizations time-delays; When two 24 latches second and the 3rd pixel number according to after, 4 sub-frequency clock signals of 2.5 pixel period latch high 16 valid data of second pixel and low 16 valid data of the 3rd pixel when using another 32 latch utilizations time-delays; When two 24 latches third and fourth pixel number according to after, 4 sub-frequency clock signals of 3.5 pixel period latch the most-significant byte valid data of the 3rd pixel and 24 valid data of the 4th pixel when using another 32 latch utilizations time-delays.
Further, embedded controller reading of data from 32 dual-port SRAM is meant that specifically 32 dual-port SRAM addressing ranges are 2k in the described step (8), and bottom half on the five equilibrium makes bottom half all can hold delegation's view data; 1 digit counter be input as capable useful signal, output writes upper half or bottom half as the 10th bit address of 32 dual-port SRAM with determination data; Embedded controller still is bottom half peek with decision from upper half by the rising edge of row useful signal is counted; In case upper half or bottom half write data line, then 32 embedded controllers can take out data from the right output port of 32 dual-port SRAM, are temporarily stored among the SDRAM.
Further, when embedded controller was peeked from upper half, system write the next line data from trend SRAM bottom half; When embedded controller was peeked from bottom half, system write the next line data from trend SRAM upper half; Finish in case embedded controller detects the frame useful signal, immediately this frame is carried out data processing and Network Transmission.
Batch images data in real time disposal route of the present invention and system, reconfigure 24 bit data of pixel by hardware circuit, avoided in 32 bit memories, increasing the redundant data of most-significant byte, reduced the data processing amount of every two field picture, improve the efficient that batch images is handled widely, realized the real-time processing of batch images data; Embedded controller carries out the time of view data processing and Network Transmission in the existing equipment by reducing, thereby guarantees that controller has time enough to finish the Network Transmission of view data and control in real time.
Description of drawings
Fig. 1 is a systematic schematic diagram of the present invention;
Fig. 2 is a method flow diagram of the present invention.
Embodiment
The real time processing system and the method for batch images data are used for the different fine sorter of cotton, and specific embodiment is as follows:
The real time processing system principle of batch images data as shown in Figure 1, this system mainly comprises:
Signal conversion module, the high speed serialization view data that is used for coming from industry spot is converted to 28 TTL/COMS level signals;
1 24 digit buffer is used to cushion the view data of 24 bit parallels;
First, second, third and fourth 24 latchs promptly are respectively 24 latchs 1,2,3,4, are used to latch 1 picture group image signal, so that handle by group; Wherein each 24 latch is used to latch 24 bit data signals of each pixel;
First, second and third 32 latchs promptly are respectively 32 latchs 1,2,3, are used to latch 96 bit data signals of every group of pixel;
First, second and third 32 digit buffer promptly is respectively 32 digit buffers 1,2,3, is used to control 32 bit image data writing to dual-port SRAM;
Frequency divider and 3 chronotrons are used to obtain required clock signal, and 3 chronotrons are respectively first, second, third chronotron and promptly are respectively chronotron 1,2,3;
1 10 digit counter is used to obtain the low 10 bit address signals of dual-port SRAM;
1 32 dual-port SRAM(Static Random Access Memory, static RAM), being divided into bottom half, last bottom half can be stored 1 row view data;
1 32 embedded controller is used for reading the data of 32 dual-port SRAM and data is handled;
1 32 SDRAM(Synchronous Dynamic Random Access Memory, synchronous DRAM), be used for temporary 1 frame image data;
1 digit counter is used to obtain the 10th bit address signal of dual-port SRAM;
24 bit image data of signal conversion module output are imported in 24 digit buffers, the output terminal of this 24 digit buffer is connected into the input end of 4 24 latchs respectively, wherein, the output terminal of 24 latchs 1 is connected into the input end of 32 latchs 1, the output terminal of 24 latchs 2 is connected into 32 latchs 1 respectively, 2 input end, the output terminal of 24 latchs 3 is connected into 32 latchs 2,3 input end, the output terminal of 24 latchs 4 is connected into the input end of 32 latchs 3, the corresponding respectively input end that is connected into 3 32 digit buffers of the output terminal of these 3 32 latchs, the output terminal of these 3 32 digit buffers all is connected into the left FPDP of 32 dual-port SRAM, the output terminal of these 32 dual-port SRAM is connected into the input end of embedded controller, and the output terminal of this embedded controller links to each other with the input end of SDRAM; The pixel clock of described signal conversion module output and frame, row useful signal are imported in the frequency divider respectively, the output terminal of this frequency divider is connected into the input end of 3 chronotrons respectively, the output terminal of chronotron 3 is connected into the input end of 10 digit counters, and the output terminal of this 10 digit counter is connected into the 0-9 position of the left address port of 32 dual-port SRAM.
The input end of 1 digit counter is connected with frame, row useful signal, and output terminal is connected into the input end of 32 dual-port SRAM.
The output of frequency divider is connected into chronotron 1,2 respectively, the output of chronotron 1 is connected into 4 24 latchs respectively, the output of chronotron 2 is connected into the input end of 3 32 latchs respectively, the output of chronotron 2 is through being connected into the input end of chronotron 3 after handling with door or door, the output of this chronotron 3 is connected into the input end of 10 digit counters.
The step of the real-time processing method that carries out based on the real time processing system of above batch images data is as follows:
Step 1: 5 pairs of LVDS conversion of signals that comprise view data and synchronizing signal that Camera Link bus is transmitted are 28 TTL/COMS level signals, thereby obtain frame useful signal, row useful signal, pixel clock and 24 bit parallel data simultaneously.
Step 2: in case detect effective frame useful signal and row useful signal, promptly pixel clock is carried out frequency division, obtain 4 frequency divisions of pixel clock; When detecting frame, when the row useful signal exists simultaneously, pixel clock being carried out frequency division and time-delay, produce the latches signal, impact damper enable signal sum counter count pulse; When detect frame, the row useful signal exists, but when the row useful signal finished, 1 digit counter work changed the 10th bit address of SRAM, returns for (1) step; When not detecting the end of frame useful signal or frame useful signal or not detecting capable useful signal, returned for (1) step;
The acquisition of latches signal is meant, use 1 pair 4 frequency-dividing clock of chronotron to delay time, 4 frequency-dividing clocks of obtain delaying time 4 frequency-dividing clocks of 0 pixel period, 4 frequency-dividing clocks of time-delay 1 pixel period, 4 frequency-dividing clocks of time-delay 2 pixel period and 3 pixel period of delaying time are respectively in turn as the latch signal of 4 24 latchs; Use 2 pairs 4 frequency-dividing clocks of chronotron to delay time, 4 frequency-dividing clocks of obtain delaying time 4 frequency-dividing clocks of 1.5 pixel period, 4 frequency-dividing clocks of time-delay 2.5 pixel period and 3.5 pixel period of delaying time are as the latch signal of 3 32 latchs;
4 frequency-dividing clocks of 4 frequency-dividing clocks of 1.5 pixel period of will delaying time simultaneously, time-delay 4 frequency-dividing clocks of 2.5 pixel period and 3.5 pixel period of delaying time are by priority encoder, and its three outputs are respectively as the enable signal of these 3 32 digit buffers; By with door 1 will delay time 2.5 pixel period 4 frequency-dividing clocks respectively with pixel clock with, obtain in four times of pixel period, to have two rising edges pulse signal; By with door 2 will delay time 4 frequency-dividing clocks of 3.5 pixel period and pixel clock with, obtain in four times of pixel period, to have two rising edges pulse signal; Since with the output of door 2 than with pixel period of lag output of door 1, with both mutually or after, obtain in four times of pixel period, to have three rising edges pulse signal; And 0.5 pixel period of delaying time is as the input of 10 digit counters, thereby obtains the rolling counters forward pulse.
Because the every row of German BASLER L304kc video camera has 4080 pixels, therefore every capable view data can be divided into 1024 groups, and every group of 4 pixels at each group data, are finished following steps:
Step 3: the 24 bit image data of changing acquisition by the unserializing of signal conversion module are imported 24 digit buffers cushion;
Step 4: when 24 bit data of first pixel arrived, 4 frequency-dividing clocks that utilize time-delay 0 pixel period made 24 latchs 1 latch 24 signals of this pixel as latch signal; When 24 bit data of second pixel arrived, 4 frequency-dividing clocks that utilize time-delay 1 pixel period made 24 latchs 2 latch 24 signals of this pixel as latch signal; When 24 bit data of the 3rd pixel arrived, 4 frequency-dividing clocks that utilize time-delay 2 pixel period made 24 latchs 3 latch 24 signals of this pixel as latch signal; When 24 bit data of the 4th pixel arrived, 4 frequency-dividing clocks that utilize time-delay 3 pixel period made 24 latchs 4 latch 24 signals of this pixel as latch signal;
Step 5: when 24 latchs 1 and 24 latchs 2 latched first and second pixel numbers according to after, 4 sub-frequency clock signals of 1.5 pixel period latched 24 valid data of first pixel and the least-significant byte valid data of second pixel when 32 latchs 1 utilized time-delay; When 24 latchs 2 and 24 latchs 3 latched second and the 3rd pixel number according to after, 4 sub-frequency clock signals of 2.5 pixel period latched high 16 valid data of second pixel and low 16 valid data of the 3rd pixel when 32 latchs 2 utilized time-delay; When 24 latchs 3 and 24 latchs 4 latched third and fourth pixel number according to after, 4 sub-frequency clock signals of 3.5 pixel period latched the most-significant byte valid data of the 3rd pixel and 24 valid data of the 4th pixel when 32 latchs 3 utilized time-delay;
Step 6: 4 frequency-dividing clocks of 1.5 pixel period of will delaying time, 4 frequency-dividing clocks of time-delay 2.5 pixel period and 4 frequency-dividing clocks of 3.5 pixel period of delaying time pass through priority encoder, its three outputs are respectively as the enable signal of 32 digit buffers, 1,32 digit buffers 2 and 32 digit buffers 3, thereby have guaranteed that each has only an impact damper to enable constantly; 3 outputs of priority encoder as or the input of door 1, or the door 1 left port enable signal that is output as 32 dual-port SRAM;
Step 7: will or door 2 output 0.5 pixel period of delaying time, thereby produced suitable time clock, input as 10 digit counters, the output of 10 digit counters is as the left port address input of 32 dual-port SRAM, the output of 32 digit buffers, 1,32 digit buffers 2 and 32 digit buffers 3 is imported as the left port data of 32 dual-port SRAM, thereby the output of 3 32 digit buffers is write among two dual-port SRAM;
Step 8: by above step the data of 4 pixels have been written to 32 dual-port SRAM, have repeated above step, just data line all can have been write 32 dual-port SRAM;
Step 9:32 position dual-port SRAM addressing range is 2k, and last bottom half is 1k, all can hold delegation's view data.1 digit counter be input as capable useful signal, output is as the 10th bit address of 32 dual-port SRAM, thereby determined data to write upper half or bottom half;
Step 10:32 position embedded controller still is bottom half peek with decision from upper half by the rising edge of row useful signal is counted.In case upper half or bottom half write data line, then 32 embedded controllers can take out data from the right output port of 32 dual-port SRAM, are temporarily stored among its peripheral SDRAM;
Step 11:32 position embedded controller is when upper half is peeked, and system writes the next line data from trend SRAM bottom half.32 embedded controllers are when bottom half is peeked, and system writes the next line data from trend SRAM upper half.Finish in case 32 embedded controllers detect the frame useful signal, immediately this frame is carried out data processing and Network Transmission.
By above step, 32 embedded controllers will not have the whole frame image data of redundant data bits to store among the peripheral SDRAM separately, than existing image data storage mode with most-significant byte zero setting, reduced by 1/4 transmission time, thereby made 32 embedded controllers have more time to carry out the real-time processing and the Network Transmission of data.
Fig. 2 is the data flowchart of the embodiment of the invention, and details are as follows:
In step 201, by conversion of signals, 5 pairs of LVDS conversion of signals that comprise view data and synchronizing signal that Camera Link bus is transmitted are 28 TTL/COMS level signals;
In step 202, obtain frame useful signal, row useful signal, pixel clock and 24 bit parallel data simultaneously;
In step 203, judge whether to receive the frame useful signal, if receive, carry out step 204, otherwise forward step 202 to;
In step 204, whether the judgment frame useful signal finishes, if finish, and execution in step 202, otherwise forward step 205 to;
In step 205, judge whether to receive capable useful signal, if receive, execution in step 206 and 207, otherwise forward step 202 to;
In step 206, utilize frequency divider, chronotron, priority encoder, with door and or the required latches signal of door generation system, impact damper enable signal, rolling counters forward pulse;
In step 207, judge whether the row useful signal finishes, if do not finish, execution in step 209, otherwise forward step 202 and execution in step 208 to;
In step 208,1 binary counter has the useful signal counting to row, thereby has changed the 10th bit address of SRAM, and promptly determination data is stored in upper half or the bottom half of SRAM;
In step 209 in step 212, because 4 pixels are formed 1 group, these four steps are that 24 bit data with first pixel latch into 24 latchs 1,24 bit data of second pixel are latched into 24 latchs 2,24 bit data of the 3rd pixel are latched into 24 latchs 3,24 bit data of the 4th pixel are latched into 24 latchs 4;
In step 213 in step 215,24 valid data of first pixel and the least-significant byte valid data of second pixel are latched into 32 latchs 1, high 16 valid data of second pixel and low 16 valid data of the 3rd pixel are latched into 32 latchs 2, the most-significant byte valid data of the 3rd pixel and 24 valid data of the 3rd pixel are latched into 32 latchs 3;
In step 218, successively open 32 digit buffers, 1,32 digit buffers 2 and 32 digit buffers 3 in step 216, the data of 4 pixels are write in 12 addresses of dual-port SRAM.Because mostly 32 position embedded controllers are byte addressing, thereby have whenever write 32 bit data, the address need add 4.
Claims (10)
1. the real time processing system of batch images data is characterized in that, this system comprises:
Signal conversion module, the high speed serialization view data that is used for coming from industry spot is converted to 28 TTL/COMS level signals;
1 24 digit buffer is used to cushion the view data of 24 bit parallels;
4 24 latchs are used to latch 1 picture group image signal, so that handle by group; Wherein each 24 latch is used to latch 24 bit data signals of each pixel;
3 32 latchs are used to latch 96 bit data signals of every group of pixel;
3 32 digit buffers are used to control 32 bit image data writing to dual-port SRAM;
Frequency divider and 3 chronotrons are used to obtain required clock signal;
1 10 digit counter is used to obtain the low 10 bit address signals of dual-port SRAM;
1 32 dual-port SRAM is divided into bottom half, and last bottom half can be stored 1 row view data;
1 32 embedded controller is used for reading the data of 32 dual-port SRAM and data is handled;
1 32 SDRAM is used for temporary 1 frame image data;
24 bit image data of described signal conversion module output are imported in 24 digit buffers, the output terminal of this 24 digit buffer is connected into the input end of 4 24 latchs respectively, the corresponding respectively input end that is connected into 3 32 latchs of the output terminal of these 4 24 latchs, the corresponding respectively input end that is connected into 3 32 digit buffers of the output terminal of these 3 32 latchs, the output terminal of these 3 32 digit buffers all is connected into the left FPDP of 32 dual-port SRAM, the output terminal of these 32 dual-port SRAM is connected into the input end of 32 embedded controllers, and the output terminal of this embedded controller links to each other with the input end of SDRAM; The pixel clock of described signal conversion module output and frame, row useful signal are imported in the frequency divider respectively, the output terminal of this frequency divider is connected into the input end of 3 chronotrons respectively, the output terminal of one chronotron is connected into the input end of 10 digit counters, and the output terminal of this 10 digit counter is connected into the 0-9 position of the left address port of 32 dual-port SRAM.
2. the real time processing system of batch images data according to claim 1, it is characterized in that: system also comprises 1 digit counter, be used to obtain the 10th bit address signal of dual-port SRAM, the input end of this 1 digit counter is connected with frame, row useful signal, and output terminal is connected into the input end of 32 dual-port SRAM.
3. the real time processing system of batch images data according to claim 1, it is characterized in that: described 3 chronotrons are respectively first, second, third chronotron, the output of described frequency divider is connected into first, second chronotron respectively, the output of first chronotron is connected into 4 24 latchs respectively, the output of described second chronotron is connected into the input end of 3 32 latchs respectively, the output of described second chronotron is through being connected into the input end of the 3rd chronotron after handling with door or door, the output of the 3rd chronotron is connected into the input end of 10 digit counters.
4. according to the real time processing system of each described batch images data among the claim 1-3, it is characterized in that: described these 4 24 latchs are first, two, three, quad latch, described 3 32 latchs are first, two, three latchs, the corresponding respectively input end that is connected into 3 32 latchs of the output terminal of described 4 24 latchs is meant that the output terminal of the one 24 latch is connected into the input end of the one 32 latch, the output terminal of the 2 24 latch is connected into first respectively, the input end of 2 32 latchs, the output terminal of the 3 24 latch is connected into second, the input end of 3 32 latchs, the output terminal of the 4 24 latch is connected into the input end of the 3 32 latch.
5. utilize the described real time processing system of claim 1 to carry out the method that the batch images data in real time is handled, it is characterized in that, may further comprise the steps:
(1) the signal conversion module view data and the synchronizing signal that will come from industry spot is converted to 28 TTL/COMS level signals, thereby obtains frame, row useful signal, pixel clock and 24 bit parallel view data simultaneously;
(2) when detecting frame, when the row useful signal exists simultaneously, pixel clock being carried out frequency division and time-delay, produce the latches signal, impact damper enable signal sum counter count pulse; When detect frame, the row useful signal exists, but when the row useful signal finished, 1 digit counter work changed the 10th bit address of SRAM, returns for (1) step; When not detecting the end of frame useful signal or frame useful signal or not detecting capable useful signal, returned for (1) step;
(3) 24 digit buffers buffering is through 24 bit image data of signal conversion module, per four pixels are one group, when 24 bit data of 4 pixels arrive, utilize latch signal, use 24 signals of four pixels in every group of 4 24 latches in turn;
(4) utilize latch signal, use 24 signals of each pixel in every group of 3 32 latches in turn;
(5) utilize the impact damper enable signal, in turn in metadata cache to 3 32 digit buffer with 3 32 latchs outputs;
(6) output of rolling counters forward pulse is imported as the left port address of 32 dual-port SRAM, the output of 3 32 digit buffers is imported as the left port data of 32 dual-port SRAM, thereby the output of 3 32 digit buffers is write among the dual-port SRAM;
(7) repeating step (1) is to (6), up to data line all being write among 32 dual-port SRAM;
(8) 32 embedded controllers reading of data from 32 dual-port SRAM is deposited to 32 SDRAM.
6. method according to claim 5, it is characterized in that: the acquisition of latches signal is meant in the described step (2), in case detect effective frame useful signal and row useful signal, promptly pixel clock is carried out frequency division and time-delay, 4 frequency-dividing clocks that obtain 4 frequency-dividing clocks of time-delay 0 pixel period, 4 frequency-dividing clocks of time-delay 1 pixel period, 4 frequency-dividing clocks of time-delay 2 pixel period and 3 pixel period of delaying time are respectively in turn as the latch signal of 4 24 latchs; Obtain the latch signal of 4 frequency-dividing clocks of 4 frequency-dividing clocks of time-delay 1.5 pixel period, 4 frequency-dividing clocks of time-delay 2.5 pixel period and 3.5 pixel period of delaying time as 3 32 latchs; 4 frequency-dividing clocks of 4 frequency-dividing clocks of 1.5 pixel period of will delaying time simultaneously, time-delay 4 frequency-dividing clocks of 2.5 pixel period and 3.5 pixel period of delaying time are by priority encoder, and its three outputs are respectively as the enable signal of these 3 32 digit buffers; By with goalkeeper delay time 2.5 pixel period and the time-delay 3.5 pixel period 4 frequency-dividing clocks respectively with pixel clock with, obtain two in four times of pixel period, have two rising edges pulse signal, with above two with the output of signal mutually or, acquisition in four times of pixel period, have three rising edges pulse signal, and 0.5 pixel period of delaying time is as the input of 10 digit counters, thereby obtains the rolling counters forward pulse.
7. method according to claim 6, it is characterized in that: in the described step (3) in every group of 4 24 latches 24 signals of four pixels specifically be, when 24 bit data of first pixel arrive, 4 frequency-dividing clocks that utilize time-delay 0 pixel period use 24 signals of the one 24 this pixel of latches as latch signal; When 24 bit data of second pixel arrived, 4 frequency-dividing clocks that utilize time-delay 1 pixel period used 24 signals of the 2 24 this pixel of latches as latch signal; When 24 bit data of the 3rd pixel arrived, 4 frequency-dividing clocks that utilize time-delay 2 pixel period used 24 signals of the 3 24 this pixel of latches as latch signal; When 24 bit data of the 4th pixel arrived, 4 frequency-dividing clocks that utilize time-delay 3 pixel period used 24 signals of the 4 24 this pixel of latches as latch signal.
8. method according to claim 7, it is characterized in that: use in the described step (4) 24 signals of each pixel in every group of 3 32 latches to be meant, when two 24 latches first and second pixel numbers according to after, 4 sub-frequency clock signals of 1.5 pixel period latch 24 valid data of first pixel and the least-significant byte valid data of second pixel when using 32 latch utilizations time-delays; When two 24 latches second and the 3rd pixel number according to after, 4 sub-frequency clock signals of 2.5 pixel period latch high 16 valid data of second pixel and low 16 valid data of the 3rd pixel when using another 32 latch utilizations time-delays; When two 24 latches third and fourth pixel number according to after, 4 sub-frequency clock signals of 3.5 pixel period latch the most-significant byte valid data of the 3rd pixel and 24 valid data of the 4th pixel when using another 32 latch utilizations time-delays.
9. method according to claim 8, it is characterized in that: embedded controller reading of data from 32 dual-port SRAM specifically is meant in the described step (8), 32 dual-port SRAM addressing ranges are 2k, and bottom half on the five equilibrium makes bottom half all can hold delegation's view data; 1 digit counter be input as capable useful signal, output writes upper half or bottom half as the 10th bit address of 32 dual-port SRAM with determination data; Embedded controller still is bottom half peek with decision from upper half by the rising edge of row useful signal is counted; In case upper half or bottom half write data line, then 32 embedded controllers can take out data from the right output port of 32 dual-port SRAM, are temporarily stored among the SDRAM.
10. method according to claim 9 is characterized in that: when embedded controller was peeked from upper half, system write the next line data from trend SRAM bottom half; When embedded controller was peeked from bottom half, system write the next line data from trend SRAM upper half; Finish in case embedded controller detects the frame useful signal, immediately this frame is carried out data processing and Network Transmission.
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