CN109933560A - A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory - Google Patents
A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory Download PDFInfo
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Abstract
The intermodule flow control communication means that the invention discloses a kind of based on FIFO in conjunction with random access memory, belong to electronic technology field, the input module of FIFO is established in FPGA, the output module of computing module and FIFO, the input module of FIFO and the output module of FIFO include data fifo buffer, the depth of data fifo buffer is set as FIFO_Size, width is FIFO_Width, data fifo buffer is divided into N number of piece, the size of the disposable read-write data of data fifo buffer is the data of a block size, solves the technical issues of carrying out data read-write operation in blocks, data are cached, solve the difference of intermodular data processing speed；It is suitble to the application scenarios operated in blocks, FIFO supports to carry out random read-write by address, meets a variety of read-write demands.
Description
Technical field
The invention belongs to electronic technology field, in particular to a kind of intermodule stream based on FIFO in conjunction with random access memory
Control communication means.
Background technique
In a communications system, it needs to transmit data between usual two modules, if the data processing speed of intermodule is identical,
Then can direct two intermodule carry out data transmission, but in the design of FPGA, the execution rate of two intermodules is usually inconsistent,
It needs to cache data, in traditional communication system, data buffer storage is carried out using RAM, but RAM can only step-by-step progress
Read-write, when needing to carry out block read-write, RAM is then showed inflexible.
Summary of the invention
The intermodule flow control communication means that the object of the present invention is to provide a kind of based on FIFO in conjunction with random access memory,
Solves the technical issues of carrying out data read-write operation in blocks.
To achieve the above object, the invention adopts the following technical scheme:
A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory, comprising the following steps:
Step 1: the input module of FIFO, the output module of computing module and FIFO, the input of FIFO are established in FPGA
Module is used to read the input data of the input module storage of FIFO, goes forward side by side for reading and storing input data, computing module
It is output to the output module of FIFO after row processing, the output module of FIFO treated for storing and export computing module number
According to；
The input module of step 2:FIFO and the output module of FIFO include data fifo buffer, set data fifo
The depth of buffer is FIFO_Size, width FIFO_Width, and data fifo buffer is divided into N number of piece, and N is positive integer,
The storage size of each block is all the same, sets the depth of each block as BSize, width BWidth, N=FIFO_Size
÷BSize；
The size of the disposable read-write data of data fifo buffer is the data of BSize size；
The sequence of addresses number of each block is 0,1,2...N-1 in the data fifo buffer；
Step 3: the write enable signal of data fifo buffer is detected in FPGA: when write enable signal is 1, expression can
Data are written into data fifo buffer；
It sets FIFOBwInc and writes full flag bit as block, when a block in data fifo buffer is fully written,
FIFOBwInc set is 1, and data fifo buffer continues to write data into next piece at this time；
It sets FIFO_Full and writes full flag bit as buffer, when entire data fifo buffer is fully written, FIFO_
Full set is 1, cannot carry out write operation to data fifo buffer at this time；
Step 4: the reading enable signal of data fifo buffer is detected in FPGA: when reading enable signal is 1, expression can
To read data from data fifo buffer；
It sets FIFOBrInc and runs through flag bit as block, when a block in data fifo buffer is run through,
FIFOBrInc set is 1, and data fifo buffer continues to read next piece of data at this time；
It sets FIFO_Empty and runs through flag bit as buffer, when entire data fifo buffer is run through, FIFO_
Empty set is 1, cannot carry out read operation to data fifo buffer at this time.
Preferably, data can only be written according to the sequence of addresses of each block in the write operation of the data fifo buffer,
When writing full in order for all pieces, if FIFO_Full signal is not 1 at this time, again according to 0,1,2...N-1 sequence to institute
The middle recurrent wrIting data of data fifo buffer are stated, setting WrPtr flag bit is directed toward presently written piece of first address；
The read operation of the data fifo buffer can only read data according to the sequence of addresses of each block, when all pieces
When running through in order, if FIFO_Empty signal is not 1 at this time, again according to 0,1,2...N-1 sequence to the FIFO
The middle circulation of data buffer reads data, and setting Rd_Ptr flag bit is directed toward the current first address for reading block.
Preferably, the row address of read operation is set as RdAddr, reads the number of a block in the data fifo buffer
According to when, be read out according to RdAddr, when a line address is run through, the data of next row address read, until the number of a block
According to running through completely；
The row address of write operation is set as WrAddr, when data are written in a block of Xiang Suoshu data fifo buffer, is pressed
It is written according to WrAddr, when a line address is fully written, continues downward a line address write-in data, until a block is write completely
It is full.
Preferably, when reading or writing simultaneously to the data fifo buffer, flag bit FIFO_Level table is set
Show that also remaining how many pieces does not read, when the data fifo buffer is empty, without read operation, the data fifo buffer is full
When without write operation, the value of FIFO_Level is described as follows: only writing block number according to without read operation, and FIFO_Level
When < N, FIFO_Level adds 1；Block number is only read according to without write operation, and FIFO_Level > 0, then FIFO_Level subtracts
1；The data fifo buffer is written and read simultaneously, and the data fifo buffer is sky, then FIFO_Level value adds
1；Simultaneously the data fifo buffer is written and read, and the data fifo buffer be it is full, then FIFO_Level value subtracts
1；The data fifo buffer is written and read simultaneously, and the data fifo buffer neither sky is also discontented with, then FIFO_
Level value is constant；When FIFO_Level value is equal to N, then FIFO_Full sets 1, indicates that presently described data fifo buffer is full
State；When FIFO_Level value is equal to 0, then FIFO_Empty sets 1, indicates presently described data fifo buffer for sky.
Preferably, the computing module is read the data of the FIFO input module, computing module by absolute address at random
Data are written to the output module of the FIFO at random by absolute address；The FPGA is by absolute address at random to the input of FIFO
Data are written in module, and the same FPGA is read the FIFO output module data by absolute address at random.
A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory of the present invention, solves
The technical issues of carrying out data read-write operation in blocks, the present invention caches data, solves intermodular data processing
The difference of speed；The present invention carries out piecemeal read-write to data fifo buffer, and be particularly suitable for being operated in blocks answers
With scene, random read-write can be carried out to data fifo buffer, flexibility is higher, meets a variety of data fifo buffer read-writes
Demand；The present invention recycles data fifo buffer, saves system storage overhead, synchronizes reading to data fifo buffer
Control is write, supports synchronous read-write.
Detailed description of the invention
Fig. 1 is FIFO communications framework figure of the invention；
Fig. 2 is FIFO piecemeal schematic diagram of the invention；
Fig. 3 is fifo structure figure of the invention；
Fig. 4 is write operation flow chart of the invention；
Fig. 5 is read operation flow chart of the invention.
Specific embodiment
A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory as Figure 1-Figure 5, packet
Include following steps:
Step 1: the input module of FIFO, the output module of computing module and FIFO, the input of FIFO are established in FPGA
Module is used to read the input data of the input module storage of FIFO, goes forward side by side for reading and storing input data, computing module
It is output to the output module of FIFO after row processing, the output module of FIFO treated for storing and export computing module number
According to；
The input module of step 2:FIFO and the output module of FIFO include data fifo buffer, set data fifo
The depth of buffer is FIFO_Size, width FIFO_Width, and data fifo buffer is divided into N number of piece, and N is positive integer,
The storage size of each block is all the same, sets the depth of each block as BSize, width BWidth, N=FIFO_Size
÷BSize；
The size of the disposable read-write data of data fifo buffer is the data of BSize size；
The sequence of addresses number of each block is 0,1,2...N-1 in the data fifo buffer；
Step 3: the write enable signal of data fifo buffer is detected in FPGA: when write enable signal is 1, expression can
Data are written into data fifo buffer；
It sets FIFOBwInc and writes full flag bit as block, when a block in data fifo buffer is fully written,
FIFOBwInc set is 1, and data fifo buffer continues to write data into next piece at this time；
It sets FIFO_Full and writes full flag bit as buffer, when entire data fifo buffer is fully written, FIFO_
Full set is 1, cannot carry out write operation to data fifo buffer at this time；
Step 4: the reading enable signal of data fifo buffer is detected in FPGA: when reading enable signal is 1, expression can
To read data from data fifo buffer；
It sets FIFOBrInc and runs through flag bit as block, when a block in data fifo buffer is run through,
FIFOBrInc set is 1, and data fifo buffer continues to read next piece of data at this time；
It sets FIFO_Empty and runs through flag bit as buffer, when entire data fifo buffer is run through, FIFO_
Empty set is 1, cannot carry out read operation to data fifo buffer at this time.
Preferably, data can only be written according to the sequence of addresses of each block in the write operation of the data fifo buffer,
When writing full in order for all pieces, if FIFO_Full signal is not 1 at this time, again according to 0,1,2...N-1 sequence to institute
The middle recurrent wrIting data of data fifo buffer are stated, setting WrPtr flag bit is directed toward presently written piece of first address；
The read operation of the data fifo buffer can only read data according to the sequence of addresses of each block, when all pieces
When running through in order, if FIFO_Empty signal is not 1 at this time, again according to 0,1,2...N-1 sequence to the FIFO
The middle circulation of data buffer reads data, and setting Rd_Ptr flag bit is directed toward the current first address for reading block.
Preferably, the row address of read operation is set as RdAddr, reads the number of a block in the data fifo buffer
According to when, be read out according to RdAddr, when a line address is run through, the data of next row address read, until the number of a block
According to running through completely；
The row address of write operation is set as WrAddr, when data are written in a block of Xiang Suoshu data fifo buffer, is pressed
It is written according to WrAddr, when a line address is fully written, continues downward a line address write-in data, until a block is write completely
It is full.
Preferably, when reading or writing simultaneously to the data fifo buffer, flag bit FIFO_Level table is set
Show that also remaining how many pieces does not read, when the data fifo buffer is empty, without read operation, the data fifo buffer is full
When without write operation, the value of FIFO_Level is described as follows: only writing block number according to without read operation, and FIFO_Level
When < N, FIFO_Level adds 1；Block number is only read according to without write operation, and FIFO_Level > 0, then FIFO_Level subtracts
1；The data fifo buffer is written and read simultaneously, and the data fifo buffer is sky, then FIFO_Level value adds
1；Simultaneously the data fifo buffer is written and read, and the data fifo buffer be it is full, then FIFO_Level value subtracts
1；The data fifo buffer is written and read simultaneously, and the data fifo buffer neither sky is also discontented with, then FIFO_
Level value is constant；When FIFO_Level value is equal to N, then FIFO_Full sets 1, indicates that presently described data fifo buffer is full
State；When FIFO_Level value is equal to 0, then FIFO_Empty sets 1, indicates presently described data fifo buffer for sky.
Preferably, the computing module is read the data of the FIFO input module, computing module by absolute address at random
Data are written to the output module of the FIFO at random by absolute address；The FPGA is by absolute address at random to the input of FIFO
Data are written in module, and the same FPGA is read the FIFO output module data by absolute address at random.
When the enabled RdEnAbs signal of absolute reading is high level, data are read from absolute address RdAddrAbs；When absolute
Write enabled WrEnAbs signal be high level when, to absolute address WrAddrAbs be written data.
RdAddrAbs is the current first address for reading block, and WrAddrAbs is the first address for currently writing block.
The present embodiment is by taking a frame image as an example: in video coding and decoding system, it usually needs reads image and carries out compression volume
Code, image need to be operated by block, and by the input module of one piece of image data write-in FIFO, computing module reads FIFO and inputs mould
The data of block are calculated, such as compressed encoding, finally export the output module that coding result is written to FIFO.
One frame image is operated according to the form of data flow, and a frame image carries out piecemeal, set one piece of size as n ×
Image block is sequentially sequentially written in the input module of FIFO by n, and computing module successively takes figure according to the sequence of FIFO first in first out
As the data of block are handled, the result for handling completion is written in the output module of FIFO, and its step are as follows:
Step S1: image compression encoding is usually handled with the block of a 16x16 size, it is assumed that data fifo buffer
Depth FIFO_Size is 256, and width FIFO_Width is 16, therefore data fifo buffer can be divided into 256/16=16
A block, each block size are 16x16, can store the data of an image block just.
Step S2: setting WrEn to write enabler flags position, when data fifo buffer is when to write enabled WrEn be high level,
It indicates that image data is written into data fifo buffer, indicates that a block number evidence writes when FIFOBwInc is high level, after
Next piece is continued, when entire data fifo buffer writes full, full signal FIFO_Full is set 1, expression cannot be to FIFO number
According to writing data in buffer.
Set RdEn as read enabler flags position, when the reading of data fifo buffer enable RdEn be high level when, indicate from
Reading image data in data fifo buffer indicate to have read an image block data, Rd_ when FIFOBrInc is high level
Ptr is directed toward the current first address for reading block, will be empty when data fifo buffer is run through after next image block data of resuming studies
Signal FIFO_Empty sets 1, and expression cannot read data from data fifo buffer, and read-write process is as shown in Figure 4 and Figure 5.
Step S3: image data can only be written to data fifo buffer according to 0,1,2 ..., 15 sequence, when the 0th piece
Can be write by writing Man Shicai by the 1st piece, and WrPtr is directed toward presently written piece of first address, when writing full in order for all pieces, if at this time
FIFO_Full signal is not 1, then again according to 0,1,2 ..., 15 sequence into FIFO recurrent wrIting image data, with this
Analogize, until the 15th fritter data fifo buffer writes.
Computing module can only read the content of data fifo buffer according to 0,1,2 ..., 15 sequence, and Rd_Ptr is directed toward
The current first address for reading block, when entire data fifo buffer is run through, if FIFO_Empty is not 1 at this time, again according to
0,1,2 ..., 15 sequence reads image data.
Step S4: when image data is written to a block of data fifo buffer, writing data by row address WrAddr, when
When a line writes, continue to write a line, until block is write completely；Computing module is from reading image data carry out in data fifo buffer
When reason, data are read by row address RdAddr, when a line is run through, after next line of resuming studies, until a block is run through.
Step S5: when reading while write FIFO image data, how many pieces of image datas are also remained using FIFO_Level expression
It does not read, it is ensured that when FIFO is empty, without read operation, without write operation when FIFO is full, the value of FIFO_Level is said
It is bright as follows: only to write an image block data and do not read FIFO, and FIFO_Level < N, then FIFO_Level adds 1；Only read one
Image block data is without write operation, and FIFO_Level > 0, then FIFO_Level subtracts 1；FIFO image data is carried out simultaneously
Read-write, and FIFO is sky, FIFO_Level value adds 1；FIFO image data is written and read simultaneously, and FIFO is full, FIFO_
Level value subtracts 1；FIFO image data is written and read simultaneously, and FIFO neither sky is also discontented with, then FIFO_Level value is constant；
When FIFO_Level value is equal to N, then FIFO_Full sets 1, indicates that current FIFO is full state；When FIFO_Level value be equal to 0,
Then FIFO_Empty sets 1, indicates current FIFO for sky.
Computing module can be read the image data of FIFO input module at random by absolute address, and computing module can be by exhausted
Image data is written to FIFO output module at random to address.System can be written to FIFO input module at random by absolute address
Image data, same system can be read FIFO output module image data at random by absolute address.FIFO proposed by the present invention
It can not only be read and write with piecemeal, also support to press absolute address random read-write function, when the enabled RdEnAbs signal of absolute reading is
When high level, image data is read from absolute address RdAddrAbs；When absolutely writing enabled WrEnAbs signal is high level, to
Data are written in absolute address WrAddrAbs.RdAddrAbs is the current first address for reading block, and WrAddrAbs is the head for currently writing block
Address.
A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory of the present invention, solves
The technical issues of carrying out data read-write operation in blocks, the present invention caches data, solves intermodular data processing
The difference of speed；The present invention carries out piecemeal read-write to data fifo buffer, and be particularly suitable for being operated in blocks answers
With scene, random read-write can be carried out to data fifo buffer, flexibility is higher, meets a variety of data fifo buffer read-writes
Demand；The present invention recycles data fifo buffer, saves system storage overhead, synchronizes reading to data fifo buffer
Control is write, supports synchronous read-write.
Claims (5)
1. a kind of intermodule flow control communication means based on FIFO in conjunction with random access memory, it is characterised in that: including following
Step:
Step 1: the input module of FIFO, the output module of computing module and FIFO, the input module of FIFO are established in FPGA
For reading and storing input data, computing module is used to read the input data of the input module storage of FIFO, and is located
It is output to the output module of FIFO after reason, the output module of FIFO treated for storing and export computing module data；
The input module of step 2:FIFO and the output module of FIFO include data fifo buffer, setting data fifo caching
The depth of device is FIFO_Size, width FIFO_Width, data fifo buffer is divided into N number of piece, N is positive integer, each
The storage size of a block is all the same, sets the depth of each block as BSize, width BWidth, N=FIFO_Size ÷
BSize；
The size of the disposable read-write data of data fifo buffer is the data of BSize size；
The sequence of addresses number of each block is 0,1,2...N-1 in the data fifo buffer；
Step 3: the write enable signal of data fifo buffer is detected in FPGA: when write enable signal is 1, expression can be to
Data are written in data fifo buffer；
It sets FIFOBwInc and writes full flag bit as block, when a block in data fifo buffer is fully written, FIFOBwInc
Set is 1, and data fifo buffer continues to write data into next piece at this time；
It sets FIFO_Full and writes full flag bit as buffer, when entire data fifo buffer is fully written, FIFO_Full
Set is 1, cannot carry out write operation to data fifo buffer at this time；
Step 4: the reading enable signal of data fifo buffer is detected in FPGA: when reading enable signal is 1, expression can be from
Data are read in data fifo buffer；
It sets FIFOBrInc and runs through flag bit as block, when a block in data fifo buffer is run through, FIFOBrInc
Set is 1, and data fifo buffer continues to read next piece of data at this time；
It sets FIFO_Empty and runs through flag bit as buffer, when entire data fifo buffer is run through, FIFO_
Empty set is 1, cannot carry out read operation to data fifo buffer at this time.
2. a kind of intermodule flow control communication means based on FIFO in conjunction with random access memory as described in claim 1,
Be characterized in that: data can only be written according to the sequence of addresses of each block in the write operation of the data fifo buffer, when all
When block writes full in order, if FIFO_Full signal is not 1 at this time, again according to 0,1,2...N-1 sequence to the FIFO
The middle recurrent wrIting data of data buffer, setting WrPtr flag bit are directed toward presently written piece of first address；
The read operation of the data fifo buffer can only read data according to the sequence of addresses of each block, when all pieces by suitable
When sequence is run through, if FIFO_Empty signal is not 1 at this time, again according to 0,1,2...N-1 sequence to the data fifo
The middle circulation of buffer reads data, and setting Rd_Ptr flag bit is directed toward the current first address for reading block.
3. a kind of intermodule flow control communication means based on FIFO in conjunction with random access memory as claimed in claim 2,
It is characterized in that: setting the row address of read operation as RdAddr, when reading the data of a block in the data fifo buffer, press
It is read out according to RdAddr, when a line address is run through, reads the data of next row address, until the data of a block are read completely
It is complete；
The row address of write operation is set as WrAddr, when data are written in a block of Xiang Suoshu data fifo buffer, according to
WrAddr is written, and when a line address is fully written, continues downward a line address write-in data, until a block is write completely completely.
4. a kind of intermodule flow control communication means based on FIFO in conjunction with random access memory as claimed in claim 2,
It is characterized in that: when to the data fifo buffer while when reading or writing, setting flag bit FIFO_Level indicates also surplus
How many pieces are not read, and when the data fifo buffer is empty, without read operation, the data fifo buffer is full Shi Bujin
Row write operation, the value of FIFO_Level are described as follows: a block number evidence is only write without read operation, and when FIFO_Level < N,
FIFO_Level adds 1；Block number is only read according to without write operation, and FIFO_Level > 0, then FIFO_Level subtracts 1；Together
When the data fifo buffer is written and read, and the data fifo buffer be sky, then FIFO_Level value adds 1；Together
When the data fifo buffer is written and read, and the data fifo buffer be it is full, then FIFO_Level value subtracts 1；Together
When the data fifo buffer is written and read, and the data fifo buffer is neither empty is also discontented with, then FIFO_Level
It is worth constant；When FIFO_Level value is equal to N, then FIFO_Full sets 1, indicates that presently described data fifo buffer is full state；
When FIFO_Level value is equal to 0, then FIFO_Empty sets 1, indicates presently described data fifo buffer for sky.
5. a kind of intermodule flow control communication means based on FIFO in conjunction with random access memory as claimed in claim 2,
Be characterized in that: the computing module is read the data of the FIFO input module by absolute address at random, and computing module is by absolute
Data are written to the output module of the FIFO at random in address；The FPGA is write to the input module of FIFO at random by absolute address
Enter data, the same FPGA is read the FIFO output module data by absolute address at random.
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