CN101882302A - Motion blur image restoration system based on multi-core - Google Patents
Motion blur image restoration system based on multi-core Download PDFInfo
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Abstract
The invention discloses a motion blur image restoration system based on multi-core. In the system, a preprocessing and logic transfer module preprocesses video frames collected by a video collecting and decoding module and temporarily stores the preprocessed video frames in a high-speed data buffer module, the core calculation of a preprocessing module is finished by adopting an FPGA (Field Programmable Gate Array), and the high-speed data buffer module is based on DDR SDRAM (Digital Data Receiver Synchronous Dynamic Random Access Memory). A double-core processing module reads the video frames in a high-speed data cache through the preprocessing and logic transfer module and carries out image compensation. The double-core processing module is established by adopting two DSPs (Digital Signal Processor), and video subject to parallel processing is played back in a playback module. In the system, the processing work of video is distributed to two parts, and by adopting the preprocessing of the FPGA and the high-speed reading and writing based on the DDR SDRAM data cache, the high-efficiency performance of double DSP core parallel calculation can effectively finish the tasks of image compensation and restoration.
Description
Technical field
The present invention relates to the motion blur image restoration technical field, particularly a kind of motion blur image restoration system based on multinuclear is finished the motion blur image compensation, is applicable to high-speed motion blurred picture recovering research.
Background technology
High precision real-time optical remote sensing campaign imaging requirements platform ideal movements, but platform is environment and the following imperfect motion that can form complicated multimode of internal disturbance influence externally, cause that remote optical sensing moves into that picture blurs, defocuses, distortion, pixel aliasing, and cause seriously degrading.It is many that remote sensing moves into the picture quantity of information, resolution height, and the general more complicated of Image Restoration Algorithm, and calculated amount is very big.Therefore the research and the development of high speed image recovery system seem particularly important, have very high scientific value and huge social economic benefit.
The hardware cell of Flame Image Process generally uses Digital Image Processor DSP (Digital SignalProcessor) to realize.DSP is not only programmable, and travelling speed can reach the per second number with ten million bar complicated order program in fact the time, and its powerful data-handling capacity and high travelling speed are considerably beyond general purpose microprocessor; FPGA (Field-Programmable Gate Array), it is field programmable gate array, it occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again; DDR SDRAM (Double Data Rate SDRAM) is the Double Data Rate synchronous DRAM, than single data rate (SDR, Single Data Rate) only in the rising edge transmission primaries data of a clock period, it can transmit two secondary data at rising edge in the clock period and negative edge to SDRAM.The DDR internal memory can be issued to higher data transmission rate at the bus frequency identical with SDRAM.Adopt the framework of FPGA pre-service, DDR SDRAM high-speed cache and the parallel computation of two DSP core to help making up flow chart of data processing efficiently and make things convenient for the distribution of Processing tasks, improve the degree of concurrence and the resource utilization of system.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of motion blur image plerosis original system based on multinuclear is provided, can improve the efficient that image restoration is handled.
Technical solution of the present invention is:
A kind of motion blur image restoration system based on multinuclear, comprise: video acquisition and decoder module, pre-service and logic transit module, the double-core processing module of forming by n digital signal processor DSP in parallel, the data cache module of forming by n double data rate synchronous dynamic random access memory DDR SDRAM, and video coding and playback module, n corresponding n digital signal processor DSP of DDR SDRAM; N is the integer more than or equal to 2;
The annexation of above-mentioned each module is: video acquisition is connected described pre-service and logic transit module with decoder module; Described pre-service and logic transit module adopt field programmable gate array FPGA to realize, connect external memory interface EMIF and the DDR SDRAM of DSP; Described double-core processing module connects described pre-service and logic transit module, and n DSP in this double-core processing module adopts the parallel processing mode, and n DSP shaking hands each other realized by interruption, the general purpose I/O pin of linking each DSP on the FPGA; N DDR SDRAM in the described data cache module connects described pre-service and logic transit module; Described video coding is connected described pre-service and logic transit module with playback module;
The workflow of above-mentioned each module is:
1. every frame image data that described video acquisition and decoder module will be gathered and decode sends to pre-service and logic transit module;
2. pre-service and logic transit module carry out pre-service to every frame image data of video acquisition and decoder module output, pretreated view data is divided into the n part, and the DDR controller of realizing by FPGA is stored in respectively among n the DDR SDRAM with the view data of burst mode with the n part; Wherein, the DDR controller is in the rising edge and the negative edge transmission data of clock;
3. each DSP is by described pre-service and logic transit module view data from the DDRSDRAM of self correspondence obtains, and carries out image restoration, and the image after restoring is sent to pre-service and logic transit module;
4. pre-service and logic transit module are merged into the image of each DSP recovery a complete two field picture and export to video coding and playback module;
5. the complete image that video coding and playback module are encoded and playback pre-service and logic transit module are merged into.
Preferably, this system further comprises a control module;
This control module links to each other with one of them DSP by host interface HPI bus based on the ARM controller that embeds WinCE, behind user's selection algorithm, and the give instructions in reply data of former algorithm types of change HPI shared memory middle finger;
The DSP that links to each other with control module, further detecting described HPI shared memory middle finger gives instructions in reply after the data of former algorithm types change, change the recovery algorithm types of other DSP by described pre-service and logic transit module, each DSP begins to carry out image restoration with the recovery algorithm after changing then.
Preferably, this system further comprises n the two-way pushup storage fifo controller that is connected between DDR SDRAM and pre-service and the logic transit module, and two-way fifo controller and DDRSDRAM are man-to-man relation.
Preferably, described pre-service and logic transit module comprise pretreatment unit, data allocations unit, the DDR controller of realizing with FPGA;
Pretreatment unit carries out pre-service to the every frame image data from video acquisition and decoder module, and pretreated data wait the data allocations resume module;
The data allocations module is divided into the n part with pretreated view data;
Under the read-write sequence control of DDR controller, store into respectively among n the DDR SDRAM with the n parts of images data of burst mode with the data allocations Module Division; Wherein, the DDR controller is in the rising edge and the negative edge transmission data of clock;
Under the read-write sequence control of DDR controller, the view data among the DDR SDRAM constantly is delivered to corresponding DSP;
At last, the data allocations module is obtained the image of recovery from each DSP, and exports to video coding and playback module after being merged into a complete two field picture.
By the above as can be seen, the present invention will distribute to two parts to the work of treatment of video, carry out pre-service by the pre-service of FPGA, carry out image compensation by parallel DSP, thereby improve the efficient of image compensation and recovery.And, the present invention adopts the buffer area of DDR SDRAM as view data, can satisfy the demand of mass data buffer memory, and DDR SDRAM can be in the rising edge and the negative edge transmission data of clock, this can only compare in the negative edge transmission data of clock period with SDR SDRAM, can improve message transmission rate greatly.
As seen, adopt the framework of FPGA pre-service, DDR SDRAM high-speed cache and the parallel computation of two DSP core to help making up flow chart of data processing efficiently and make things convenient for the distribution of Processing tasks, improve the degree of concurrence and the resource utilization of system.
Secondly, the present invention adopts control module to select to restore algorithm, has increased the dirigibility of native system greatly.
In addition, the present invention also adds two-way fifo controller between FPGA and DDR SDRAM, and this makes and can write in order and read writing data and reading of data in DDR SDRAM when.
Description of drawings
Fig. 1 is the motion blur image restoration system structural representation based on multinuclear of the present invention;
Fig. 2 is a composition structured flowchart of the present invention;
Fig. 3 is the functional block diagram of pre-service of the present invention and logic transit module;
Fig. 4 is the loose coupling structural drawing of double-core processing module.
Embodiment
The invention provides a kind of motion blur image restoration system based on multinuclear, as depicted in figs. 1 and 2, image restoration system of the present invention comprises video acquisition and decoder module 1, pre-service and logic transit module 2, the double-core processing module 3 is made up of n DSP in parallel, data cache module 4 and the video be made up of n DDR SDRAM encode and playback module 6.Wherein, n corresponding n DSP of DDRSDRAM; N is the integer more than or equal to 2.The embodiment of the invention and n=2 are example.
Video acquisition and decoder module 1 link to each other with logic transit module 2 with pre-service, will gather with decoded video and be sent to pre-service and logic transit module 2.
Pre-service and logic transit module 2, adopt FPGA to realize, every frame image data that this module is at first being born video acquisition and decoder module 1 output carries out pretreated task, as necessary image processing algorithm before the core calculations such as video image binaryzation, filtering; Secondly, the DDR controller logic that FPGA realizes plays a bridge between double-core processing module 3 and data cache module 4, promptly the DDRSDRAM of the external memory interface of DSP (EMIF) and data cache module 4 is coupled together.Under this connection situation, the view data after FPGA will handle is divided into the n=2 part, this two-part view data is stored in respectively among 2 DDR SDRAM with burst mode by the DDR controller; Read the view data of DSP request from DDR SDRAM, the image that each DSP is restored is merged into a complete two field picture and sends to video coding and playback module 6.
N in the double-core processing module 3 DSP adopts the parallel processing mode; Each DSP is by pre-service and logic transit module 2 view data from the DDR SDRAM of self correspondence obtains, and carries out image restoration; Two DSP shaking hands each other realized by interruption, the general purpose I/O pin of linking each DSP on the FPGA.
Two DDR SDRAM in the data cache module 4, caching image data when being used for DSP each block image is restored.
Video coding and playback module are used to encode and complete image that playback pre-service and logic transit module are merged into.
The workflow of above-mentioned each module is:
1. video acquisition and the decoder module every frame image data that will gather and decode sends to pre-service and logic transit module.
2. pre-service and logic transit module carry out pre-service to every frame image data of video acquisition and decoder module output, pretreated view data is divided into two parts, and the DDR controller of realizing by FPGA is stored in two-part view data respectively among two DDR SDRAM with burst mode; Wherein, the DDR controller is in the rising edge and the negative edge transmission data of clock.
3. each DSP is by described pre-service and logic transit module view data from the DDRSDRAM of self correspondence obtains, and carries out image restoration, and the image after restoring is sent to pre-service and logic transit module;
4. pre-service and logic transit module are merged into the image of each DSP recovery a complete two field picture and export to video coding and playback module;
5. the complete image that video coding and playback module are encoded and playback pre-service and logic transit module are merged into.
By image restoration system of the present invention as can be seen, the present invention adopts the framework of FPGA pre-service, DDRSDRAM high-speed cache and the parallel computation of two DSP core to help making up flow chart of data processing efficiently and makes things convenient for the distribution of Processing tasks, improves the degree of concurrence and the resource utilization of system.
Function to each important module is described in detail below.
Pre-service and logic transit module 2, be responsible for all logic controls and image preprocessing tasks except that Image Restoration Algorithm, as shown in Figure 3, this mainly comprises: the input and output of video, frame of video essential image Preprocessing Algorithm, data cache module 4 core devices DDRSDRAM and the sequential control of double-core processing module 3 memory interfaces and data allocations before the image Parallel Processing etc. before restoring.The introducing of DDR SDRAM has improved the efficient of 3 processing of double-core processing module and memory image greatly.
Specifically, as shown in Figure 3, pre-service and logic transit module comprise pretreatment unit, data allocations unit and the DDR controller of realizing with FPGA;
Pretreatment unit carries out pre-service to the every frame image data from video acquisition and decoder module, and pretreated data wait the data allocations resume module.
The data allocations module is divided into the n part with pretreated view data.
The DDR controller is used to control the sequential of DDR SDRAM reading and writing data.Under the read-write sequence control of DDR controller, store into respectively among 2 DDRSDRAM with the view data of burst mode with the n=2 part.Wherein, the DDR controller is in the rising edge and the negative edge transmission data of clock.
When DSP when DDR SDRAM obtains data, under the control of DDR controller read-write sequence, the view data among the DDR SDRAM constantly is delivered to corresponding DSP.
The final data distribution module is obtained the image of recovery from each DSP, and exports to video coding and playback module after being merged into a complete two field picture.
Double-core processing module 3 is restored algorithm by the collaborative blurred picture of finishing of the DSP core of two parallel connections.As shown in Figure 2, two DSP are called DSP-A and DSP-B, and two DSP shaking hands each other realized by interruption, the general purpose I/O pin of linking each DSP on the FPGA.Two cores in the double-core processing module 3 are based on MIMD (multiple-instruction-stream multiple-data stream) system, and this system is generally described by tightly coupled system and two kinds of structures of loosely coupled system.Tightly coupled system is realized communication between the processor by the storer of sharing, and the contact between the processor is tightr.Each processor node has storer in the loosely coupled system, and the mode by the message transmission between the processor intercoms mutually.The present invention adopts the structure based on loose coupling, its architecture as shown in Figure 4, each DSP connects external bus by buffer memory, this external bus inserts pre-service and logic transit module 2.Each DSP has storer, and this storer is the DDR SDRAM among Fig. 2, DSP not with DDR SDRAM direct communication, but intercom mutually with logic transit module 2 with pre-service by external bus.
As seen, the present invention adopts two DSP parallel processing system (PPS)s, many DSP communication mode is not subjected to not have coupling and support burst type, mass data high-speed communication between the restriction, each DSP of DSP Communications Control Interface, and the occasion big at data throughout, that digital operation is complicated is widely used.
The present invention adopts the buffer area of DDR SDRAM as view data.Because under high speed data fields such as Flame Image Process are closed, need the high-speed cache lot of data, traditional SDRAM can not satisfy the demand of this mass data buffer memory, and DDR SDRAM (Double Data Rage, double data rate) because fast, the capacious characteristics of its speed is well positioned to meet this demand, therefore, as shown in Figure 2, data cache module 4 of the present invention has been used the buffer area of two DDR SDRAM as view data.With SDR SDRAM can only be different in the negative edge of clock period transmission data, this DDRSDRAM can both transmit data at the rising edge and the negative edge of clock.Therefore the transfer rate of DDR SDRAM is the twice of SDR SDRAM transfer rate.But the interface of the dsp processor that adopts among the present invention can not directly link to each other with the DDR memory interface, and therefore exchanges data between the two need be finished by the DDR controller that pre-service and logic transit module 2 are realized.
The core of control module 5 is based on the ARM controller that embeds WinCE, and control module 5 comprises a touch-screen, and the user can select different Image Restoration Algorithm by touch-screen, and the video after energy current collection video of live preview and the algorithm process.
For the ease of the demonstration and the quality of more various Image Restoration Algorithm, image restoration system of the present invention comprises that further control module 5 finishes the selection of algorithm.Control module 5 is finished based on the ARM controller that embeds WinCE, it by host interface (HPI, Host Port Interface) bus and one of them DSP for example DSP-A link to each other, to finish communication between the two.When the user selectes certain algorithm, control module 5 changes the give instructions in reply data of former algorithm types of HPI shared memory middle fingers, when DSP-A detects that these data change in the HPI shared memory, by the recovery algorithm types of FPGA change DSP-B, so latter two DSP begins to carry out image restoration with the recovery algorithm after changing.
Preferably, control module 5 contains a resistive touch screen, opens that the user can select different Image Restoration Algorithm by touch-screen easily behind the algorithm setting program.Video after control module 5 all right further current collection videos of live preview and the algorithm process, in this case, the data before and after pre-service and logic transit module 2 restore send to control module 5 by some DSP.
In practice, in order to guarantee the order of view data, it is necessary respectively adding a two-way FIFO between FPGA and two DDR SDRAM, and this makes and can write in order and read writing data and reading of data in DDR SDRAM when.This FIFO is not shown in Figure 4, increases if desired, then increases FIFO between storer and the external bus in Fig. 4.
The course of work of image restoration system of the present invention is:
At first deliver to FPGA from every frame image signal of video acquisition and decoder module output and carry out the image pre-service, data after the processing are divided into two parts, and the DDR controller of realizing by FPGA is stored in them among two DDR SDRAM of respectively corresponding two DSP cores with burst mode.Under the dma controller effect of DSP-A and DSP-B, the data of storing among the DDR SDRAM are constantly transferred in the DSP ram in slice by FIFO, and so latter two DSP carries out image restoration to the image that is assigned to separately.Single-frame images is controlled and reconstituted to view data after two-way restores by the logical sequence of FPGA, by pre-service and the 2 control output playback of logic transit module.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. motion blur image restoration system based on multinuclear, it is characterized in that: this system comprises: video acquisition and decoder module, pre-service and logic transit module, the double-core processing module of being made up of n digital signal processor DSP in parallel, the data cache module of being made up of n double data rate synchronous dynamic random access memory DDR SDRAM, and video coding and playback module, n corresponding n digital signal processor DSP of DDR SDRAM; N is the integer more than or equal to 2;
The annexation of above-mentioned each module is: video acquisition is connected described pre-service and logic transit module with decoder module; Described pre-service and logic transit module adopt field programmable gate array FPGA to realize, connect external memory interface EMIF and the DDR SDRAM of DSP; Described double-core processing module connects described pre-service and logic transit module, and n DSP in this double-core processing module adopts the parallel processing mode, and n DSP shaking hands each other realized by interruption, the general purpose I/O pin of linking each DSP on the FPGA; N DDR SDRAM in the described data cache module connects described pre-service and logic transit module; Described video coding is connected described pre-service and logic transit module with playback module;
The workflow of above-mentioned each module is:
1. every frame image data that described video acquisition and decoder module will be gathered and decode sends to pre-service and logic transit module;
2. pre-service and logic transit module carry out pre-service to every frame image data of video acquisition and decoder module output, pretreated view data is divided into the n part, and the DDR controller of realizing by FPGA is stored in respectively among n the DDR SDRAM with the view data of burst mode with the n part; Wherein, the DDR controller is in the rising edge and the negative edge transmission data of clock;
3. each DSP is by described pre-service and logic transit module view data from the DDRSDRAM of self correspondence obtains, and carries out image restoration, and the image after restoring is sent to pre-service and logic transit module;
4. pre-service and logic transit module are merged into the image of each DSP recovery a complete two field picture and export to video coding and playback module;
5. the complete image that video coding and playback module are encoded and playback pre-service and logic transit module are merged into.
2. the motion blur image restoration system based on multinuclear as claimed in claim 1 is characterized in that this system further comprises a control module;
This control module links to each other with one of them DSP by host interface HPI bus based on the ARM controller that embeds WinCE, behind user's selection algorithm, and the give instructions in reply data of former algorithm types of change HPI shared memory middle finger;
The DSP that links to each other with control module, further detecting described HPI shared memory middle finger gives instructions in reply after the data of former algorithm types change, change the recovery algorithm types of other DSP by described pre-service and logic transit module, each DSP begins to carry out image restoration with the recovery algorithm after changing then.
3. the motion blur image restoration system based on multinuclear as claimed in claim 1, it is characterized in that, this system further comprises n the two-way pushup storage fifo controller that is connected between DDR SDRAM and pre-service and the logic transit module, and two-way fifo controller and DDR SDRAM are man-to-man relation.
4. the motion blur image restoration system based on multinuclear as claimed in claim 1 is characterized in that, described pre-service and logic transit module comprise pretreatment unit, data allocations unit, the DDR controller of realizing with FPGA;
Pretreatment unit carries out pre-service to the every frame image data from video acquisition and decoder module, and pretreated data wait the data allocations resume module;
The data allocations module is divided into the n part with pretreated view data;
Under the read-write sequence control of DDR controller, store into respectively among n the DDR SDRAM with the n parts of images data of burst mode with the data allocations Module Division; Wherein, the DDR controller is in the rising edge and the negative edge transmission data of clock;
Under the read-write sequence control of DDR controller, the view data among the DDR SDRAM constantly is delivered to corresponding DSP;
At last, the data allocations module is obtained the image of recovery from each DSP, and exports to video coding and playback module after being merged into a complete two field picture.
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| CN109741234A (en) * | 2018-12-29 | 2019-05-10 | 深圳市太赫兹科技创新研究院 | A kind of OCT image processing unit and system |
| CN109741234B (en) * | 2018-12-29 | 2023-02-17 | 深圳市华讯方舟光电技术有限公司 | OCT image processing device and system |
| CN111191362A (en) * | 2019-12-27 | 2020-05-22 | 苏州浪潮智能科技有限公司 | Graph computation data preprocessing method, device, equipment and medium based on FPGA |
| CN111191362B (en) * | 2019-12-27 | 2022-08-19 | 苏州浪潮智能科技有限公司 | Graph computation data preprocessing method, device, equipment and medium based on FPGA |
| CN112235579A (en) * | 2020-09-28 | 2021-01-15 | 深圳市洲明科技股份有限公司 | Video processing method, computer-readable storage medium and electronic device |
| CN112235579B (en) * | 2020-09-28 | 2022-09-06 | 深圳市洲明科技股份有限公司 | Video processing method, computer-readable storage medium and electronic device |
| CN114095777A (en) * | 2022-01-20 | 2022-02-25 | 广东欧谱曼迪科技有限公司 | Video processing system, method, electronic equipment and storage medium |
| CN114095777B (en) * | 2022-01-20 | 2022-05-17 | 广东欧谱曼迪科技有限公司 | Video processing system, method, electronic equipment and storage medium |
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