CN102081963A - Embedded dynamic random access memory (eDRAM) cell -gain cell eDRAM cell with metal oxide semiconductor (MOS) capacitors and preparation method of gain cell eDRAM cells - Google Patents

Abstract

The invention provides an embedded dynamic random access memory (eDRAM) cell-gain cell eDRAM cell with metal oxide semiconductor (MOS) capacitors and a preparation method of the gain cell eDRAM cells, belonging to the technical field of eDRAMs. The invention has the following beneficial effects: an MOS capacitor is added on the memory node of each gain cell eDRAM cell, thus lengthening the data hold time of the gain cell eDRAM cells, reducing the refresh frequency and reducing the power consumption of the eDRAM formed by the gain cell eDRAM cells; and at the same time, the added MOS capacitors can be compatible with the standard MOS process, so the preparation method has the characteristic of low preparation cost.

Description

Gain cell eDRAM unit, storer and the preparation method of band mos capacitance

Technical field

The invention belongs to dynamic RAM (DRAM) technical field, be specifically related to a kind of embedded DRAM (eDRAM) technology, relate in particular to a kind of with mos capacitance, can with gain cell eDRAM (GainCell eDRAM) unit, storer and the preparation method of the integrated manufacturing of MOS technology.

Background technology

Storer can be divided into chip external memory and in-line memory, in-line memory be a kind of be integrated in the chip with chip system in the element of the common compositing chips of IP module such as each logic, mixed signal.In-line memory comprises embedded static RAM (eSRAM) and embedded DRAM (eDRAM), wherein, eDRAM is because its unit includes only a transistor and an electric capacity, and six transistors of eSRAM unit have the little characteristics of cellar area relatively.

But, the manufacturing that the difficult point of traditional eDRAM is its electric capacity generally not with standard MOS process compatible, thereby DRAM technology and conventional logic process are widely different, the integration of technology is difficulty quite.Therefore industry has proposed to come with the stray capacitance of metal-oxide-semiconductor self thought of electric capacity among the equivalent substitute DRAM.

See also Fig. 1, Figure 1 shows that the gain cell eDRAM cellular construction synoptic diagram of prior art.This eDRAM is proposed in U.S. Pat 7120072 by Intel Company, as shown in Figure 1, this Gain Cell eDRAM 100 comprise write MOS transistor 101, read MOS transistor 102, write word line (Write Word Line, WWL) 105, readout word line (ReadWord Line, RWL) 106, write bit line (Write Bit Line, WBL) 107, sense bit line (Read Bit Line, RBL) 108 and equivalent parasitic capacitances 104.Wherein, the source region of writing MOS transistor 101 is connected in the grid of reading MOS transistor 102, and MN point 103 is a memory node, equivalent parasitic capacitances 104 1 ends are connected with 103, other end ground connection, therefore, conducting and shutoff that MOS transistor 102 is read in the high low energy control of the current potential that MN is ordered; For example, during electric capacity 104 stored charges, representative storage " 1 ", MN point 103 is a noble potential, can control and read MOS transistor 102 shutoffs.Read a termination RBL of MOS transistor 102, another termination RWL; Write a termination WBL of MOS transistor 101, another termination is read the grid of MOS transistor 102.In this embodiment, equivalent parasitic capacitances 104 is for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102, also or both combinations.Specify its operating process below in conjunction with operating list:

(1) write operation (Write): when writing " 0 ", RWL, RBL put 0 current potential, read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 0V, thus equivalent parasitic capacitances 104 discharges, and memory node 103 current potentials are 0.During one writing, RWL, RBL put 0 current potential, read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 1V, thus equivalent parasitic capacitances 104 chargings, and memory node 103 current potentials are noble potential.

(Hold): RWL, RBL put 0 current potential when (2) data kept, and read MOS transistor 102 and did not work, and WWL puts 1V, write MOS transistor 101 and turn-offed, and the current potential of memory node 103 is not subjected to ectocine.

(3) read operation (Read): when reading " 0 ", WWL puts 1V, and WBL puts 0V, writes MOS transistor 101 and turn-offs; The RWL biasing is less than 1V, and RBL puts 0V, and read MOS transistor 102 conductings this moment, and RWL charges to RBL by reading MOS transistor, because sensing circuit has clamping action, the electrical potential energy of RBL reaches 200mV, thereby can sense data " 0 ".When reading " 1 ", WWL puts 1V, and WBL puts 0V, writes MOS transistor 101 and turn-offs; The RWL biasing is read MOS transistor 102 this moment and is turn-offed less than 1V, and RWL can not charge to RBL by reading MOS transistor, and RBL keeps the 0V current potential, thereby can sense data " 1 ".

Gain Cell eDRAM unit shown in Figure 1 does not need to make in addition electric capacity, adopt standard CMOS process, and the relative eSRAM of its structure is simpler, can realize highdensity embedded storage.But, because equivalent parasitic capacitances 104 is for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102 or for to write the active area stray capacitance of MOS transistor 101 and the combination of reading the gate capacitance of MOS transistor 102, the capacitance of equivalent parasitic capacitances 104 is less relatively.The 104 charge stored retention times of equivalent parasitic capacitances have been reflected the data retention characteristics of this gain cell eDRAM unit, and charge retention time is long more, and the required frequency that refreshes is just low more.Generally, the leakage current path of 104 stored charges of equivalent parasitic capacitances of this gain cell eDRAM unit mainly contains three kinds: the firstth, by writing the subthreshold value electric leakage of MOS transistor 101; The secondth, by the PN junction electric leakage at memory node 103 places; The 3rd is the electric leakage by writing MOS transistor 101 and reading the grid oxide layer of MOS transistor 102.

Gain cell eDRAM unit shown in Figure 1 is because equivalent parasitic capacitances is less relatively, under the situation of electric leakage, data hold time is too short, is particularly adopting standard logic process to have only the data hold time of 10us under 65nm, thereby memory refress frequency height, power consumption increase.

Figure 2 shows that the physical arrangement synoptic diagram of gain cell eDRAM shown in Figure 1 unit.In the prior art, gain cell eDRAM unit shown in Figure 1 is by using physical arrangement shown in Figure 2 and finishing manufacturing.Wherein 201 for writing the active area of MOS transistor 101, and 202 for writing the grid of MOS transistor 101, and 205 for reading the active area of MOS transistor 102, and 206 for reading the grid of MOS transistor 102; The active area 201 of writing MOS transistor is connected by metal wire 207 with the grid 206 of reading MOS transistor.Zone in the dotted line block diagram is the memory node 204 of this eDRAM unit.On the metal wire 207 of memory node 204, can reflect the storage current potential of equivalent parasitic capacitances (the active area stray capacitance of the active area 201 of MOS transistor or the gate capacitance or the parallel connection of the two combination of reading MOS transistor).The size of the equivalent parasitic capacitances at memory node 204 places is directly determining the length of the time data memory of this storage unit, thereby has determined the speed of refreshing frequency and the size of power consumption.And such memory capacitance that constitutes with metal-oxide-semiconductor active area electric capacity and gate capacitance is quite little, so its data hold time is shorter, refreshing frequency is had relatively high expectations.

Summary of the invention

It is long to the purpose of this invention is to provide a kind of data hold time, and refreshing frequency is low, the gain cell eDRAM unit that power consumption is economized, storer and preparation method thereof.

Gain cell eDRAM provided by the invention unit, comprise read MOS transistor, write MOS transistor, the equivalent parasitic capacitances at write word line, write bit line, readout word line, sense bit line and memory node place, also comprise the mos capacitance, the manufacturing of described mos capacitance and the standard MOS process compatible that place stored charge described memory node place, that be used to increase the gain cell eDRAM unit.

According to gain cell eDRAM provided by the present invention unit, wherein, the bottom electrode of described mos capacitance is a substrate, the dielectric layer of described mos capacitance with the gate dielectric layer of reading MOS transistor, write the synchronous composition of the gate dielectric layer of MOS transistor and form, the top electrode of described mos capacitance and the gate electrode of reading MOS transistor, the synchronous composition of gate electrode of writing MOS transistor form.

As preferred embodiment, the top electrode of described mos capacitance and the described gate electrode of reading MOS transistor link together.

As another embodiment, the top electrode of described mos capacitance and the described gate electrode of reading MOS transistor are isolated.

According to gain cell eDRAM provided by the present invention unit, wherein, do not increasing under the situation of reading MOS transistor device cell area, increase with the area of reading the active area that the MOS transistor grid is connected, be used for forming described mos capacitance.

Describedly read MOS transistor and write MOS transistor and can be the PMOS transistor; Perhaps describedly read MOS transistor and write MOS transistor and can be nmos pass transistor.

The present invention provides the preparation method of a kind of gain cell eDRAM unit simultaneously, wherein, with the eDRAM unit read MOS transistor or write MOS transistor synchronously, prepare the mos capacitance of the stored charge that is used for increasing the gain cell eDRAM unit with standard MOS technology.

According to the preparation method of gain cell eDRAM provided by the present invention unit, wherein, the step of described preparation mos capacitance comprises:

(1) do not increasing under the situation of writing MOS transistor device cell area, increasing and read the area of writing the MOS transistor active area that the MOS transistor grid is connected, forming the bottom electrode of described mos capacitance;

(2) form the dielectric layer of described mos capacitance with the gate dielectric layer of reading MOS transistor, the synchronous composition of gate dielectric layer of writing MOS transistor;

(3) form the top electrode of described mos capacitance with the gate electrode of reading MOS transistor, the synchronous composition of gate electrode of writing MOS transistor.

The top electrode of described mos capacitance and the described gate electrode of reading MOS transistor link together.

The present invention further provides a kind of gain cell eDRAM, comprising:

The gain cell eDRAM array, it is arranged by the form of row and column by arbitrary aforesaid gain cell eDRAM unit and forms;

Line decoder;

Column decoder;

Sense amplifier;

The word line driver module;

The bit-line drive module;

Logic control module is used for controlling described word line driver module and described bit-line drive module keep operation and refresh operation in read operation, write operation, data sequential.

Technique effect of the present invention is, by increase mos capacitance at the memory node place, the memory capacitance at memory node place is increased, improve the data hold time (the especially retention time of data " 1 ") of gain cell eDRAM unit, reduce refreshing frequency, reduce the power consumption of the storer formed by this gain cell eDRAM unit.Simultaneously since the mos capacitance that is increased can with standard MOS process compatible, the preparation of gain cell eDRAM unit does not compared to existing technology need to increase in addition processing step, therefore has the low characteristics of preparation cost.

Description of drawings

Fig. 1 is the gain cell eDRAM cellular construction synoptic diagram of prior art;

Fig. 2 is the physical arrangement synoptic diagram of gain cell eDRAM shown in Figure 1 unit;

Fig. 3 is the electrical block diagram of the gain cell eDRAM unit of first embodiment provided by the invention;

Fig. 4, Fig. 5 are the physical arrangement embodiment synoptic diagram of gain cell eDRAM embodiment illustrated in fig. 3 unit, and wherein Fig. 4 is the plan view from above of gain cell eDRAM embodiment illustrated in fig. 3 unit, and Fig. 5 is the structural representation in the A-A cross section of Fig. 4;

Fig. 6 is the C-V curve of mos capacitance embodiment illustrated in fig. 4;

Fig. 7 is the another embodiment synoptic diagram of the physical arrangement of gain cell eDRAM embodiment illustrated in fig. 3 unit;

Fig. 8 is a gain cell eDRAM memory construction synoptic diagram provided by the invention, that be made up of gain cell eDRAM unit cell arrangement embodiment illustrated in fig. 3.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.

Figure 3 shows that the electrical block diagram of the gain cell eDRAM unit of first embodiment provided by the invention.As shown in Figure 3, this gain cell eDRAM unit 400 comprise write MOS transistor 401, read MOS transistor 402, equivalent parasitic capacitances 404, mos capacitance 405, write word line (Write Word Line, WWL) 406, write bit line (Write Bit Line, WBL) 407, readout word line (Read Word Line, RWL) 408, sense bit line (Read Bit Line, RBL) 409.Wherein, the grid of writing MOS transistor 401 is connected to WWL, controlled by WWL thereby write MOS transistor 401; The source end of MOS transistor 401 (perhaps drain terminal) meets WBL, and the drain terminal of MOS transistor 401 (perhaps source end) connects the grid of reading MOS transistor 402; The source end (perhaps drain terminal) of reading MOS transistor 402 meets RWL, and the drain terminal (perhaps source end) of reading MOS transistor 402 meets RBL.Therefore, according to the stray capacitance of MOS crystal as can be known, can there be an equivalent parasitic capacitances, i.e. equivalent parasitic capacitances shown in Fig. 3 404 in the junction of the grid of reading MOS transistor 402 and the drain terminal (perhaps source end) of writing metal-oxide-semiconductor 401.This equivalence stray capacitance 404 dots, and is because this electric capacity is not self-existent capacitor element, but gate capacitance or above the two the parallel connection combination writing the active area stray capacitance of MOS transistor 401 or read MOS transistor 402.Read the grid of MOS transistor 402 and the junction formation memory node 403 of the drain terminal (perhaps source end) of writing metal-oxide-semiconductor 401.In this embodiment, mos capacitance 405 is parallel forms with equivalent parasitic capacitances 403, and the one end connects memory node 403.Therefore, mos capacitance 405 is the same with equivalent parasitic capacitances 403, also is to be used for stored charge realization data storage, because the existence of mos capacitance 405, compare independent equivalent parasitic capacitances 404 stored charges of using, it can be used for increasing the stored charge of gain cell eDRAM unit.In this embodiment, the capacitance size of mos capacitance 405 is 0.3-10 times of equivalent parasitic capacitances 404, and preferably, about 0.5-1 times, for example, under 0.13 micron process node, the capacitance size of mos capacitance 405 is 0.8 times of equivalent parasitic capacitances 404.

In one example, when equivalent parasitic capacitances 404, mos capacitance 405 stored charges, memory node 403 is noble potentials, represent this eDRAM unit storage data " 1 ", when equivalent parasitic capacitances 404, when mos capacitance 405 discharges electric charge, memory node 403 is electronegative potentials, represents this eDRAM unit storage data " 0 ".Certainly, also can select opposite form to define store status.In this was embodiment illustrated in fig. 3, writing MOS transistor 401, reading MOS transistor 402 was the PMOS transistor, when its gate voltage is negative voltage signal, can make transistor 401 and 402 conductings.

The method of operating of the method for operating of gain cell eDRAM shown in Figure 3 unit 400 and the gain cell eDRAM unit 100 of prior art shown in Figure 1 is basic identical.

Fig. 4, Figure 5 shows that the physical arrangement embodiment synoptic diagram of gain cell eDRAM embodiment illustrated in fig. 3 unit.Wherein Fig. 4 is the plan view from above of gain cell eDRAM embodiment illustrated in fig. 3 unit, and Fig. 5 is the structural representation in the A-A cross section of Fig. 4.

See also Fig. 4, compare and Fig. 3, omit and provided write word line, write bit line, readout word line, sense bit line.Wherein, 301 for writing the active area of MOS transistor, and 302 for writing the grid of MOS transistor, and 305 for reading the active area of MOS transistor, and 306 for reading the grid of MOS transistor; The active area 301 of writing MOS transistor is connected by metal wire 307 with the grid 306 of reading MOS transistor.This gain cell eDRAM unit also comprises the top electrode 308 of mos capacitance.Wherein the frame of broken lines zone is the memory node 304 of this gain cell eDRAM unit, and this memory node 304 has reflected the active area stray capacitance of writing MOS transistor, the gate capacitance of reading MOS transistor and mos capacitance, and mos capacitance places this memory node place.

Fig. 4 is than the physical arrangement of prior art gain cell eDRAM unit 200 shown in Figure 2, in this embodiment, on the basis of original scheme 200, under the situation that the cellar area that guarantees to write MOS transistor does not increase, composition definition active area 301 and 305 o'clock, with the area in the drain region of writing MOS transistor active area (drain region with the grid of reading MOS transistor be electrically connected) relevant with memory node 304 do bigger to form bottom electrodes 303 of mos capacitance, wherein, the border of bottom electrode 303 of writing MOS transistor is shown in the dotted line under the top electrode 308 of mos capacitance among the figure, but owing to have gate medium between drain region and the top electrode 308, it can stop the ion when forming the drain region to inject, therefore, the drain region under the top electrode 308 is actually substrate bottom electrode 303 (under 308 among Fig. 5).Substrate part 303 has formed the bottom electrode of mos capacitance under the top electrode 308 of mos capacitance.In this embodiment, the dielectric layer of mos capacitance zone is the top electrode 308 of mos capacitance and the overlapping region of bottom electrode 303, and the top electrode of the top electrode 308 of mos capacitance is done as a whole linking together with the gate electrode 306 of reading MOS transistor.

Further consult Fig. 5, in conjunction with Fig. 4 and Fig. 5, wherein the represented electric capacity of solid line is the electric capacity with respect to eDRAM unit of gain unit shown in Figure 2 increased newly, wherein, 3042 are the mos capacitance (Cox_add) that increases newly, and 3041 for because of the increase of the active area stray capacitance that expansion caused of the drain region area of writing the MOS transistor active area partly (Cj_add).Wherein the represented electric capacity of dotted line is equivalent parasitic capacitances (Cj, Cox_read).

Therefore, by Fig. 3, Fig. 4, Fig. 5 associated description as can be known, the memory capacitance of storing data not only comprised and write MOS transistor active area stray capacitance, reads the equivalent parasitic capacitances that the pipe gate capacitance of MOS crystal is combined to form being used to of gain cell eDRAM unit, the mos capacitance that also comprises necessary being, therefore increased the memory capacitance of memory node, can improve the data hold time (the especially retention time of data " 1 ") of gain cell eDRAM unit, reduce refreshing frequency, reduce the power consumption of the storer formed by this gain cell eDRAM unit.

In the embodiment shown in fig. 4, because substrate is that P type, drain region are the N type, the curve of the mos capacitance of formation Figure 6 shows that the C-V curve of the mos capacitance of this embodiment as shown in Figure 6.Horizontal ordinate is the voltage Vgs that the metal-oxide-semiconductor top electrode is setovered, and ordinate is the capacitance Cgs of mos capacitance.Because the gate capacitance (Cgs) that mos capacitance shows when accumulation area and strong inversion district is maximum, and be smaller in the gate capacitance (Cgs) that weak inversion regime shows, this embodiment mos capacitance top electrode 308 with read under the situation that MOS transistor gate electrode 306 is connected as a single entity, when memory node 304 is deposited " 1 ", when promptly putting high level, the mos capacitance that is equivalent to neotectonics is biased in the strong inversion district, the Cgs added value that obtains will be bigger, thereby the storage capacitance value of memory node can be stored more electric charge when depositing " 1 ", and the retention time that shows as data " 1 " is longer.And when storing " 0 " (in the electric capacity not stored charge), its data hold time is not a principal element, so this scheme can more effectively increase the data hold time of this storage unit.The simulation result of the gain cell eDRAM unit of comparison diagram 2 and structure shown in Figure 4, the data hold time of scheme shown in Figure 4 have increased by 40.6% (emulated data under the 0.13um).

Further, the manufacturing of this mos capacitance and standard MOS technology are compatible mutually, therefore, than traditional DRAM unit, have overcome because memory capacitance and the incompatible difficulty of bringing of standard MOS technology.Below among the preparation method to Fig. 3, Fig. 4, gain cell eDRAM unit shown in Figure 5, how concrete mos capacitance is explained with standard MOS process compatible:

Step 1 is not increasing under the situation of writing MOS transistor device cell area, increases and reads the area of writing the MOS transistor active area that the MOS transistor grid is connected, and forms the bottom electrode (bottom electrode 303 zones under 308 parts among Fig. 4) of mos capacitance.Therefore, the bottom electrode of mos capacitance can form in same step with the active area of writing MOS transistor.

Step 2 is with the gate dielectric layer of reading MOS transistor, write the dielectric layer that the synchronous composition of the gate dielectric layer of MOS transistor forms mos capacitance.Therefore, the dielectric layer of mos capacitance can form in same step with the gate dielectric layer of reading MOS transistor, the gate dielectric layer of writing MOS transistor.

Step 3 is with the gate electrode of reading MOS transistor, write the top electrode 308 that the synchronous composition of the gate electrode of MOS transistor forms mos capacitance.Therefore, the top electrode 308 of mos capacitance can form in same step with the gate electrode 306 of reading MOS transistor, the gate electrode 302 of writing MOS transistor.

The formation method of the reading MOS transistor, write MOS transistor of concrete gain cell eDRAM unit, write word line, write bit line, readout word line, sense bit line is consistent with method of the prior art, does not elaborate in addition at this.As from the foregoing, behind the increase mos capacitance, the eDRAM preparation process basically identical of the preparation process of gain cell eDRAM unit and prior art does not need additionally to increase step, only needs to revise the part layout design and gets final product.Therefore, the gain cell eDRAM unit that provides of this invention has the low characteristics of preparation cost equally.

In above Fig. 3, Fig. 4 and the gain cell eDRAM unit embodiment illustrated in fig. 5, reading MOS transistor, writing MOS transistor is PMOS.According to those skilled in the art's knowledge, also can read MOS transistor, write MOS transistor and be set to nmos pass transistor, the principle of work of its gain cell eDRAM unit, preparation aspect are basic identical, this embodiment are not described in detail at this.

Figure 7 shows that the another embodiment synoptic diagram of physical arrangement of gain cell eDRAM embodiment illustrated in fig. 3 unit.Comparison diagram 4 and Fig. 7, the difference of this embodiment is that the top electrode 308 of mos capacitance and the gate electrode 306 of reading MOS transistor are isolated.But the formation method of mos capacitance is with described above consistent, only need do trickle modification to the domain of that one deck of forming gate electrode 306 and get final product.Therefore, the mos capacitance of this embodiment equally can with standard MOS process compatible, thereby the preparation cost of this embodiment gain cell eDRAM unit is low.Equally,, the memory capacitance of memory node can be increased, data hold time (the especially retention time of data " 1 "), the reduction refreshing frequency of gain cell eDRAM unit can be improved owing to increased mos capacitance.Just because the top electrode 308 of mos capacitance is to be in floating dummy status all the time, when storage data " 1 ", mos capacitance is not in the strong inversion state, the gate capacitance increase of acquisition is smaller in fact, so its simulation result has only shown the increase of 16.4% data hold time.

This invention further provides the storer that comprises the gain cell eDRAM unit described in this specific embodiment.

Figure 8 shows that gain cell eDRAM memory construction synoptic diagram provided by the invention, that form by gain cell eDRAM unit cell arrangement embodiment illustrated in fig. 3.This single eDRAM storer that gains comprises the gain unit array, and the gain unit array is to be arranged by the form of row and column by gain unit to form.Word line and bit line cross arrangement, gain unit place the cross arrangement point.This single eDRAM storer that gains also comprises line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module.The function of Logic control module is that control word line driver module and bit-line drive module keep the sequential in operation and the refresh operation in read operation, write operation, data.Wherein selected line chooses the bit-line voltage of row to change and can differentiate by sense amplifier, and compares with Vref (reference voltage), obtains sense data.Row address is counted the line of input code translator, is used for choosing the WWL and the RWL of array, column address input column decoder.

Although the description of this invention is to make in the mode of reference example and preferred embodiment, those skilled in the art arrives cognition, under the prerequisite that does not depart from the scope of the present invention with spirit, can make change on form or details.

Claims (9)

1. gain cell eDRAM unit, comprise read MOS transistor, write MOS transistor, the equivalent parasitic capacitances at write word line, write bit line, readout word line, sense bit line and memory node place, it is characterized in that, also comprise the mos capacitance, the manufacturing of described mos capacitance and the standard MOS process compatible that place stored charge described memory node place, that be used to increase the gain cell eDRAM unit.

2. gain cell eDRAM according to claim 1 unit, it is characterized in that, the bottom electrode of described mos capacitance is a substrate, the dielectric layer of described mos capacitance with the gate dielectric layer of reading MOS transistor, write the synchronous composition of the gate dielectric layer of MOS transistor and form, the top electrode of described mos capacitance and the gate electrode of reading MOS transistor, the synchronous composition of gate electrode of writing MOS transistor form.

3. gain cell eDRAM according to claim 2 unit is characterized in that, the top electrode of described mos capacitance and the described gate electrode of reading MOS transistor link together.

4. gain cell eDRAM according to claim 2 unit is characterized in that, the top electrode of described mos capacitance and the described gate electrode of reading MOS transistor are isolated.

5. gain cell eDRAM according to claim 2 unit is characterized in that, is not increasing under the situation of reading MOS transistor device cell area, increases and the area of reading the active area that the MOS transistor grid is connected, is used for forming described mos capacitance.

6. gain cell eDRAM according to claim 1 unit is characterized in that, the described MOS transistor of reading is the PMOS transistor with writing MOS transistor; The perhaps described MOS transistor of reading is a nmos pass transistor with writing MOS transistor.

7. the preparation method of a gain cell eDRAM unit, with the eDRAM unit read MOS transistor or write MOS transistor synchronously, be used for increasing the mos capacitance of the stored charge of gain cell eDRAM unit with the preparation of MOS technology, specifically

Step comprises:

(1) do not increasing under the situation of writing MOS transistor device cell area, increasing and read the area of writing the MOS transistor active area that the MOS transistor grid is connected, forming the bottom electrode of described mos capacitance;

(2) form the dielectric layer of described mos capacitance with the gate dielectric layer of reading MOS transistor, the synchronous composition of gate dielectric layer of writing MOS transistor;

(3) form the top electrode of described mos capacitance with the gate electrode of reading MOS transistor, the synchronous composition of gate electrode of writing MOS transistor.

8. the preparation method of gain cell eDRAM according to claim 7 unit is characterized in that, the top electrode of described mos capacitance and the described gate electrode of reading MOS transistor link together.

9. a gain cell eDRAM is characterized in that, comprising:

The gain cell eDRAM array, it is arranged by the form of row and column by the arbitrary described gain cell eDRAM of claim 1-6 unit and forms;

Line decoder;

Column decoder;

Sense amplifier;

The word line driver module;

The bit-line drive module;

Logic control module is used for controlling described word line driver module and described bit-line drive module keep operation and refresh operation in read operation, write operation, data sequential.

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