CN101853697B - Gain cell embedded dynamic random access memory (eDRAM) unit, memory and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of dynamic random access memories (DRAM), and in particular discloses a gain cell eDRAM unit, a memory and a preparation method thereof. The gain cell eDRAM unit comprises a read MOS transistor, a write MOS transistor, a write word line, a write bit line, a read word line, a read bit line and an equivalently parasitical capacitor, wherein the drain of the write MOS transistor is electrically connected with the grid of the read MOS transistor; the depth of the drain of the write MOS transistor is greater than that of the source of the write MOS transistor; and the drain doping concentration of the write MOS transistor is set to reduce the drain current of a PN junction of the drain. The gain cell eDRAM has the characteristic of long data hold time. The memory consisting of the gain cell eDRAM unit has the characteristics of low refresh rate and low power consumption.

Description

Gain cell eDRAM unit, storer and preparation method thereof

Technical field

The invention belongs to dynamic RAM (DRAM) technical field, be specifically related to a kind of embedded DRAM (eDRAM) technology, relate in particular to a kind of gain cell eDRAM that MOS transistor is unsymmetric structure (Gain Cell eDRAM) unit, storer and preparation method thereof write.

Background technology

Storer can be divided into chip external memory and in-line memory, in-line memory be a kind of be integrated in the chip with chip system in the element of the common compositing chips of IP module such as each logic, mixed signal.In-line memory comprises embedded static RAM (eSRAM) and embedded DRAM (eDRAM), wherein, eDRAM is because its unit includes only a transistor and an electric capacity, and six transistors of eSRAM unit have the little characteristics of cellar area relatively.

But, the manufacturing that the difficult point of traditional eDRAM is its electric capacity generally not with standard MOS process compatible, thereby DRAM technique and conventional logic process are widely different, the integration difficult of technique.Therefore industry has proposed to come with the stray capacitance of metal-oxide-semiconductor self thought of electric capacity among the equivalent substitute DRAM.

See also Fig. 1, Figure 1 shows that the electrical block diagram of the gain cell eDRAM unit of prior art.This eDRAM is proposed in US Patent No. 7120072 by Intel Company, as shown in Figure 1, this Gain Cell eDRAM 100 comprise write MOS transistor 101, read MOS transistor 102, write word line (Write Word Line, WWL) 105, readout word line (Read Word Line, RWL) 106, write bit line (Write Bit Line, WBL) 107, sense bit line (Read Bit Line, RBL) 108 and equivalent parasitic capacitances 104(equivalent parasitic capacitances do not exist as an individual devices, just schematically illustrate separately among the figure).Wherein, the drain region of writing MOS transistor 101 is connected in the grid of reading MOS transistor 102, and MN point 103 is memory node, equivalent parasitic capacitances 104 1 ends are connected with 103, other end ground connection, therefore, conducting and shutoff that MOS transistor 102 is read in the high low energy control of the current potential that MN is ordered; For example, during electric capacity 104 stored charge, representative storage " 1 ", MN point 103 is noble potential, can control and read MOS transistor 102 shutoffs.Read a termination RBL of MOS transistor 102, another termination RWL; Write a termination WBL of MOS transistor 101, another termination is read the grid of MOS transistor 102.Normally, equivalent parasitic capacitances 104 is for writing the active area stray capacitance (also being the stray capacitance in drain region) of MOS transistor 101 or reading the gate capacitance of MOS transistor 102, also or both combinations.Specify its operating process below in conjunction with operating list:

1, write operation (Write): when writing " 0 ", RWL, RBL set to 0 current potential, read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL sets to 0 V, thus equivalent parasitic capacitances 104 discharges, and memory node 103 current potentials are 0.During one writing, RWL, RBL set to 0 current potential, read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 1V, thus equivalent parasitic capacitances 104 chargings, and memory node 103 current potentials are noble potential.

(Hold): RWL, RBL set to 0 current potential when 2, data kept, and read MOS transistor 102 and did not work, and WWL puts 1V, write MOS transistor 101 and turn-offed, and the current potential of memory node 103 is not subjected to ectocine.

3, read operation (Read): when reading " 0 ", WWL puts 1V, and WBL sets to 0 V, writes MOS transistor 101 and turn-offs; The RWL biasing is less than 1V, and RBL sets to 0 V, and read MOS transistor 102 conductings this moment, and RWL charges to RBL by reading MOS transistor, because sensing circuit has clamping action, the electrical potential energy of RBL reaches 200mV, thereby can sense data " 0 ".When reading " 1 ", WWL puts 1V, and WBL sets to 0 V, writes MOS transistor 101 and turn-offs; The RWL biasing is read MOS transistor 102 this moment and is turn-offed less than 1V, and RWL can not charge to RBL by reading MOS transistor, and RBL keeps the 0V current potential, thereby can sense data " 1 ".

Gain Cell eDRAM unit shown in Figure 1 does not need to make in addition electric capacity, adopt standard CMOS process, and the relative eSRAM of its structure is simpler, can realize highdensity embedded storage.But, because equivalent parasitic capacitances 104 is for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102 or for writing the active area stray capacitance of MOS transistor 101 and the combination of reading the gate capacitance of MOS transistor 102, the capacitance less of equivalent parasitic capacitances 104.The charge retention time of equivalent parasitic capacitances 104 storages has reflected the data retention characteristics of this gain cell eDRAM unit, and charge retention time is longer, and the required frequency that refreshes just power consumption lower, storer is also just lower.Generally, the leakage current path of 104 stored charges of equivalent parasitic capacitances of this gain cell eDRAM unit has multiple, for example, by the subthreshold value electric leakage of writing MOS transistor 10, the electric leakage by writing MOS transistor 101 and reading the grid oxide layer of MOS transistor 102.Wherein, active area (drain region) the stray capacitance stored charge of writing MOS transistor 101 is easier of the knot between source and the substrate (PN junction) leakage, thereby greatly reduces the data hold time of this storer.Particularly only have the data hold time of 10us at employing standard logic process under 65nm, thereby the memory refress frequency is high, power consumption increases.

Figure 2 shows that the vertical view of gain cell eDRAM shown in Figure 1 unit, Figure 3 shows that the cross sectional elevation of gain cell eDRAM shown in Figure 1 unit.In the prior art, gain cell eDRAM unit shown in Figure 1 is by application drawing 2 and physical arrangement shown in Figure 3 and finish manufacturing.In this embodiment, write MOS transistor and read MOS transistor and be PMOS pipe.In conjunction with Fig. 2 and shown in Figure 3, wherein, 201 for writing the source of MOS transistor 101,202 for writing the grid of MOS transistor 101,203 for writing the drain terminal of MOS transistor 101, and 205 for reading the active area (source or drain terminal) of MOS transistor 102, and 206 for reading the grid of MOS transistor 102; The electric capacity (equivalent parasitic capacitances) that is used for stored charge is electric capacity shown in dotted lines in Figure 3 (gate capacitance of the junction capacity of drain terminal 203 and grid 206), for the drain terminal 203 of writing MOS transistor connects by metal wire 207 with the grid 206 of being connected MOS transistor.The memory node 204(that zone in the block diagram of dotted line shown in Fig. 2 is this eDRAM unit is drain terminal and the grid of 204 indications shown in Figure 3).On the metal wire 207 of memory node 204, can reflect the storage current potential (electric charge is more in the equivalent parasitic capacitances, current potential is higher) of equivalent parasitic capacitances.The equivalent parasitic capacitances that electric capacity shown in the dotted line among Fig. 3 forms is when stored charge, and easily the junction capacity of the drain terminal by writing MOS transistor is leaked.

In view of this, be necessary to propose a kind of eDRAM unit of new structure to improve the data hold time of eDRAM unit.

Summary of the invention

The technical problem to be solved in the present invention is to improve the stored charge leakage problem of the equivalent parasitic capacitances of eDRAM unit, to improve the data hold time of eDRAM unit.

For solving above technical matters, according to first aspect of the present invention, a kind of gain cell eDRAM unit is provided, it comprise read MOS transistor, write MOS transistor, write word line, write bit line, readout word line, sense bit line and equivalent parasitic capacitances, the described drain terminal of writing MOS transistor is electrically connected with the grid of reading MOS transistor, the degree of depth of the described drain terminal of writing MOS transistor is greater than the described degree of depth of writing the source of MOS transistor, the described drain terminal doping concentration distribution of writing MOS transistor is set with the leakage current of the PN junction that reduces drain terminal.

As the preferred technique scheme, the described average doping content of writing the drain terminal of MOS transistor is lower than the described average doping content of writing the source of MOS transistor.Particularly, the described average doping content of writing the drain terminal of MOS transistor be the described source of writing MOS transistor average doping content 40% to 90%.

As another preferred technique scheme, the shared area of the described drain terminal of writing MOS transistor is greater than the shared area of the source of described MOS transistor.Particularly, perpendicular to the size of channel direction, the described drain terminal of writing MOS transistor greater than the described size of writing the source of MOS transistor.

As a preferred technique scheme again, the doping content of the described drain terminal of writing MOS transistor is perpendicular to the substrate surface direction, reduce with gradual form from top to bottom.

Particularly, the described degree of depth of writing the drain terminal of MOS transistor is 1.1 to 2 times of the degree of depth of the described source of writing MOS transistor.

According to another aspect of the present invention, a kind of method for preparing gain cell eDRAM of the present invention unit is provided, wherein, increase the independent composition doping step to the drain terminal of writing MOS transistor, with the degree of depth of the drain terminal that increases MOS transistor and adjust its doping concentration distribution.

Particularly, may further comprise the steps:

(1) provide the first doping type, be used to form the substrate of reading MOS transistor and writing MOS transistor;

(2) to described source and the drain terminal of reading MOS transistor, writing MOS transistor, carry out simultaneously the light dope first time of the second doping type;

(3) separately to the described drain terminal of writing MOS transistor carry out the second doping type the second time light dope with the degree of depth of the drain terminal that increases MOS transistor;

(4) to the described source of MOS transistor, the source of reading MOS transistor and the drain terminal write, carry out simultaneously the heavy doping of the second doping type.

Described first time, light dope was that lightly doped drain mixes.

Provide a kind of gain cell eDRAM more on the one hand according to of the present invention, it comprises:

The gain cell eDRAM array, it comprises a plurality of the above arbitrary middle gain cell eDRAM unit that reach of arranging by the form of row and column;

Line decoder;

Column decoder;

Sense amplifier;

Word line driver module;

The bit-line drive module;

Logic control module is for controlling described word line driver module and the described bit-line drive module sequential at read operation, write operation, data maintenance operation and refresh operation.

Technique effect of the present invention is, improve by the structure of writing MOS transistor to the gain cell eDRAM unit, increase the degree of depth of its drain terminal and adjust its dopant profiles, electric field intensity with the PN junction place of the drain terminal that reduces to write MOS transistor, thereby reduce the leakage current of the PN junction of drain terminal, the leakage rate of stored charge of equivalent parasitic capacitances of memory node slows down, increased the data hold time of gain cell eDRAM, reduced the refreshing frequency of the storer that is formed by this gain cell eDRAM unit, the power consumption of the storer that has reduced.

Description of drawings

Fig. 1 is the electrical block diagram of the gain cell eDRAM unit of prior art.

Fig. 2 is the vertical view of gain cell eDRAM shown in Figure 1 unit.

Fig. 3 is the cross sectional elevation of gain cell eDRAM shown in Figure 1 unit.

Fig. 4 is the vertical view according to the gain cell eDRAM unit of the first embodiment provided by the invention.

Fig. 5 is the A-A cross sectional elevation of gain cell eDRAM embodiment illustrated in fig. 4 unit.

Fig. 6 is the vertical view according to the gain cell eDRAM unit of the second embodiment provided by the invention.

Fig. 7 is eDRAM memory construction synoptic diagram provided by the invention.

Fig. 8 A-8C is the procedure of reading MOS transistor and writing MOS transistor of preparation gain cell eDRAM.

Embodiment

The below introduces is a plurality of some in may embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.

Figure 4 shows that the vertical view according to the gain cell eDRAM unit of the first embodiment provided by the invention; Figure 5 shows that the A-A cross sectional elevation of gain cell eDRAM embodiment illustrated in fig. 4 unit.As shown in Figure 4 and Figure 5, the eDRAM unit 300 of this embodiment is similarly that shown in Figure 1 comprising write MOS transistor, read MOS transistor, the structure of write word line, write bit line, readout word line and readout word line, therefore, the electrical block diagram of eDRAM unit 300 is identical with the electrical block diagram of eDRAM unit shown in Figure 1, write MOS transistor, read MOS transistor, the annexation between write word line, write bit line, readout word line and the readout word line and the function that realizes be also identical, do not remake at this and give unnecessary details.

Continue as shown in Figure 4 and Figure 5, wherein Fig. 4 omits and has provided write word line, write bit line, readout word line, sense bit line.Particularly, 301 for writing the source of MOS transistor, and 302 for writing the grid of MOS transistor, and 303 for writing the drain terminal of MOS transistor, and 305 for reading the active area (source or drain terminal) of MOS transistor, and 306 for reading the grid of MOS transistor; The source 301 of writing MOS transistor connects by metal wire 307 with the grid 306 of being connected MOS transistor.Wherein dotted line frame zone is the memory node 304 of this gain cell eDRAM unit, and this memory node 304 has comprised the active area stray capacitance (Cj) of writing MOS transistor and the gate capacitance (Cox) of reading MOS transistor.

In this invention, for the leakage current of the PN junction that reduces to write MOS transistor so that memory node to be used for the charge leakage of stray capacitance of the information of storing slower, to write MOS transistor and be designed to unsymmetric structure, wherein, as shown in Figure 5, the degree of depth of writing the drain terminal 303 of MOS transistor strengthens, and it is greater than the degree of depth of the source 301 of writing MOS transistor; In addition, the doping content of the drain terminal 303 write MOS transistor is set, reduces to write the electric field intensity that the PN junction (drain terminal 303 can and substrate form PN junction) of the drain terminal 303 of MOS transistor is located, like this, the leakage current of PN junction will reduce.Preferably, the average doping content of writing the drain terminal 303 of MOS transistor is lower than the average doping content of source 301, for example, when drain terminal 303 and source 301 are the doping of P type, source 301 can be heavy doping, and drain terminal 303 is relative light dope, and particularly, the average doping content of drain terminal 303 can be 40% to 90% of the average doping content of source 301.In the preferred embodiment, perpendicular to substrate surface direction (also being the horizontal direction among Fig. 5), the doping content of drain terminal 303 reduces in gradual mode from top to bottom, exists like this, the electric-field intensity distribution of the drain terminal 303 at PN junction place can be lower, further reduces the leakage current of PN junction.For example, the electric field intensity of drain terminal 303 can be with the 30%-60% for the electric field intensity of the traditional drain terminal 303 of writing MOS transistor.In addition, particularly, the degree of depth of writing the drain terminal 303 of MOS transistor can be 1.1 to 2 times of the degree of depth of the source 301 of writing MOS transistor.

Figure 6 shows that the vertical view according to the gain cell eDRAM unit of the second embodiment provided by the invention.As shown in Figure 6, in this second embodiment, the key distinction with respect to the first embodiment shown in Figure 4 is drain terminal 403, when the drain terminal 403 of writing MOS transistor being done transistorized variation arranges shown in Fig. 4, also increase drain terminal 403 sizes in the direction (also being the width of MOS transistor) perpendicular to the communication of writing MOS transistor, thereby the area that the drain terminal 403 that increases MOS transistor is shared, make its area greater than the area of source 301, like this, equivalent parasitic capacitances as memory capacitance can increase because of area, can relatively further improve the data hold time (the especially retention time of data " 1 ") of gain cell eDRAM unit 400, reduce refreshing frequency, reduce the power consumption of the storer that formed by this gain cell eDRAM unit.

This invention further provides the storer that comprises the gain cell eDRAM unit described in arbitrary specific embodiment.

Figure 7 shows that eDRAM memory construction synoptic diagram provided by the invention.This single eDRAM storer that gains comprises the gain unit array, and the gain unit array is to be arranged by the form of row and column by the gain cell eDRAM unit to form, and wherein, the gain cell eDRAM unit is the gain cell eDRAM unit of above Fig. 4 or Fig. 6 embodiment.Word line and bit line cross arrangement, gain unit place the cross arrangement point.This gain cell eDRAM storer also comprises line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module.The function of Logic control module is that control word line driver module and bit-line drive module keep the sequential in operation and the refresh operation in read operation, write operation, data.Wherein selected line chooses the bit-line voltage of row to change and can differentiate by sense amplifier, and with the Vref(reference voltage) relatively, obtain sense data.Row address is counted the line of input code translator, is used for choosing WWL and the RWL of array, column address input column decoder.

Further specify the method for preparation gain cell eDRAM unit embodiment illustrated in fig. 6 in following examples.

Fig. 8 A-8C is depicted as the procedure of reading MOS transistor and writing MOS transistor of preparation gain cell eDRAM.Because in this invention, mainly concentrate on the stored charge leakage rate that the structure of writing MOS transistor is improved to reduce the gain cell eDRAM unit, therefore, to its preparation method, article is write preparation method's process of MOS transistor, relates in particular to the preparation process of source drain terminal.In this embodiment, writing MOS transistor and reading MOS transistor and be the PMOS transistor and describe as example take the gain cell eDRAM unit of preparation.

Shown in Fig. 8 A, after the associated process steps before doping is leaked in the source of finishing (for example numerous processing step of channel doping, shallow groove isolation layer formation etc.), the part that wish forms source and drain areas is exposed to prepare to carry out to the open air the doping first time, in this embodiment, substrate is that N-type is mixed, source 301 and drain terminal 403, the source of reading MOS transistor and the drain terminal of writing MOS transistor carried out P type light dope, particularly, be the LDD(lightly doped drain) mix (to prevent the electronics degradation effect).Wherein, can select BF ₂Deng as doped source, doping way is generally Implantation.In this process, the degree of depth of controlled doping.Need to prove that in this embodiment, the area of the composition of drain terminal 403 is greater than the area of the composition of source 301, perpendicular to channel direction, the size of drain terminal 403 is greater than the size (not shown) of source 301.

Continuation after having carried out above step, also can form abutment wall in the both sides, edge, the left and right sides of grid 302 and 306 usually shown in Fig. 8 B, it mainly is in order to form the LDD district.Then, separately drain terminal 403 is carried out composition, for example, form the figure of photoresist 405 as shown in the figure, with its mask as doping, the surface area of drain terminal 403 is carried out P type light dope for the second time with the degree of depth of the drain terminal that greatly increases MOS transistor, and particularly, the degree of depth of writing the drain terminal 403 of MOS transistor can be 1.1 to 2 times of the degree of depth of the final source of writing MOS transistor 301 that forms.Wherein, can select B etc. as doped source, doping way is generally Implantation.The above light dope that reaches mainly is with respect to the heavy doping of following steps.Lightly doped concrete concentration for the second time, those skilled in the art can select according to specific requirement, preferably, the doping content that can make the drain terminal of writing MOS transistor is perpendicular to the substrate surface direction, reduce with gradual form from top to bottom, thereby is conducive to reduce the leakage current of the PN junction of drain terminal.

Continuation is shown in Fig. 8 C, after finishing the doping of drain terminal 403, adopt photoresist 406 as masked drain terminal 403 zones, to the source 301 of writing MOS transistor, the source of reading MOS transistor and drain terminal, carry out simultaneously the heavy doping of P type, read MOS crystal source and drain terminal, write the source 301 of MOS transistor with final formation, therefore, the average doping content of writing the source 301 of MOS transistor can be greater than the average doping content of drain terminal 403.In this doping process, when for example adopting ion implantation doping, the energy of control Implantation with the degree of depth of controlled doping, thereby makes the formed source 301 of writing MOS transistor, the degree of depth of reading MOS crystal source and drain terminal is all less than the degree of depth of the drain terminal 403 of writing MOS transistor.

After above step, also can form successively readout word line, sense bit line, write word line, write bit line of gain cell eDRAM etc., the formation method of the method for its formation and prior art is basic identical, and is conventionally known to one of skill in the art, does not give unnecessary details one by one at this.

Need to prove, more than just with form the PMOS transistor types read MOS transistor and write MOS transistor describe, those skilled in the art can be used to form its similar method reading MOS transistor and writing MOS transistor of nmos pass transistor type equally.

Among the above embodiment, although just the concrete structure of the gain cell eDRAM unit that is similar to circuit structure shown in Figure 1 is illustrated, but, it is writing structure on the MOS transistor and preparation method thereof improved thought, can be applied to equally in the different circuit structure gain cell eDRAMs unit, for example, can also be applied to the gain cell eDRAM unit that is used for programmable logic device (PLD) of gain cell eDRAM unit that bit line merges, band isolation metal-oxide-semiconductor, in addition with the gain cell eDRAM unit of store M OS electric capacity etc.

Above example has mainly illustrated gain cell eDRAM of the present invention unit, preparation method and by this formed storer in gain cell eDRAM unit.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and embodiment are regarded as illustrative and not restrictive, and in situation about not breaking away from such as the defined spirit of the present invention of appended each claim and scope, the present invention may be contained various modifications and replacement.

Claims (7)

1. eDRAM unit, comprise and read MOS transistor, write MOS transistor, write word line, write bit line, readout word line, sense bit line and equivalent parasitic capacitances, connection between these parts is identical with the connection between the existing eDRAM unit corresponding component, the described drain terminal of writing MOS transistor is electrically connected with the grid of reading MOS transistor, it is characterized in that, the degree of depth of the described drain terminal of writing MOS transistor is greater than the described degree of depth of writing the source of MOS transistor, the described average doping content of writing the drain terminal of MOS transistor is set is lower than the described average doping content of writing the source of MOS transistor, with the leakage current of the PN junction that reduces drain terminal;

Wherein, described equivalent parasitic capacitances is the gate capacitance of writing the active area stray capacitance of MOS transistor or reading MOS transistor, or both write the active area stray capacitance of MOS transistor and the combination of reading the gate capacitance of MOS transistor.

2. eDRAM as claimed in claim 1 unit is characterized in that, the shared area of the described drain terminal of writing MOS transistor is greater than the described shared area of source of writing MOS transistor.

3. eDRAM as claimed in claim 1 or 2 unit is characterized in that, the doping content of the described drain terminal of writing MOS transistor is perpendicular to the substrate surface direction, reduce with gradual form from top to bottom.

4. eDRAM as claimed in claim 2 unit is characterized in that, perpendicular to the size of channel direction, the described drain terminal of writing MOS transistor greater than the described size of writing the source of MOS transistor.

5. eDRAM as claimed in claim 1 unit is characterized in that, the described degree of depth of writing the drain terminal of MOS transistor is 1.1 to 2 times of the degree of depth of the described source of writing MOS transistor.

6. eDRAM as claimed in claim 1 unit is characterized in that, the described average doping content of writing the drain terminal of MOS transistor be the described source of writing MOS transistor average doping content 40% to 90%.

7. one kind prepares the as claimed in claim 1 method of eDRAM unit, it is characterized in that, increases the independent composition doping step to the drain terminal of MOS transistor, and with the degree of depth of the drain terminal that increases MOS transistor and adjust its doping concentration distribution, concrete steps are:

(1) provide the first doping type, be used to form the substrate of reading MOS transistor and writing MOS transistor;

(2) to described source and the drain terminal of reading MOS transistor, writing MOS transistor, carry out simultaneously the light dope first time of the second doping type;

(3) separately to the described drain terminal of writing MOS transistor carry out the second doping type the second time light dope with the degree of depth of the drain terminal that increases MOS transistor;

(4) to the described source of MOS transistor, the source of reading MOS transistor and the drain terminal write, carry out simultaneously the heavy doping of the second doping type;

Described first time, light dope was that lightly doped drain mixes.

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