CN102867540A - Operation method for raising multiport multichannel floating body memory performance - Google Patents
Operation method for raising multiport multichannel floating body memory performance Download PDFInfo
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Abstract
The invention, belonging to the technical field of memory, discloses an operation method for raising the performances of a multiport multichannel floating body memory, characterized in that: the multiport multichannel floating body memory disclosed herein comprises a plurality of memory cells, each memory cell is provided with n transistors, each transistor comprises a source region, a drain region, grids, and a body region arranged between the source region and the drain region, the source regions and the drain regions between adjacent transistors are mutually connected or shared, and when each transistor breakovers, a conducting channel is formed between the source and the drain of the transistor. The invention provides a solution for a multichannel embedded dynamic random memory with 90nm and under nodes, thus the operation windows, data-hold characteristics, accuracy, reliability, and other storage characteristics can be obviously improved.
Description
Technical field
The invention belongs to the memory technology field, proposed a kind of method of operating that improves multiport, many channel transistor structures device stores performance.
Background technology
Multiport, the embedded DRAM of many raceway grooves comprises several storage unit, each storage unit has n transistor (n is natural number, n 〉=2); Multiport, many raceway grooves floating body memory are as shown in Figure 1, here n=2, each storage unit has 2 transistors, each transistor comprises source region, drain region, grid and the tagma between source region and drain region, share the source region between adjacent transistor, during each transistor turns, form conducting channel between this transistorized source and leakage; Each transistor has 1 word line and 1 bit lines; Each transistorized bit line can link to each other with an input/output end port; Different crystal pipe in the storage unit is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side; The wordline bits line of different crystal pipe is to independently of one another, can be simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, can be simultaneously or the timesharing storage operation that reads and refresh by corresponding port.Refresh operation and read operation are separate, are independent of each other, and peripheral circuit can arrive the storage unit reading out data at any time, realize reading at a high speed with this.This device can be used as embedded DRAM, can significantly improve the speed of read operation, and can satisfy different power consumption demand by the frequency of adjusting refresh operation; When being used for static random-access, can greatly dwindle area and the power consumption of storage unit.Fig. 1 (a) is respectively multiport (b), the storage unit cross-section structure of many raceway grooves random access memory (n=2) and the embodiment that is formed static RAM by several storage unit, the situation that two N channel metal-oxide field effect transistors are arranged in storage unit 100, two raceway grooves are arranged, two ports, be specially: P-type silicon substrate 101, N-type buried layer 102,102 upper surfaces are first degree of depth below P type substrate 101 surfaces, form depletion region 103-104 between 101 and 102, shallow trench isolation region 105, the degree of depth of shallow trench isolation region 105 is deeper than following first degree of depth of semiconductor surface, namely gos deep into 102 upper surfaces below.106 and 107 are respectively source region and the drain region of the first transistor heavy doping N++ type, 108 and 109 are respectively source region and the drain region of the first transistor light dope N+ type, 110 is the drain region of transistor seconds heavy doping N++ type, the source region of transistor seconds heavy doping N++ type and the first transistor N++ share in heavily doped source region 106,111 and 112 are respectively source region and the drain region of transistor seconds light dope N+ type, 108 and 109 are respectively source region and the drain region of the first transistor light dope N+ type, the gate electrode 114 of the first transistor, the gate electrode 115 of transistor seconds, the sidewall region 116-117 of the first transistor, the sidewall region 118-119 of transistor seconds, the gate oxide 120-121 of the first transistor and transistor seconds, the first transistor, form depletion region 104 between the source region of the N-type of transistor seconds and drain region and P type substrate, STI 105, depletion region 103, depletion region 104 surrounds the floater area 113 with electricity isolation on every side.The source region 106 general ground connection that the first transistor and transistor seconds are shared.The first transistor and transistor seconds respectively have a pair of wordline bits line pair, wherein the first transistor bit line BL1 is connected to the drain region 107 of the first transistor, and link to each other with the first port, transistor seconds bit line BL2 is connected to the drain region 109 of transistor seconds, and link to each other with the second port, article one, word line WL1 is connected to the gate electrode 114 of the first transistor, and second word line WL2 is connected to the gate electrode 115 of transistor seconds.The drain region 107 of the first transistor heavy doping N++ type, floater area 113, two transistor are shared the heavily doped source region 106 of N++ and are consisted of parasitic triode 122; The drain region 110 of transistor seconds heavy doping N++ type, floater area 113, two transistor are shared the heavily doped source region 106 of N++ and are consisted of parasitic triode 123, but under existing operating voltage, 122 and 123 are in off state all the time, and read current only is the MOS electric current;
Prior art multiport, many raceway grooves floating body memory method of operating are as follows:
Write 1: the bit line to a transistor (this pipe be called write pipe) applies the first voltage, and the word line applies second voltage, and the value of the first voltage is larger than second voltage, causes hot carrier and injects, and makes the hole inject buoyancy aid, reduces this transistorized threshold voltage; Perhaps for the bit line of writing pipe applies tertiary voltage, the word line applies the 4th voltage, and the 4th voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject buoyancy aid, reduces transistorized threshold voltage.
Write 0: for the bit line of writing pipe applies the 5th voltage, the 5th voltage is negative voltage, and the word line applies the 6th voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage.
Refresh: be that the word line of the first transistor and bit line apply and write 0 or write 1 required voltage according to the original data of storage unit, reach the purpose of refresh of memory cells legacy data
Read: bit line and word line at another transistor (this pipe be called read pipe) apply respectively the 7th voltage and the 8th voltage, read the electric current of this metal-oxide-semiconductor by the port of reading pipe, 1 and 0 the state electric current that correspondence is large respectively and little electric current, thus tell different store statuss.
The core concept of multiport, many channel transistor structures is to write/refresh, read independent of each other, can write at any time/refresh the storage hole replenish to run off, and not consider whether read operation is carried out.But because the isolation of the buoyancy aid device of body silicon substrate itself is insufficient, one writing, the effect of writing " 0 " are obvious not, the initial storage window of traditional read method very little (memory window=I1-I0), only be 6～7 μ A, and general sense amplifier read threshold be 5 μ A.The refreshing frequency of so just having relatively high expectations, and be easy to misread, as shown in Figure 2.After the device scaled down, the quantity in storage space and hole is also dwindled thereupon, and I_gap can reduce thereupon, can't differentiate " 1 ", " 0 " state.
Therefore, prior art multiport, many raceway grooves floating body memory itself are isolated abundant not, have the poor less problem of reading current.
Summary of the invention
In view of this, the invention provides a kind of 90nm and with a solution of many raceway grooves of lower node embedded DRAM, can obviously improve the storage characteristicss such as action pane, data retention characteristics, accuracy, reliability of device.
In order to achieve the above object, the invention provides a kind of multiport, many channel transistor structures unit comprises: several storage unit; Each storage unit has n transistor, and (n is natural number, n 〉=2), each transistor comprises source region, drain region, grid and the tagma between source region and drain region, source region between adjacent transistor and drain region interconnect or share, during each transistor turns, form conducting channel between this transistorized source and leakage.Source transistor-tagma-drain terminal forms parasitic triode, and the parasitic transistor here can be optimized, so that it is sensitiveer to the change of body potential; Each transistor has 1 pair of wordline bits line pair, i.e. 1 word line and 1 word line; Each transistorized bit line can link to each other with an input/output end port; Different crystal pipe in the storage unit is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side; By at least one port injected carrier or extract charge carrier in the described buoyancy aid, regulate transistorized threshold voltage, reach the purpose of write signal; Read or read simultaneously by a plurality of ports the electric current of MOS transistor channel current and parasitic triode by a port, by differentiating the size of electric current, reach the purpose of read output signal, large electric current represents the first data mode 1, and little electric current represents the 2nd data mode 0; Regularly original signal in the storage unit is write back by at least one port, reached the purpose of refresh signal.
Preferably, the wordline bits line of different crystal pipe is to independently of one another, can be simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, can be simultaneously or the timesharing storage operation that reads and refresh by corresponding port.
In order to achieve the above object, the invention provides a kind of based on multiport, the novel method of operating of many raceway grooves embedded DRAM, utilize the parasitic triode effect of memory device itself to distinguish " 1 " and " 0 ", rather than utilize merely the bulk effect of MOS device, having significantly improved and read accuracy and reliability, also is that multiport, many raceway grooves floating body memory scaled down are to a kind of desirable mode of operation of 90nm and following technology node.
In order to achieve the above object, the present invention also provides a kind of multiport, many raceway grooves embedded DRAM storer, comprise: multiport, many raceway grooves embedded DRAM memory array, it comprises a plurality of multiports of arranging by the form of row and column, many channel transistor structures unit; Line decoder; Column decoder; Sense amplifier; Word line driver module; The bit-line drive module; Logic control module is for controlling described word line driver module and the described bit-line drive module sequential at read operation, write operation, data maintenance operation and refresh operation.
Description of drawings
Accompanying drawing 2 is prior art multiport, many raceway grooves random access memory read-write/refresh operation graph of a relation;
Accompanying drawing 3 is according to one embodiment of the invention multiport, many raceway grooves floating body memory method of operating;
Accompanying drawing 4 (a) and (b) be the principle comparison diagram of traditional operation mode and mode of operation of the present invention;
Accompanying drawing 5 is multiport of the present invention, many raceway grooves random access memory read-write/refresh operation graph of a relation;
Accompanying drawing 6 is according to embodiment of the invention multiport, many raceway grooves random access memory operating impulse figure;
Accompanying drawing 7 is according to embodiment of the invention multiport, many raceway grooves random access memory peripheral circuit diagram.
Embodiment
With reference to the accompanying drawings 3, for according to one embodiment of the invention multiport, many raceway grooves floating body memory method of operating.
Device in the accompanying drawing 3 is the embedded DRAM unit of a kind of multiport, many raceway grooves, comprises several storage unit; Each storage unit has n transistor, n is natural number, n 〉=2, each transistor comprises source region, drain region, grid and the tagma between source region and drain region, source region between adjacent transistor and drain region interconnect or share, during each transistor turns, form conducting channel between this transistorized source and leakage; Source transistor-tagma-drain terminal forms parasitic triode, here can be by rationally controlling process parameter optimizing parasitic triode characteristic, thereby improve memory performance (such as so that parasitic triode is sensitiveer to the change of body potential, and easier conducting etc.).Each transistor has 1 pair of wordline bits line pair, i.e. 1 word line and 1 word line; Each transistorized bit line can link to each other with an input/output end port;
Different crystal pipe in the storage unit is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side; By at least one port injected carrier or extract charge carrier in the described buoyancy aid, regulate transistorized threshold voltage, reach the purpose of write signal; Read or read simultaneously the electric current of source transistor between leaking by a plurality of ports by a port, by differentiating the size of electric current, reach the purpose of read output signal, large electric current represents the first data mode 1, and little electric current represents the 2nd data mode 0; Regularly original signal in the storage unit is write back by at least one port, reached the purpose of refresh signal; The wordline bits line of different crystal pipe is to independently of one another, can be simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, can be simultaneously or the timesharing storage operation that reads and refresh by corresponding port.
In one embodiment, n can equal 2, and each unit comprises two MOS (metal-oxide-semiconductor) memory: the first transistor and transistor seconds; The source of the leakage of the first transistor or source and transistor seconds or leak links to each other or is shared, and is connected to the ground; The word line of the first transistor and transistor seconds connects respectively to the grid of the first transistor and transistor seconds; The bit line of the first transistor and transistor seconds connects respectively to the source of the first transistor or leakage or the source of leakage and transistor seconds, and is connected input/output end port with transistor seconds with the first transistor respectively and is connected.Two transistorized source regions, tagma and drain regions all form parasitic audion.
In one embodiment, n can equal 3, comprises 3 metal-oxide-semiconductor field effect t transistors in the described unit: the first transistor, transistor seconds and the 3rd transistor; The first transistor, transistor seconds and the 3rd transistorized grid are connected with the 3rd transistorized word line with the word line of the first transistor, the word line of transistor seconds respectively; The leakage of the first transistor or source and the 3rd transistorized source or leakage is connected or share, and be connected with ground; The source of transistor seconds or leak with the 3rd transistorized leakage or the source links to each other or shared; The leakage of the source of the first transistor or leakage, transistor seconds or source are connected with the 3rd transistorized bit line with the bit line of the first transistor, the bit line of transistor seconds respectively with the 3rd transistorized leakage or source, and are connected each with the first transistor, transistor seconds, the 3rd transistorized input/output end port respectively.Transistorized source region, tagma and drain region form parasitic audion.
When reading, read to manage word line voltage probably at 0.2-0.8V, read to manage bit-line voltage about about 2.0V.After multiport, many channel transistor structures one writing keep, in the body because storage hole, bulk potential is increased to V
B1, so that read the emitter junction forward bias (V of the source of pipe-body drain parasitic triode
BE＞0), and the voltage of drain terminal (collector) is approximately 2V, so that electricity knot reverse bias extremely, reads like this source of pipe-body drain parasitic triode and opens, and drain terminal (collector) electric current is larger, shown in Fig. 3 (a); After multiport, many channel transistor structures were write " 0 " maintenance, the storage hole was discharged bulk potential V in the body
B0Be reduced near 0V, so that read the emitter inverse biasing (V of the source of pipe-body drain parasitic triode
BE＜=0), and extremely electricity is tied still reverse bias, reads the source of pipe-body drain parasitic triode cut-off, and drain terminal (collector) electric current is very little, shown in Fig. 3 (b).
When described transistor was two N channel metal-oxide field effect transistors, concrete operation method was:
Write 1: the bit line to the first transistor applies the 1st voltage, and the word line applies the 2nd voltage, and the value of the 1st voltage is larger than the 2nd voltage, causes hot carrier and injects, and makes the hole inject buoyancy aid, reduces transistorized threshold voltage; Perhaps for the bit line of the first transistor applies the 3rd voltage, the word line applies the 4th voltage, and the 4th voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject buoyancy aid, reduces transistorized threshold voltage.
Write 0: for the bit line of the first transistor applies the 5th voltage, the 5th voltage is negative voltage, and the word line applies the 6th voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage.
Refresh: be that the word line of the first transistor and bit line apply and write 0 or write 1 required voltage according to the original data of storage unit, reach the purpose of refresh of memory cells legacy data.
Read: for bit line and the word line of transistor seconds applies respectively the 7th voltage and the 8th voltage, for state 1, source-the body of transistor seconds-omit living triode to open, the parasitic triode electric current that the electric current that port by transistor seconds reads equals transistor seconds adds the channel current of transistor seconds, and the parasitic triode of transistor seconds is obviously greater than channel current.For state 0, because bulk potential is lower, the emitter junction of the living triode of the source-body of transistor seconds-omit can not conducting, this parasitic transistor cuts out, the electric current that port by transistor seconds reads only is the channel current of transistor seconds, and since the threshold voltage of state 0 greater than the threshold voltage of state 1, this moment transistor seconds channel current less than the channel current of state 1, therefore the electric current difference of state 1 and state 0 is very large, and store status is easy to differentiate.
The wordline bits line of choosing transistor seconds carries out read operation and the wordline bits line of choosing the first transistor to storage unit, and that storage unit is carried out refresh operation is separate, when reading, can refresh, also can when not reading, refresh, the frequency that refreshes can be at a high speed, middling speed, at a slow speed.
When described transistor was three N channel metal-oxide field effect transistors, concrete operation method was:
Write 1: be that the 3rd transistorized bit line applies the 9th voltage, the word line applies the 10th voltage, and the value of the 9th voltage is greater than the 10th voltage, utilize impact ionization to produce electronics---hole pair, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be the 3rd transistorized bit line ground connection, the word line applies the 11st voltage, and the 11st voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject floater area, reduces transistorized threshold voltage.
Write 0: be that the 3rd transistorized bit line applies the 12nd voltage, the 12nd voltage is negative sense, and the word line applies forward the 13rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage.
Refresh: according to the original data of storage unit, regularly be that the 3rd transistorized word line and bit line apply and write 0 or write 1 required voltage, reach the purpose of refresh of memory cells legacy data.
Read: for bit line and the word line of the first transistor applies respectively the 14th and the 15th voltage, for state 1, source-the body of transistor seconds-leakage NPN parasitic triode is opened, the electric current that port by transistor seconds reads is the channel current that the parasitic triode electric current of transistor seconds adds transistor seconds, and the parasitic triode of transistor seconds is obviously greater than channel current.For state 0, because bulk potential is lower, source-the body of transistor seconds-omit living triode to close, the electric current that port by transistor seconds reads only is the channel current of transistor seconds, and since the threshold voltage of state 0 greater than the threshold voltage of state 1, this moment transistor seconds channel current less than the channel current of state 1, so the electric current difference of state 1 and state 0 is very large, store status is easy to differentiate.Also can apply for the bit line of transistor seconds forward the 16th voltage that is higher than its source voltage terminal, for the word line of transistor seconds applies forward the 17th voltage, read channel current and the parasitic triode electric current of transistor seconds by the port of transistor seconds, 1 or 0 state is the large and little electric current of correspondence respectively, thereby tells the data in the storage unit; Can also be simultaneously for applying, the bit line of the first transistor and transistor seconds and word line read required voltage, read simultaneously channel current and the parasitic triode electric current of the first transistor and transistor seconds by first crystal pipe port and transistor seconds port, obtain the storage data from first crystal pipe port and transistor seconds port simultaneously.
Choosing the 3rd transistorized wordline bits line that storage unit is carried out refresh operation and the wordline bits line of choosing the first transistor and/or transistor seconds, that storage unit is carried out read operation is separate, and the frequency that refreshes can be at a high speed, middling speed, at a slow speed.
Fig. 4 is the principle contrast of traditional operation mode and neoteric mode of operation, wherein Fig. 4 (a) is traditional read method, because bulk effect, threshold voltage corresponding to bulk potential that state " 1 " is different with state " 0 " read pipe and is offset to linear zone when reading, the MOS electric current of reading can be distinguished to some extent, but by Fig. 4 (a) as can be known, read current only is directly proportional with bulk potential VB square root, and is insensitive to the variation of VB, thereby the read current of conventional MOS reading manner is poor less.Its formula is:
And method of operating of the present invention utilizes different bulk potential to regulate the on off state of parasitic triode, and read current and bulk potential VB are that index concerns, and is such as Fig. 4 (b), poor also more remarkable by the read current that the difference of VB causes.Certainly, the read current of new invention mode of operation may comprise MOS electric current and triode electric current simultaneously, and is poor with further increase read current.Its formula is:
The invention provides the superior multiport of a kind of effect, many raceway grooves floating body memory read method, through test, use the reading current window of the method 1 and 0 two condition can reach 20～150 μ A, is 4～30 times of traditional read method, as shown in Figure 5.Along with reducing of process, the base length WB of parasitic triode also can reduce (device grid length is dwindled), the current gain of triode increases, and will reduce according to the difference between current of related documents report traditional operation mode, therefore along with the scaled down of device, the advantage of novel read method will be more remarkable.
The below provides multiport of the present invention, many raceway grooves floating body memory operating voltage table, and is as shown in the table:
Table one:
| Voltage | WL1 | BL1 | WL2 | BL2 | Source | N_buried |
| Write 1 | 1.2V | 2.0 |
0 | 0 | 0 | 0.5 |
| Write 0 | -2.0V | -2.0 |
0 | 0 | 0 | 0.5 |
| Read | 0 | 0 | 0.2～0.8V | 2.0 |
0 | 0.5 |
| Keep | 0 | 0 | 0 | 0 | 0 | 0.5 |
Wherein operating impulse as can be seen from the figure, is write pipe and is refreshed once at set intervals as shown in Figure 6, can read and read to manage any time, and 10us, 100us, 1ms, 10ms read once respectively here.
When reading, if read the tube grid voltage bias at Vg=0.6V, have simultaneously MOS electric current and multi-electrode tube electric current, but take the triode electric current as main, MOS electric current difference also has a contribution to total read current is poor.
Table two:
With reference to the accompanying drawings 7, its peripheral circuit diagram, it comprises line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module etc.The function of Logic control module is that control word line driver module and bit-line drive module keep the sequential in operation and the refresh operation in read operation, write operation, data.Wherein selected line chooses the bit-line voltage of row to change and can differentiate by sense amplifier, and compares with reference source, obtains sense data.Row address is counted the line of input code translator, is used for choosing WWL and the RWL of array, column address input column decoder.
Although illustrate and described the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that at it and can make a lot of variations and modification without departing from the invention aspect wider.The present invention includes the process optimization, layout strategy and the testing algorithm that read principle based on triode: such as, on device architecture, change 111 among Fig. 1 and 112 light dope N districts into heavy doping N++ district, to shorten triode base length, increase the triode current gain; Suitably adjust the voltage of 102N-type buried layer when reading, to obtain larger difference between current etc.The present invention is applicable to multiport, many raceway grooves floating body memory device of multiple device architecture, such as SOI, double grid, three grid and gate-all-around structure, and comprises based on these device architecture characteristics, suitable improvement and optimization on method of operating.
Claims (8)
1. a multiport, many channel transistor structures unit comprise:
Several storage unit;
Each storage unit has n transistor, wherein n is natural number, n 〉=2, each transistor comprises source region, drain region, grid and the tagma between source region and drain region, source region between adjacent transistor and drain region interconnect or share, and during each transistor turns, form conducting channel between this transistorized source and leakage, transistorized source region, tagma and drain region form bipolar transistor structure, i.e. parasitic triode;
Each transistor has 1 pair of wordline bits line pair, i.e. 1 word line and 1 word line; Each transistorized bit line can link to each other with an input/output end port; Different crystal pipe in the storage unit is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side; By at least one port injected carrier or extract charge carrier in the described buoyancy aid, regulate transistorized threshold voltage, reach the purpose of write signal; Read or read simultaneously transistor conducting channel electric current and parasitic triode electric current by a plurality of ports by a port, by differentiating the size of electric current, reach the purpose of read output signal, large electric current represents the first data mode 1, and little electric current represents the 2nd data mode 0; Regularly original signal in the storage unit is write back by at least one port, reached the purpose of refresh signal;
The wordline bits line of different crystal pipe is to independently of one another, can be simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, can be simultaneously or the timesharing storage operation that reads and refresh by corresponding port.
2. according to claim 1 multiport, many channel transistor structures unit is characterized in that described float structure is the float structure that is formed in the monocrystalline substrate, wherein:
The float structure that is formed in the monocrystalline substrate is as follows: form the buried layer with second conduction type below the semiconductor surface with first conduction type, the buried layer upper surface is positioned at following first degree of depth of semiconductor surface, the zone that has the first conduction type above buried layer forms storage unit, isolated by shallow trench isolation region between the storage unit, the degree of depth of shallow trench isolation region is deeper than following first degree of depth of semiconductor surface; Comprise n transistor in each storage unit, wherein n is natural number, n 〉=2, each transistor comprises source region, drain region and the tagma between source region and drain region with second conduction type, transistorized source region, tagma and drain region form parasitic audion, between buried layer and tagma, between source region and tagma, form depletion region between drain region and tagma, depletion region and shallow trench isolation region surround the float structure that forms with electricity isolation all around.
3. according to claim 1 multiport, many channel transistor structures unit is characterized in that, n transistor in the described same storage unit can all be N channel metal-oxide field effect transistor, and wherein n is natural number, n 〉=2.
4. according to claim 1 multiport, many channel transistor structures unit is characterized in that, n can equal 2, and each unit comprises two MOS (metal-oxide-semiconductor) memory: the first transistor and transistor seconds; The source of the leakage of the first transistor or source and transistor seconds or leak links to each other or is shared, and is connected to the ground; The word line of the first transistor and transistor seconds connects respectively to the grid of the first transistor and transistor seconds; The bit line of the first transistor and transistor seconds connects respectively to the source of the first transistor or leakage or the source of leakage and transistor seconds, and be connected input/output end port with transistor seconds with the first transistor respectively and be connected, two transistorized source regions, tagma and drain regions all form parasitic audion.
5. according to claim 1 multiport, many channel transistor structures unit is characterized in that, n can equal 3, comprises 3 metal-oxide-semiconductor field effect t transistors in the described unit: the first transistor, transistor seconds and the 3rd transistor; The first transistor, transistor seconds and the 3rd transistorized grid are connected with the 3rd transistorized word line with the word line of the first transistor, the word line of transistor seconds respectively; The leakage of the first transistor or source and the 3rd transistorized source or leakage is connected or share, and be connected with ground; The source of transistor seconds or leak with the 3rd transistorized leakage or the source links to each other or shared; The leakage of the source of the first transistor or leakage, transistor seconds or source are connected with the 3rd transistorized bit line with the bit line of the first transistor, the bit line of transistor seconds respectively with the 3rd transistorized leakage or source, and be connected with the first transistor, transistor seconds, the 3rd transistorized input/output end port respectively, transistorized source region, tagma and drain region form parasitic audion.
6. the methods of storage operating of a multiport, many channel transistor structures unit, when described transistor was two N channel metal-oxide field effect transistors, described method comprised:
Write 1: the bit line to the first transistor applies the 1st voltage, and the word line applies the 2nd voltage, and the value of the 1st voltage is larger than the 2nd voltage, causes hot carrier and injects, and makes the hole inject buoyancy aid, reduces transistorized threshold voltage; Perhaps for the bit line of the first transistor applies the 3rd voltage, the word line applies the 4th voltage, and the 4th voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject buoyancy aid, reduces transistorized threshold voltage;
Write 0: for the bit line of the first transistor applies the 5th voltage, the 5th voltage is negative voltage, and the word line applies the 6th voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;
Refresh: be that the word line of the first transistor and bit line apply and write 0 or write 1 required voltage according to the original data of storage unit, reach the purpose of refresh of memory cells legacy data;
Read: for bit line and the word line of transistor seconds applies respectively the 7th voltage and the 8th voltage, for state 1, because body potential raises, source-the body of transistor seconds-leakage NPN parasitic triode is opened, the electric current that port by transistor seconds reads is the channel current that the parasitic triode electric current of transistor seconds adds transistor seconds, and the parasitic triode of transistor seconds is obviously greater than channel current; For state 0, body potential is lower, the emitter junction of the living triode of the source-body of transistor seconds-omit can conducting, this parasitic transistor cuts out, the electric current that port by transistor seconds reads only is the channel current of transistor seconds, and since the threshold voltage of state 0 greater than the threshold voltage of state 1, this moment transistor seconds channel current less than the channel current of state 1, therefore the electric current difference of state 1 and state 0 is very large, and store status is easy to differentiate;
The wordline bits line of choosing transistor seconds carries out read operation and the wordline bits line of choosing the first transistor to storage unit, and that storage unit is carried out refresh operation is separate, when reading, can refresh, also can when not reading, refresh, the frequency that refreshes can be at a high speed, middling speed, at a slow speed.
7. the methods of storage operating of a multiport, many channel transistor structures unit, when described different components was 3 N channel metal-oxide field effect transistor transistors, its methods of storage operating comprised:
Write 1: be that the 3rd transistorized bit line applies the 9th voltage, the word line applies the 10th voltage, and the value of the 9th voltage is greater than the 10th voltage, utilize impact ionization to produce electronics---hole pair, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be the 3rd transistorized bit line ground connection, the word line applies the 11st voltage, and the 11st voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject floater area, reduces transistorized threshold voltage;
Write 0: be that the 3rd transistorized bit line applies the 12nd voltage, the 12nd voltage is negative sense, and the word line applies forward the 13rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;
Refresh: according to the original data of storage unit, regularly be that the 3rd transistorized word line and bit line apply and write 0 or write 1 required voltage, reach the purpose of refresh of memory cells legacy data;
Read: for bit line and the word line of the first transistor applies respectively the 14th and the 15th voltage, for state 1, source-the body of transistor seconds-leakage NPN parasitic triode is opened, the electric current that port by transistor seconds reads is the channel current that the parasitic triode electric current of transistor seconds adds transistor seconds, the parasitic triode of transistor seconds is obviously greater than channel current, for state 0, because bulk potential is lower, source-the body of transistor seconds-omit living triode to close, the electric current that port by transistor seconds reads only is the channel current of transistor seconds, and since the threshold voltage of state 0 greater than the threshold voltage of state 1, the channel current of transistor seconds is less than the channel current of state 1 at this moment, therefore the electric current difference of state 1 and state 0 is very large, and store status is easy to differentiate; Also can apply for the bit line of transistor seconds forward the 16th voltage that is higher than its source voltage terminal, for the word line of transistor seconds applies forward the 17th voltage, read channel current and the parasitic triode electric current of transistor seconds by the port of transistor seconds, 1 or 0 state is the large and little electric current of correspondence respectively, thereby tells the data in the storage unit; Can also be simultaneously for applying, the bit line of the first transistor and transistor seconds and word line read required voltage, read simultaneously channel current and the parasitic triode electric current of the first transistor and transistor seconds by first crystal pipe port and transistor seconds port, obtain the storage data from first crystal pipe port and transistor seconds port simultaneously;
Choosing the 3rd transistorized wordline bits line that storage unit is carried out refresh operation and the wordline bits line of choosing the first transistor and/or transistor seconds, that storage unit is carried out read operation is separate, and the frequency that refreshes can be at a high speed, middling speed, at a slow speed.
8. a multiport, many channel transistor structures is characterized in that, comprising:
Multiport, many channel transistor structures array, it comprises the arbitrary described multiport of a plurality of claims 1 to 4, the many channel transistor structures unit of arranging by the form of row and column;
Line decoder;
Column decoder;
Sense amplifier;
Word line driver module;
The bit-line drive module;
Logic control module is for controlling described word line driver module and the described bit-line drive module sequential at read operation, write operation, data maintenance operation and refresh operation.
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| US20050174873A1 (en) * | 2003-05-13 | 2005-08-11 | Richard Ferrant | Semiconductor memory device and method of operating same |
| CN101221953A (en) * | 2007-11-22 | 2008-07-16 | 林殷茵 | Multiport and multi-channel embedded dynamic ram and operating method thereof |
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| US20050174873A1 (en) * | 2003-05-13 | 2005-08-11 | Richard Ferrant | Semiconductor memory device and method of operating same |
| CN101221953A (en) * | 2007-11-22 | 2008-07-16 | 林殷茵 | Multiport and multi-channel embedded dynamic ram and operating method thereof |
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