CN102867539B - gain eDRAM memory cell structure - Google Patents
gain eDRAM memory cell structure Download PDFInfo
- Publication number
- CN102867539B CN102867539B CN201110188441.5A CN201110188441A CN102867539B CN 102867539 B CN102867539 B CN 102867539B CN 201110188441 A CN201110188441 A CN 201110188441A CN 102867539 B CN102867539 B CN 102867539B
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- metal
- oxide
- gain
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The invention belongs to memory technology field, propose one and improve gain-type eDRAM device architecture.A kind of gain eDRAM unit of the present invention, comprise read MOS transistor, write MOS transistor, write word line, write bit line, readout word line, sense bit line, the grid reading metal-oxide-semiconductor and the drain region writing metal-oxide-semiconductor are connected by metal wire and jointly form storage node, write metal-oxide-semiconductor, read metal-oxide-semiconductor and respectively there is gate dielectric, it is characterized in that, described write metal-oxide-semiconductor, read metal-oxide-semiconductor and have trench channel, write metal-oxide-semiconductor, read the gate dielectric of metal-oxide-semiconductor and be arranged in silicon substrate groove, grid is the convex cylindrical shape to lower convexity.The present invention obviously can improve the data retention characteristics of device.
Description
Technical field
The invention belongs to memory technology field, propose one and improve gain-type eDRAM device architecture.
Background technology
As shown in Figure 1, be the 2T Gain Cell eDRAM unit of intel.This Gain Cell eDRAM 100 comprise write MOS transistor 101, read MOS transistor 102, write word line (Write Word Line, WWL) 105, readout word line (Read Word Line, RWL) 106, write bit line (Write Bit Line, WBL) 107, sense bit line (Read Bit Line, RBL) 108 and equivalent parasitic capacitances 104 (equivalent parasitic capacitances does not exist as an individual devices, just schematically illustrates separately in figure).Wherein, the drain region writing MOS transistor 101 is connected to the grid reading MOS transistor 102, and MN point 103 is memory node, equivalent parasitic capacitances 104 one end is connected with 103, other end ground connection, therefore, the high low energy of the current potential of MN point controls conducting and the shutoff of reading MOS transistor 102; Such as, during electric capacity 104 stored charge, representative stores " 1 ", and MN point 103 is noble potential, can control to read MOS transistor 102 and turn off.Read a termination RBL of MOS transistor 102, another termination RWL; Write a termination WBL of MOS transistor 101, another termination reads the grid of MOS transistor 102.Normally, equivalent parasitic capacitances 104 namely for writing the active area stray capacitance stray capacitance of drain region (also) of MOS transistor 101 or reading the gate capacitance of MOS transistor 102, also or both combinations.This storage unit is based on standard logic process, and its leakage current path has three:
1, by the sub-threshold leakage 110 of gate tube 101;
2, the PN junction electric leakage 111 at storage node 104 place;
3, by the electric leakage 112 of the grid oxygen of 101 and 102.
According to document analysis and device simulation, wherein sub-threshold leakage 110 and PN junction electric leakage 111 are chief components of leakage current.This unit Problems existing leaks electricity relatively seriously, and data hold time is too short, adopt standard logic process to only have the data hold time of about 10us, thus refreshing frequency is very high under 65nm, and power consumption increases.
As shown in Figure 2, the domain of 2T Gain Cell eDRAM unit.The wherein active area of 201 representative write pipes 101, the grid of 202 representative write pipes, the active area of pipes 102 is read in 205 representatives, and the grid of pipes is read in 206 representatives, to be connected jointly to form storage node 204 by the grid 206 reading pipe and the drain region 203 that writes pipe by metal wire 207.The size of storage node 204 place electric capacity and leakage current determine the length of the time data memory of this storage unit jointly, thus determine the speed of refreshing frequency and the size of power consumption.And such memory capacitance formed with metal-oxide-semiconductor active area electric capacity and gate capacitance is quite little, so its data hold time is shorter, refreshing frequency requires higher.
The maximum problem of gain-type eDRAM device is data hold time too small (being only μ s magnitude), and especially after device scaled down, problem is more outstanding, and reason is as follows:
In order to reduce sub-threshold leakage 110, substrate doping need be increased, the electric field intensity that improve near memory node 104 but larger substrate adulterates, PN junction electric leakage 111 increases thereupon, become the chief component of leakage current, and the high electric field near 104 also may aggravate tunneling effect, cause other tunnelling current, therefore total leakage current does not reduce, and increases to some extent on the contrary;
The present invention is a solution of 65nm and random access memory (particularly in-line memory) of volatilizing with lower node, obviously can improve the data retention characteristics of device.
Summary of the invention
In view of this, the invention provides a kind of 65nm and with a solution of lower node volatilization random access memory (particularly in-line memory), obviously can improve the data retention characteristics of device.
In order to achieve the above object, the invention provides a kind of gain eDRAM unit, comprise read MOS transistor, write MOS transistor, write word line, write bit line, readout word line, sense bit line, the grid reading metal-oxide-semiconductor and the drain region writing metal-oxide-semiconductor are connected by metal wire and jointly form storage node, write metal-oxide-semiconductor, read metal-oxide-semiconductor and respectively there is gate dielectric, it is characterized in that, write metal-oxide-semiconductor, read metal-oxide-semiconductor there is trench channel, write metal-oxide-semiconductor, read the gate dielectric of metal-oxide-semiconductor and be arranged in silicon substrate groove, grid is convex cylindrical shape.
Preferably, read MOS transistor to comprise with the structure writing MOS transistor: N trap impurity doping region, is defined in semiconductor base; Active region, is defined by trench isolation region domain separation; Gate trench, is located in N trap impurity doping region, and in convex cylindrical shape, channel bottom has lower convex curved surface profile; Grid, is located in gate trench; And normal source-drain structure.
In order to achieve the above object, the present invention also provides a kind of gain eDRAM storer, it is characterized in that, comprising: gain cell eDRAM array, and it comprises the arbitrary described gain eDRAM unit of the multiple claims 1 to 3 arranged by the form of row and column; Line decoder; Column decoder; Sense amplifier; Word line driver module; Bit-line drive module; Logic control module, for controlling described word line driver module and the sequential of described bit-line drive module in read operation, write operation, data retention operation and refresh operation.
Accompanying drawing explanation
Accompanying drawing 1 is the 2T Gain Cell eDRAM unit of prior art Intel;
Accompanying drawing 2 is the domain of the 2T Gain Cell eDRAM unit of prior art Intel;
Accompanying drawing 3 (a) is the domain according to one embodiment of the invention storage unit;
Accompanying drawing 3 (b) is according to the sectional view of one embodiment of the invention storage unit along AA ' and BB ' both direction;
Accompanying drawing 4 (a) is the domain of storage unit according to a further embodiment of the invention;
Accompanying drawing 4 (b) be according to a further embodiment of the invention storage unit along the sectional view of AA ' and BB ' both direction;
Accompanying drawing 5 is eDRAM memory construction schematic diagram of the present invention;
Accompanying drawing 6 is another embodiment trench channel structure of eDRAM memory construction of the present invention.
Embodiment
With reference to accompanying drawing 3, for according to the domain of one embodiment of the invention storage unit and sectional view thereof.The eDRAM unit 300 of this embodiment is similarly and writes MOS transistor comprising shown in Fig. 1, read MOS transistor, the structure of write word line, write bit line, readout word line and readout word line, therefore, the electrical block diagram of eDRAM unit 300 is identical with the electrical block diagram of the eDRAM unit shown in Fig. 1, write MOS transistor, read MOS transistor, write word line, write bit line, annexation between readout word line and readout word line and the function that realizes also identical, do not remake at this and repeat.
Particularly, the source region of 301 representative write metal-oxide-semiconductors 101, the grid of 302 representative write metal-oxide-semiconductors, the active area of metal-oxide-semiconductor 102 is read in 305 representatives, the grid of metal-oxide-semiconductors is read in 306 representatives, to be connected jointly to form storage node 304 by the grid 306 reading metal-oxide-semiconductor and the drain region 303 that writes metal-oxide-semiconductor by metal wire 307.308,309 the gate dielectric writing metal-oxide-semiconductor 101, read metal-oxide-semiconductor 102 is respectively.Write metal-oxide-semiconductor, reading metal-oxide-semiconductor are PMOS, as Fig. 3 (b), include: N trap impurity doping region 313, is defined in semiconductor base; Active region 305, is isolated by trench isolation regions 312 and defines; Gate trench 310,311, be located in N trap impurity doping region 313, in convex cylindrical shape, channel bottom has lower convex curved surface profile, the height (degree of depth of vertical side wall portion) of cylinder is h1, h2, and depth representing convex under cylindrical base curved surface is r1, r2, generally speaking, h1 >=r1, h2 >=r2.Grid 302,306, is located in gate trench; Grid oxic horizon 308,309, is located on gate trench, between N-type impurity doped region 313 and grid, is high dielectric constant material (as hafnia); Normal source and drain doped structure.
Here a kind of effective ways improving gain eDRAM 2T gaincell device provided, compared with flat tube, the trench channel of write pipe increases the length of effective channel (effect channel length) of transistor, make device while scaled down, keep certain grid long, short-channel effect is effectively suppressed, subthreshold current 110 reduces, therefore the doping content of substrate need not be too high, near memory node, electric field intensity effectively reduces, and PN junction electric leakage 111 also reduces thereupon.Leakage current total like this can effectively reduce, the degree of minimizing and the geometric configuration of raceway groove, the degree of depth (h1, r1, h2, r2) relevant, if do not consider the difficulty of technique, h1, r1, h2, r2 are larger, leakage current is less, in the scope that technique allows, leakage current can reduce at least one the order of magnitude, and therefore data hold time increases.Read tube grid electric capacity and be mainly used to stored charge (grid capacitance is approximately 50% ~ 70% of total memory capacitance under normal circumstances), two-dimentional electric capacity is expanded to three-dimensional capacitor by raceway groove/gate trench, capacity area enlarges markedly, total memory capacitance increases, also can improve the data retention characteristics of memory device, the degree of increase is also relevant with the physical dimension of trench channel.In addition, the sub-threshold leakage reading pipe also will reduce, and this is conducive to the signal to noise ratio (S/N ratio) improving read output signal, strengthens antijamming capability.Use the present invention, the data hold time of gain eDRAM unit can be made to obtain significantly improving of at least one order of magnitude.Be specially adapted to 65nm and following technology node low-power consumption, high-performance embedded random storage application.
Accompanying drawing 4 (a) is the domain of storage unit according to a further embodiment of the invention; Accompanying drawing 4 (b) be according to a further embodiment of the invention storage unit along the sectional view of AA ' and BB ' both direction.For 32nm process node, memory device is as Figure 40 0.32nm logical device adopts High k Metal Gate technology, hafnium base gate medium.In order to manufacture trench channel device, and optimize the write pipe groove shape different with reading pipe respectively, the mask plate 410 and 411 that on domain, increase by two pieces is special.Wherein: 402 and 406 is metal gate, 408,409 is the gate medium of high-k, and other are introduced with accompanying drawing 3.
Accompanying drawing 5 is eDRAM memory construction schematic diagram of the present invention.This gain cell eDRAM storer comprises gain unit array, and gain unit array is formed by the form arrangement of gain cell eDRAM unit by row and column, and wherein, gain cell eDRAM unit is the gain cell eDRAM unit of above Fig. 3 or Fig. 4 embodiment.Wordline and bit line cross arrangement, gain unit is placed in cross arrangement point.This gain cell eDRAM storer also comprises line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module.The function of Logic control module controls word line driver module and the sequential of bit-line drive module in read operation, write operation, data retention operation and refresh operation.Wherein selected line chooses the bit-line voltage change of row to differentiate by sense amplifier, and compares with Vref (reference voltage), obtains sense data.Row address number line of input code translator, for choosing WWL and RWL in array, column address input column decoder.
Although illustrate and describe the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that and can make a lot of change and amendment without departing from the invention in it is wider.The present invention includes SOI substrate, and the structure of all advanced persons such as FinFET, ring grid; Much technique and domain implementation may be had; Channel Trench shape or the structure of multiple improvement may be had, be used for increasing store electricity further and perhaps reduce leakage current, as shown in Figure 6.
Claims (7)
1. a gain eDRAM memory cell structure, comprise read metal-oxide-semiconductor, write metal-oxide-semiconductor, write word line, write bit line, readout word line, sense bit line, the grid reading metal-oxide-semiconductor and the drain region writing metal-oxide-semiconductor are connected by metal wire and jointly form storage node, write metal-oxide-semiconductor, read metal-oxide-semiconductor and respectively there is gate dielectric, it is characterized in that, described metal-oxide-semiconductor of reading comprises with the structure writing metal-oxide-semiconductor: N trap impurity doping region, is defined in semiconductor base; Active region, is defined by trench isolation region domain separation; Gate trench, is located in N trap impurity doping region, and in convex cylindrical shape, channel bottom has lower convex curved surface profile, and grid is located in gate trench; And normal source and drain doped structure; The trench channel writing metal-oxide-semiconductor increases the length of effective channel of transistor, reads metal-oxide-semiconductor trench channel and increases parasitic gate electric capacity, is three-dimensional structure by grid electricity by two-dimensional expansion.
2. gain eDRAM memory cell structure as claimed in claim 1, it is characterized in that, the trench channel writing metal-oxide-semiconductor increases the length of effective channel of transistor.
3. gain eDRAM memory cell structure as claimed in claim 1, is characterized in that, read metal-oxide-semiconductor trench channel and increase parasitic gate electric capacity, is three-dimensional structure by grid capacitance by two-dimensional expansion.
4. gain eDRAM memory cell structure as claimed in claim 1, it is characterized in that, read metal-oxide-semiconductor and write metal-oxide-semiconductor to have normal source-drain structure, grid is arranged among the convex groove of N trap impurity doping region downwards, groove is cylindric, and channel bottom has lower convex curved surface profile.
5. gain eDRAM memory cell structure as claimed in claim 1, it is characterized in that, gate dielectric is high-dielectric-coefficient grid medium.
6. gain eDRAM memory cell structure as claimed in claim 1, it is characterized in that, gate dielectric is hafnium base high-dielectric-coefficient grid medium.
7. a gain eDRAM storer, comprising:
Line decoder;
Column decoder;
Sense amplifier;
Word line driver module;
Bit-line drive module;
Logic control module, for controlling described word line driver module and the sequential of described bit-line drive module in read operation, write operation, data retention operation and refresh operation;
It is characterized in that, also comprise:
Gain cell eDRAM array, it comprises the arbitrary described gain eDRAM memory cell structure of the multiple claims 1 to 6 arranged by the form of row and column.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110188441.5A CN102867539B (en) | 2011-07-05 | 2011-07-05 | gain eDRAM memory cell structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110188441.5A CN102867539B (en) | 2011-07-05 | 2011-07-05 | gain eDRAM memory cell structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102867539A CN102867539A (en) | 2013-01-09 |
| CN102867539B true CN102867539B (en) | 2015-08-26 |
Family
ID=47446352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110188441.5A Expired - Fee Related CN102867539B (en) | 2011-07-05 | 2011-07-05 | gain eDRAM memory cell structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102867539B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764132A (en) * | 2008-12-24 | 2010-06-30 | 上海华虹Nec电子有限公司 | 1.5 T SONOS flash memory unit |
| CN101853697A (en) * | 2010-07-05 | 2010-10-06 | 复旦大学 | Gain cell embedded dynamic random access memory (eDRAM) unit, memory and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2910999B1 (en) * | 2006-12-28 | 2009-04-03 | Commissariat Energie Atomique | MEMORY CELL WITH DOUBLE-GRID TRANSISTORS, INDEPENDENT AND ASYMMETRIC GRIDS |
-
2011
- 2011-07-05 CN CN201110188441.5A patent/CN102867539B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764132A (en) * | 2008-12-24 | 2010-06-30 | 上海华虹Nec电子有限公司 | 1.5 T SONOS flash memory unit |
| CN101853697A (en) * | 2010-07-05 | 2010-10-06 | 复旦大学 | Gain cell embedded dynamic random access memory (eDRAM) unit, memory and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102867539A (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102246294B (en) | There is the low power memory device of junction field effect transistor apparatus structure | |
| US9425190B2 (en) | Techniques for providing a direct injection semiconductor memory device | |
| US8964461B2 (en) | Techniques for providing a direct injection semiconductor memory device | |
| US7969808B2 (en) | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same | |
| TW200537488A (en) | 3 TID memory cells using gated diodes and methods of use thereof | |
| US20120307568A1 (en) | Techniques for providing a semiconductor memory device | |
| WO2022137607A1 (en) | Method for manufacturing memory device using semiconductor element | |
| JP2000340679A (en) | Body contact type dynamic memory | |
| JP2005175494A (en) | Gate controlled diode memory cells | |
| CN101853697B (en) | Gain cell embedded dynamic random access memory (eDRAM) unit, memory and preparation method thereof | |
| KR101461629B1 (en) | Memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and method of operating the same | |
| CN103972238A (en) | Memory unit structure | |
| WO2022162870A1 (en) | Memory device using semiconductor elements | |
| TWI671886B (en) | Memory cell comprising first and second transistors and methods of operating | |
| CN102867539B (en) | gain eDRAM memory cell structure | |
| CN111640461B (en) | Operation method of DRAM | |
| US20130315000A1 (en) | Techniques For Providing A Direct Injection Semiconductor Memory Device | |
| CN103824861A (en) | Fin-like back gate storage structure and automatic refreshing method of floating body cells | |
| TWI795167B (en) | Semiconductor element memory device | |
| WO2022185540A1 (en) | Memory device in which semiconductor element is used | |
| WO2022168159A1 (en) | Memory device using semiconductor element | |
| WO2022168147A1 (en) | Semiconductor memory device | |
| Saha et al. | Performance analysis of a high speed, energy efficient 4× 4 dynamic RAM cell array using 32nm fully depleted SOI/SON and CNFET | |
| Sakui et al. | Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield | |
| Xie et al. | A Novel 1T-DRAM Fabricated With 22 nm FD-SOI Technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150826 Termination date: 20180705 |