KR101461629B1 - Memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and method of operating the same - Google Patents

Abstract

The present invention discloses memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using a bipolar junction transistor (bipolar junction transistor (BJT)) operation. The apparatus includes a memory array having a plurality of memory cells and a control unit, wherein each of the plurality of memory cells has a first node connected to at least one bit line, at least one source line and at least one word line, And a floating body transistor having a node and a gate node, wherein the control unit causes the refresh operation to be performed in response to the refresh command by selecting one of the at least one source line and at least one bit line, When stored in the memory cell connected to the selected line, the first current caused by the operation of the bipolar junction transistor flows.

Description

To memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating them same}

The present invention relates to memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating them with one transistor without a capacitor.

A typical memory, for example, a dynamic semiconductor memory device (DRAM), has one transistor and one capacitor. However, due to the size of the capacitor, in particular, the capacitor, there is a limitation in reducing the size of a general memory. As a result, memories having memory cells with one transistor 1T and no capacitor, referred to as " capacitor-less " memories, have been developed, The capacitorless 1T DRAM mentioned later may include an electrically floated body.

In general, a conventional capacitorless memory uses an SOI wafer having silicon on an insulator, accumulates a large number of carriers (holes or electrons) in the floating body region, or emits a large number of carriers from the floating body region, And identifies data that controls the area voltage. If a majority carrier is accumulated in the floating body region, this state is represented as data " 1 ", and conversely, if many carriers are emitted from the floating body region, this state is represented as data " 0 ".

There are two types of operation of a memory device without a common capacitor. One using metal oxide semiconductor transistor (MOS) operating characteristics and the other using bipolar junction transistor (BJT) operating characteristics. In general, it is disclosed that bipolar junction transistor operation has faster operation and / or better charge retention properties than MOS operation.

It is an object of the present invention to provide memory cell structures, memory cell arrays, memory devices, memory controllers, memory systems, and methods of operating them with one transistor without a capacitor for bipolar junction transistor operation have.

Embodiments illustrate memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and how to operate them, and may include memory cell structures, memory arrays, memory devices, memory controllers, Memory systems use bipolar junction transistor (BJT) operation.

An embodiment illustrates memory devices having a memory array having a plurality of memory cells and a controller, wherein each of the plurality of memory cells includes a first bit line, at least one source line, and a first And a floating body transistor having a node, a second node and a gate node, wherein the control unit causes the refresh operation to be performed in response to the refresh command by selecting one of the at least one source line and at least one bit line, When the first data is stored in the memory cell connected to the selected line, a first current caused by the operation of the bipolar junction transistor flows.

An embodiment illustrates memory devices having a memory array having a plurality of memory cells and a controller, wherein each of the plurality of memory cells includes a first bit line, at least one source line, and a first And a floating body transistor having a node, a second node and a gate node, wherein the control unit applies a bit line write voltage to at least one bit line and a source line voltage to at least one source line in accordance with data information , And performs a write operation by applying a word line write voltage to at least one word line.

Embodiments provide a memory structure comprising a silicon-on-insulator (SOI) structure and a gate structure comprising a substrate, an insulator and a silicon layer, wherein the silicon layer comprises first and second impurity-implanted nodes, a floating body region, And a buffer region between one of the second nodes and the floating body region, wherein the buffer region has an impurity concentration lower than the impurity concentration of the adjacent node and the floating body region, and the buffer region includes all of one A gate structure is formed on the silicon layer, covering the boundary.

An embodiment illustrates a memory structure comprising a silicon-on-insulator structure and a gate structure comprising a substrate, an insulator and a silicon layer, wherein the silicon layer comprises first and second impurity-implanted nodes, A floating body region having a floating body length and a buffer region between the first node and one of the second nodes and a floating body region, wherein the gate structure is formed on the silicon layer with a gate length, Or an impurity concentration lower than the impurity concentration of the floating body region, and the floating body length is longer than the gate length.

Embodiments illustrate a memory structure comprising a silicon-on-insulator structure comprising a substrate, an insulator and a silicon layer, wherein the silicon layer comprises an impurity implanted emitter / source and collector / drain, a floating body region, an emitter / source and a floating body An auxiliary body region between the regions and a gate structure over the silicon, and the auxiliary body region has a lower impurity concentration than the floating body region.

Embodiments illustrate a memory structure comprising a silicon-on-insulator structure and a gate structure comprising a substrate, an insulator and a silicon layer, wherein the silicon layer comprises first and second impurity-implanted nodes, a floating body region, And a gate structure is formed on the silicon layer.

The embodiment shows a memory cell structure including an insulating layer on the substrate, a silicon pattern formed on the insulating layer and including a first node, a second node and a floating body region, and a gate surrounding the floating body region, Is shorter than the length of the floating body region and a voltage difference between the voltages applied to the first and second nodes with respect to the set voltage applied to the gate induces a bipolar junction operation.

An embodiment includes a silicon pattern on an insulating layer over the substrate, an insulating layer comprising an extended body region over the first node, a second node, a floating body region and a floating body region, and a silicon body overlying the floating body region and the extended body region Lt; / RTI > shows a memory cell structure including a gate structure.

The embodiments illustrate a method of controlling a memory device comprising memory cells without a plurality of capacitors, the method comprising: providing a mode register setting (MRS) instruction that specifies one of a block refresh operation, a partial refresh operation, Lt; RTI ID = 0.0 > a < / RTI >

The embodiment shows a memory controller having a register for storing an MRS instruction for selecting one of a block refresh and a partial refresh operation.

The embodiment shows a capacitorless memory device comprising a register for storing information for selecting one of a block refresh and a partial refresh operation.

Embodiments illustrate a memory cell structure including a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes, a floating body region, and a gate over the floating body region , The length of the gate is less than the length of the floating body region, and the voltage difference between the voltages applied to the first and second nodes with respect to the set voltage applied to the gate induces a bipolar junction operation.

An embodiment illustrates a memory device having a plurality of memory cells and a control, wherein each of the plurality of memory cells has a first node connected to at least one bit line, at least one source line and at least one word line, And a gate, wherein the control unit causes the read operation to be performed by selecting one of the at least one source line and not selecting one of the at least one word line, The first current induced by the bipolar junction operation flows.

The memory cell structures, memory arrays and memory devices of the present invention are capable of increasing the charge retention time, thereby increasing the refresh period and allowing the bipolar junction transistor operation to be more smooth.

The memory system of the present invention does not require a separate instruction for transferring the row address and can transfer the row address and the column address at the same time when the write command and the read command are transmitted, This simplifies the control of the memory controller of the present invention.

The operation method of the present invention is simple and easy to control the operation of the bipolar junction transistor. Particularly, it is possible to perform the partial refresh operation and the block refresh operation by controlling the bit line or the source line in the refresh operation, and although the block refresh operation takes a long time for the refresh operation as compared with the partial refresh operation, All the time required for the refresh operation can be reduced.

Hereinafter, the memory cell structures, the memory cell arrays, the memory devices, the memory controllers, the memory systems, and the method of operating the same will be described with reference to the accompanying drawings.

1A shows a structure of an embodiment of a memory cell without a horizontal structure capacitor. As shown in FIG. 1A, a memory cell without a capacitor in a horizontal structure includes a substrate 10, for example, a substrate may be a P conductive type or an N conductive type substrate. If it is an NMOS transistor, the substrate 10 is a P conductivity type substrate.

The memory cell comprises an insulating layer 12 on a substrate 10 and the insulating layer 12 is an insulator of a silicon on insulator (SOI) arrangement. The memory cell includes a first node (14) and a second node (16) on an insulating layer (12). In MOS operation, the first and second nodes 14 and 16 may be referred to as source S and drain D, respectively. In a bipolar junction transistor (BJT) operation, the first and second nodes 14 and 16 may be referred to as emitter E and collector C, respectively. The first and second nodes 14 and 16 may be mutually altered. As an example, the first and second nodes 14 and 16 may be N-conductive or P-conductive. If it is an NMOS transistor, the first and second nodes 14 and 16 may be N-conductive.

The memory cell includes a floating body region 18 between the first and second nodes 14 and 16 and on the insulating layer 12 and the conductive type of the floating body region 18 includes the first and second nodes 14 and 16, Lt; RTI ID = 0.0 > 14 < / RTI > For an embodiment of an NMOS transistor, the floating body region 18 may be of the P conductivity type. As a result, the bipolar junction transistor (BJT) shown in Fig. 1A is an NPN-conducting bipolar junction transistor. The floating body region 18 is electrically separated from the substrate 12 by the insulating layer 12 and floated. As shown in FIG. 1A, the floating body region 18 may have a floating body length L1.

The memory cell further includes a gate structure G including a gate insulating layer 20 and a gate 22 and the gate 22 may have a gate length L2. As shown in FIG. 1A, a capacitor-free memory cell having a horizontal structure having a floating body region 18 may be formed on an insulating layer 12 formed additionally on a silicon substrate 10. [ As described above, the emitter / source E / S or the collector / drain C / D can be changed relative to each other. As a result, in the embodiment, the terms first node and second node will be described.

Generally, the emitter / source E / S is a node to which a relatively low voltage is applied, and the collector / drain C / D is a node to which a relatively high voltage is applied. Generally, L1 denotes the distance between the emitter / source E / S and the collector / drain C / D, and L2 denotes the gate length. In embodiments, L2 is longer than L1. This is generally done using self-alignment technology or lightly doped drain (LDD) technology to form the emitter / source E / S and collector / drain (C / D) Because.

1B shows an embodiment of a memory cell without a vertical structure capacitor. 1B, a memory cell without a capacitor in a vertical structure has a substrate 10, a first node 14, a floating body region 18, and a second node 16 formed vertically on the substrate 10 Respectively. The floating body region 18 is electrically floated. As shown in FIG. 1B, the floating body region 18 may have a floating body length L1.

The gate insulating layer 10 and the gate 22 may cover the floating body region 18. For example, the gate insulating layer 10 and the gate 22 may be in contact with all or a portion of two or more faces of the floating body region 18. As an example, L2 is longer than L1.

If the memory cell without a vertical structure capacitor is an NMOS transistor, then the first and second nodes 14 and 16 may be of a first conductivity type, for example N conductive, and the floating body region 18 may be of a first conductivity type, 2 conductive type, for example, a P conductive type. In addition, the vertical capacitor structure may have an SOI substrate, or may have a general bulk substrate as shown in FIG. 1B.

Fig. 2 shows an equivalent circuit of a capacitorless memory cell of Figs. 1A and 1B. As shown in Fig. 2, the equivalent circuit includes one NMOS transistor and one NPN bipolar junction transistor. For example, the emitter / source (E / S), collector / drain (C / D) and gate (G) of FIGS. 1A and 1B form NMOS transistors. Likewise, the emitter / source E / S, collector / drain (C / D) and electrically floating region 18 (or base B) of Figs. 1a and 1b form an NPN bipolar junction transistor. As shown in Fig. 2, a coupling capacitor CC is formed between the gate G of the NMOS transistor and the base B of the bipolar junction transistor.

In an embodiment, the bipolar junction transistor is also used to program / write not only to read and refresh the memory cell. The bipolar junction transistor generates a bipolar transistor current that is used to read the data state of the memory cell to program / write the data state to the memory cell and to refresh the data state of the memory cell.

3 illustrates the DC characteristics of a capacitorless memory cell according to an embodiment of the present invention. As shown in FIG. 3, for example, when Vg is set to OV, -1V, and -2V, Vds (or Vce) can rise from 0V to a voltage higher than OV, and logIds (or Ice) Lt; / RTI > As shown in Fig. 3, the left line of the graph for each gate voltage can be used to designate data " 1 ", and the right line can be used to designate data " 0 ". The difference between the left line designating data " 1 " and the right designation designating data " 0 " can be referred to as a sensing margin for each gate voltage. The majority carriers of the floating body region 18 for data " 1 " are larger than the majority carriers of the floating body region 18 for data " 0 ". In particular, Figure 3 shows a sharp change in current flow when Vds is greater than 1.5 V for all three gate voltages. The abrupt current increase is described below.

As shown in Figures 2 and 3, raising the voltage Vds is due to the forward bias between the emitter / source E / S and the base B and the reverse bias between the base B and the collector / drain C / Thereby increasing the electric potential of the electrically floating region 18 or the body B generating the bias. Thus, the bipolar junction transistor is turned on. As a result, electrons move from the emitter / source E / S through the body B to the junction between the base B and the collector / drain C / D, and these electrons collide with the silicon bulkhead at the junction And generates an electron-hole pair. This can be referred to as impact ionization or band-to-band tunneling.

For each electron-hole pair, the electrons move to the collector / drain (C / D) and the holes move to the base (B). Then, the voltage of the base B is increased and more electrons from the emitter / source E / S are injected into the floating body region, and the base B and the collector / drain C / D). The above operation is repeatedly performed, and due to the positive feedback, the multiplication can be large, which can be referred to as " avalanche generation ". As a result of the positive feedback, holes are accumulated in the floating body region, and this state can be referred to as data state " 1 ".

As shown in FIG. 3, the bipolar junction transistor operation occurs more quickly when Vg = 0V than when Vg = -1V and Vg = -2V. This is because the body potential of Vg = 0V is larger and the voltage between the base B of the high Vg and the emitter / source E / S of the emitter / source E / Because the forward bias will reach the forward bias more quickly than the voltage between. Likewise, the operation of the bipolar junction transistor of data " 1 " occurs faster than the operation of the bipolar junction transistor of data " 0 ".

4 shows a memory device having a memory array 150, a row controller 52 and a column controller 54. The memory device shown in FIG.

The memory array 150 includes memory cells MC1 to MCi without a plurality of capacitors and each memory cell is connected to a row control unit 52 and a column control unit 54. [ Each of the row control unit 52 and the column control unit 54 receives the write command WR, the read command RD, the refresh command REF, and / or the address signals ADD. Each memory cell is also connected to the word lines WL1, ..., WLi, the source lines SL1, ..., SLi, and the bit lines BL1, ..., BLj. As shown in Figure 4, each row of memory cells has a corresponding word line and a corresponding source line, i. E., The number of word lines and the number of source lines are the same. This structure can be referred to as a separate source line structure. In the embodiment of Figure 4, the first node is connected to the source line and the second node is connected to the bit line. As shown in FIG. 4, the word lines WL1, ..., WLi and the source lines SL1, ..., SLi may be arranged in the same direction, and the bit lines BL1, And may be arranged in a direction orthogonal to the lines and source lines.

4, the row control unit 52 outputs one of the word lines and one of the source lines in response to one of a write command WR, a read command RD, and a refresh command REF And may receive an address ADD to select. The column control unit 54 may receive the address ADD to select one of the bit lines in response to one of the write command WR, the read command RD and the refresh command REF.

The column control unit 54 may provide data information to the selected bit line during the write operation and receive data information from the selected bit line during the read operation. In addition, the column control unit 54 may supply a voltage level set to at least one of the bit lines during the refresh operation.

As an embodiment, the refresh command REF may be supplied from an external device or internally generated by counting the refresh period.

Although the row control unit 52 and the column control unit 54 are shown separately in FIG. 4, they may be implemented as one control unit that performs the functions of the two control units.

FIG. 5 shows a timing chart of an embodiment for the row operation of the memory device of FIG. 4. FIG. 5 shows a write operation, a read operation, and a refresh operation for writing both data "1" and data "0". In the following embodiment, the refresh operation may be a block refresh operation or a partial refresh operation. In the block refresh operation, all the memory cells are simultaneously refreshed, and the block refresh operation can perform the refresh at a high speed, but requires a large amount of current. In the partial refresh operation, a group of cells (e.g., 2, 4, or 8) are simultaneously refreshed, and each group is sequentially refreshed until all memory cells are refreshed. The partial refresh operation requires a low current, but can not perform a high-speed refresh.

5, the sections T0, T3, and T5 designate a holding or precharge or wait state before and / or after a write, read, or refresh operation, and sections T1 and T2 designate a write section (Twrite) T4 designates a read interval (Tread), and T6 designates a refresh interval (Trefresh). As to the bit lines (BL1-j) during the write operation and the bit line current (iBL1-j) during the write, read and refresh operations, the solid line indicates data "0" The displayed data is for data " 1 ".

Data "1" or data "1" is written into the memory cells MC1 connected to the word line WL1 and one row connected to the source line SL1 during the write interval Twrite as shown in FIG. 5, And is read during the read period (Tread). However, this is only an embodiment, and can be read and written to memory cells connected to any row.

5, the bit line holding voltage is applied to the bit lines, for example, OV, and the source line holding voltage, for example, 0 V, is applied to the source lines in the section T0 before the write operation And a word line holding voltage, for example, -1 V, is applied to the word lines.

5, if it is desired to write data " 0 " to the memory cells MC1 in the interval T1, the column control unit 54 sets the first level, for example, And supplies a voltage to the bit lines BL1 to j.

If it is desired to write data " 1 " to the memory cells MC1, the column control section 54 supplies the bit line write voltage of the second level, for example, 0V, to the bit lines BL1 to j. As an example, the second level of the bit line write voltage may be equal to the bit line hold voltage, e.g., 0V.

The memory cells MC2-i are controlled by a bit line holding voltage, for example OV, a source line holding voltage, for example 0 V, and a word line holding voltage, And the word lines, the data state stored in the memory cells MC2 to i can be maintained.

At this time, the row control unit 52 supplies the source line write voltage, for example, 2V to the source line SL1, and supplies the source line holding voltage, for example, 0V to all the other source lines SL2 to SL Continue to supply.

The row control unit 52 supplies the word line write voltage, for example OV, to the word line WL1 and supplies the word line holding voltage, for example -1 V, to all the other word lines WL2 to i .

5, a bit line write voltage (the voltage level depends on the written data information) is applied to the bit lines BL1 to j, and then the source line write voltage is applied to the source line SL1 . Finally, a word line write voltage is applied to the word line WL1. As shown in Fig. 5, when the bit line write voltage, the source line write voltage and the word line write voltage are applied to write data " 1 ", the voltage i2 flows through the bit lines BL1 to j.

As shown in the timing chart of Fig. 5, for data " 1 ", Vds is 2V and Vg is 0V during the interval T1. Thus, according to Fig. 3, the current i2 flowing through the bit lines BL1 to j is caused by the avalanche occurrence of the bipolar junction transistor operation. For the data " 1 ", during the interval T2, Vds is 2V and Vg is -1V. Thus, according to Fig. 3, the current i1 flowing through the bit lines BL1 to j is caused by the avalanche occurrence of the bipolar junction transistor operation. As shown in Fig. 5, the current i1 flowing through the bit lines BL1 to j during the period T2 is smaller than the current i2. This is because the body potential decreases as a result of the coupling effect of the coupling capacitor CC.

As shown in the timing chart of Fig. 5, for data " 0 ", Vds is 1.5V and Vg is 0V during the interval T1. Thus, according to Fig. 3, the avalanche of the bipolar junction transistor operation is not caused, and the holes can be discharged to the bit lines BL1 to j by the gate coupling effect. Similarly, for the data " 0 ", during the period T2, Vds is 1.5V and Vg is -1V. Thus, according to Fig. 3, the avalanche occurrence of the bipolar junction transistor operation is not caused, and as a result, no current flows through the bit lines BL1 to j.

The bit line write voltage has to be applied before the source line write voltage is applied and this means that if the source line SL1 is changed to 2 V before the voltage is applied to the bit line BL1, And the voltage between the emitter and the source (E / S) becomes 2V. As shown in Fig. 3, the operation of the bipolar junction transistor is caused, and holes can be accumulated in the floating body region B, and as a result, data "1" can be rewritten regardless of the data information.

As shown in Fig. 5, the application of the bit line write voltage can not be instantaneous. The bit line write voltage may begin to be applied before the source line write voltage is applied. Alternatively, the bit line write voltage may reach a constant state (e.g., the first level) before the source line write voltage is applied.

The source line write voltage must be applied before the word line write voltage is applied. This is because if the word line write voltage is changed to OV before the source line write voltage is applied to the source line SL1, the holes in the floating body region B are electrically connected to the bit line WL by the coupling effect of the coupling capacitor CC BL1 or source line SL1.

Further, as shown in the timing chart of FIG. 5, during the period T2, the word line holding voltage is applied again to the word line WL1 before the source line holding voltage is applied to the source line SL1. Then, the source line holding voltage is applied again to the source line SL1 before the bit line holding voltage is applied to the bit line BL1. In particular, the word line holding voltage is applied to the word line WL1 before the source line holding voltage is applied again to the source line SL1, which is before the word line holding voltage is applied to the word line WL1 The holes in the floating body region B are removed to the source line SL1 due to the forward bias between the floating body region B and the source line SL1 so that the memory cells The data " 1 " written to the MC1 may be damaged.

In addition, the source line holding voltage must be applied again to the source line SL1 before the bit line holding voltage is applied to the bit line BL1. This is because if the voltage of the bit line BL1 is changed to OV before the source line holding voltage is applied to the source line SL1, the voltage between the collector / drain C / D and the emitter / (Vds) becomes 2V, causing the operation of the bipolar junction transistor, and as a result, the data " 0 " written to the memory cells MC1 may be damaged.

Although FIG. 5 shows that all memory cells connected to word line WL1 and bit lines BL1 to j (or BLi) write one of data "1" and data "1" And each memory cell can be written with data " 1 " or data " 0 " according to the voltage of the corresponding bit line.

5 illustrates a read operation according to an embodiment of the present invention. As shown in FIG. 5, during a period T4, a read operation is performed on one row of memory cells connected to the word line WL1 and the source line SL1 Lt; / RTI >

5, a bit line holding voltage (for example, 0 V) is applied to the bit lines BL1 to j, a source line holding voltage is applied to the source lines SL1 to SL1, For example, a word line holding voltage, for example, -1V, is applied to 0V and word lines WL1 to i.

The row control unit 52 supplies the source line read voltage, for example, 2V to the source line SL1 and continuously applies the source line holding voltage, for example, 0V, to the other source lines SL2 to i do. The row control unit 52 continuously supplies the word line holding voltage, for example, -1 V to the word lines WL1 to i.

In an embodiment, the read operation may be performed by supplying a source line read voltage coupled to the memory cell being read. During the read operation, the bit lines BL1 to j can be electrically floated after being precharged by the holding voltage, and the voltage of the bit lines BL1 to j can be changed according to the data stored in the memory cell . That is, the column control unit 54 does not need to supply the holding voltage to the bit lines during the read operation. Further, the above description is applicable when the voltage sense amplifier is used as a bit line sense amplifier. However, it can not be applied if a current sense amplifier is used as a bit line sense amplifier.

The memory cells MC2 to i are maintained in a maintained state by supplying a bit line holding voltage, for example, OV, a source line holding voltage, for example, OV, and a word line holding voltage, .

As shown in FIG. 3, when the voltage (Vds) between the drain and the source reaches 2V when Vg is -1V, the bipolar junction transistor operation is induced for the data " 1 " do. That is, the read current i1 caused by the operation of the bipolar junction transistor flows through the data "1" cell, and the read current i1 does not flow through the data "0" cell. In the embodiment, the write current i2 and the read current i1 can be the same.

As a result, the data can be identified by a later sense amplifier, for example a current sense amplifier or a voltage sense amplifier. In the embodiment, in the row operation as shown in Fig. 5, since the data for each of the bit lines is read, the same number of sense amplifiers as the bit lines are required.

In addition, data " 1 " and data " 0 " stored in the memory cell connected to the selected source line SL1 during the read operation can be restored by the bipolar junction transistor operation and the coupling operation, respectively.

5 is an operation timing chart showing a refresh operation according to an embodiment of the present invention.

As shown in Fig. 5, in the period T5 before the refresh operation, the bit lines BL1 to j are connected to the bit line holding voltage, for example, 0 V, the source line holding voltage to the source lines SL1 to i, For example, 0 V, and the word line holding voltage, for example, -1 V, is applied to the word lines WL1 to i.

When the refresh command REF is generated by an external device or an internal circuit, the row control unit 52 supplies a refresh voltage, for example, 2V to all the source lines SL1 to SL. Also, the row control section 52 can sequentially supply the refresh voltage to at least two source lines, whereby the current during the refresh operation can be reduced. The number of source lines activated at one time during a refresh operation may be set by the user using the setup steps described in detail below in connection with FIG.

All the memory cells connected to the source lines SL1 to i are refreshed by only supplying the source lines SL1 to i with a voltage capable of causing bipolar junction transistor operation in the cells in which the data " 1 " That is, the cells in which the data " 1 " are stored are refreshed by the bipolar junction transistor operation and the cells in which the data " 0 " are refreshed by the coupling effect between the source line and the floating body region. The row control unit 52 continuously supplies the word line holding voltage, for example, -1 V to the word lines WL1 to i.

During the refresh period Trefresh, as shown in Fig. 5, current i1 flows through the bit line connected to the cell in which data " 1 " is stored. As an embodiment, the refresh current i1 may be equal to the read current i1 and / or the write current i2.

As an embodiment, a refresh operation may be performed by supplying a refresh voltage to at least one bit line instead of applying a voltage to at least one source line.

As shown in Fig. 5, all the source lines SL1 to i are refreshed. If a voltage capable of causing bipolar junction transistor operation is supplied to the mode source lines or all bit lines, then all memory cells may be refreshed at the same time. This may be referred to as block refresh.

In an embodiment, the number of source lines selected for simultaneous refresh operation may be a group of source lines (e.g., 2, 4, or 8) in a mode register set by the user, ) Unit. This may be referred to as a partial refresh operation.

In an embodiment, the refresh operation need not be performed by a sensing operation.

FIG. 6 is an operation timing chart for explaining the operation of one cell of the memory device of FIG. 4, and shows the operations of the write operation (write operation for data "1" and data "0"), the read operation, and the refresh operation Lt; / RTI > In the embodiment described below, the refresh operation may be a block refresh operation or a partial refresh operation.

6, the write operation and the read operation are performed only for the memory cell MC1 connected to the bit line BL1, the source line SL1 and the word line WL1, and the source line SL1 and the word Is not performed for the other memory cells MC1 connected to the line WL1, and is in a prohibited state. Other explanations other than the prohibited state for both the write operation and the read operation can be easily understood with reference to the description of FIG.

As described above, the difference between FIG. 5 and FIG. 6 is that the cell is not written in one row in FIG. 6 but is written to or read from one cell. As a result, in Fig. 6, the remaining cells of one row that are not written or read are prohibited from writing or reading. In the embodiment, the remaining cells of one row are inhibited from being written or read by applying the bit line write inhibit voltage or the bit line read inhibit voltage to the bit lines (BL2 to j).

During a write operation, a bit line write inhibit voltage, for example, 1 V, is applied to the bit lines BL2 to j during the periods T1 and T2. As a result, Vds is 1 V, and the bipolar junction transistor operation is inhibited, as shown in Fig. 3, and no current flows.

Similarly, during the read operation, during the period T4, a bit line read prohibition voltage, for example, 1 V, is applied to the bit lines BL2 to j. As a result, Vds is 1 V, and the bipolar junction transistor operation is inhibited, as shown in Fig. 3, and no current flows.

The refresh operation shown in Fig. 6 is the same as the refresh operation shown in Fig.

The timing diagram of Fig. 6 clearly shows that the random access operation of the memory cell array is possible.

As shown in Figures 5 and 6, the memory device requires only two voltage levels, a word line write voltage and a word line hold voltage for write, read and refresh operations.

7 shows a memory device according to an embodiment of the present invention, unlike the memory device according to the embodiment shown in FIG. 4, which shows a separate source line structure, the memory device of FIG. 7 includes, for example, adjacent memory cells MC2 and MC3 share a corresponding source line SL2. The description of the remaining part of FIG. 7 can be easily understood with reference to the description of FIG.

As shown in Fig. 7, the number of the source lines SL1 to k is smaller than the number of the word lines WL1 to i. The advantage of this arrangement is that layout complexity can be reduced. Additionally, as described in the embodiment of FIG. 4, the row controller 52 and the column controller 54 may be implemented as a single controller.

FIG. 8 is an operation timing chart for explaining the row operation of the memory device of FIG. 7, showing timing diagrams of the write operation (data "1" and data "0" write operation), read operation and refresh operation. In the embodiment described below, the refresh operation may be a block refresh operation or a partial refresh operation.

The timing diagram of FIG. 8 shows that the gate voltage Vg during the periods T0, T3, and T5 is lower than that shown in FIG. 5 because the transistors sharing the common source lines SL1- Is similar to the timing of Figure 5, except that it may be a negative (e.g., -2 V) voltage.

In the embodiment shown in Fig. 8, the order of the control signals applied to the bit lines (BL1 to j), the source lines (SL1 to k) and the word lines (WL1 to i) May be the same as shown.

As shown in the timing chart of Fig. 8, for the data " 1 ", during the interval T1, Vds is 2V and Vg is 0V and so, according to Fig. 3, through the bit lines BL1 to j The current i3 is caused by the avalanche occurrence of the bipolar junction transistor operation. For data " 1 ", during the interval T2, even though Vds is 2V and Vg is -2V, since the body potential remains sufficiently high to create a forward bias between the bit lines BL1 to j, (I4) through the bit lines BL1-j is caused by the avalanche occurrence of the bipolar junction transistor operation. As shown in Fig. 8, the current i4 through the bit lines BL1 to j during the period T2 is smaller than the current i3. This is because the coupling between the coupling capacitors CC reduces the body potential.

As shown in the timing chart of Fig. 8, Vds is 1.5V and Vg is 0V for the data " 0 " during the period T1. Thus, according to FIG. 3, no avalanche occurrence of the bipolar junction transistor operation is caused. Similarly, for data " 0 ", Vds is 1.5 V and Vg is -2 V during the period T2. Thus, according to FIG. 3, no avalanche occurrence of the bipolar junction transistor operation is caused. As a result, no current flows through the bit lines BL1 to j.

In an embodiment, the word line write voltage may be -1 V, not 0 V as shown in Figures 5 and 8.

As shown in Fig. 8, although three levels of voltage are applied to the word lines WL1 to i, -2V, - < RTI ID = 0.0 > 1V, and 0V may be used, but a voltage of two levels, for example, -1V and 0V, as shown in Fig. 5, may be used.

8, the order of the control signals applied to the bit lines BL1 to j, the source lines SL1 to k, and the word lines WL1 to i during the read operation is shown in Fig. Lt; / RTI >

8, during the read operation, the row control unit 52 supplies the source line read voltage, for example, 2V to the source line SL1, and supplies the source line SL2 with all the remaining source lines SL2- A constant voltage, for example, 0 V is continuously supplied. The row control unit 52 applies the word line read voltage, for example, -1 V to the word line WL1 and continues the word line holding voltage, for example -2 V, to the other word lines WL2 to i .

In an embodiment, the read operation may be performed by supplying only the source line lead voltage to the source line connected to the memory cell being read. In the read operation, the bit lines BL1 to j can be electrically floating after being precharged by the holding voltage, and the voltage of the bit lines BL1 to j can be changed according to the data stored in the memory cell have. That is, the column control section 54 does not need to supply the holding voltage to the bit lines BL1 to j during the read operation, and the above description can also be applied when the voltage sense amplifier is used as the bit line sense amplifier, It can not be applied when the current sense amplifier is used as a bit line sense amplifier.

As shown in FIG. 3, when the gate voltage Vg is -1 V, the voltage (Vds) between the drain and the source reaches 2 V, so that the operation of the bipolar junction transistor is not the cell in which data "0" A "1" is triggered for the stored cell. That is, the read current i5 induced by the operation of the data bipolar junction transistor flows for the memory cell in which the data "1" is stored and does not flow for the memory cell in which the data "0" is stored.

As a result, the data can be identified by a sense amplifier, for example, a current sense amplifier or a voltage sense amplifier.

Additionally, data " 1 " and data " 0 " can be restored by the bipolar junction transistor operation and the coupling effect, respectively, during the read operation.

8, except that the row controller 52 selects at least two word lines and supplies the word line refresh voltage to at least two word lines, the bit lines BL1 to j, The order of the control signals for the refresh operation between the source lines SL1 to k and the word lines WL1 to i may be the same as the read operation shown in Fig. The word line refresh voltage may be equal to the word line read voltage, and the read current i5 may be equal to the refresh current i6. The same explanation as the refresh operation in Fig. 5 can be applied to the refresh operation in Fig.

FIG. 9 shows a timing chart for explaining one cell operation of the memory device shown in FIG. 7. FIG. 9 shows timing charts of embodiments of the write operation (write operation of data "1" and data "0"), read operation and refresh operation. In the embodiment described below, the refresh operation may be a block refresh operation and a partial refresh operation.

9, the write operation and the read operation are performed only for one memory cell MC1 connected to the bit line BL1, the source line SL1 and the word line WL1, and the source line SL1 and the word The other memory cells MC1 connected to the line WL1 are in a prohibited state. 8 except for the write operation and the read operation.

As described above, the difference between FIG. 8 and FIG. 9 is not written or read to all the cells connected to one row, but is written or read in only one cell in FIG.

During a write operation, a bit line forbidden voltage, for example, 1V, is applied to the bit lines BL2 to BLj during the sections T1 and T2. As a result, Vds is 1 V, and the bipolar junction transistor operation is inhibited and no current flows, as shown in Fig.

Similarly, during the read operation, during the period T4, a bit line read inhibition voltage, for example, 1 V, is applied to the bit lines BL2 to BLj. As a result, Vds is 1V, and the bipolar junction transistor operation is inhibited, as shown in Fig. 3, and no current flows.

As shown in Fig. 9, the refresh operation is the same as that of Fig.

The timing diagram of FIG. 9 clearly shows that the random access operation of the memory cell array is possible.

As shown in Figures 8 and 9, although three levels of voltage (e.g., a word line write voltage of 0V, a word line refresh voltage of -1V and a word line read voltage, and a word line hold voltage of -2V) Although shown for the word lines WL1-i, it is also possible to use two levels of voltage (e.g., a word line write voltage of 0V for word lines WL1-i, as shown in FIG. 5, A word line holding voltage, a word line holding voltage, a word line refresh voltage) can be used.

10 shows a memory device according to an embodiment of the present invention. 10 shows a memory device including a row controller and a column controller as well as a plurality of memory blocks BK1, BK2, ..., BKn. In an embodiment, each memory cell block may be the same or similar to the memory cell blocks shown in Figs. Additionally, as shown in Fig. 10, the sense amplifiers SA1-n may be provided between the memory blocks, and the sense amplifiers SA1-n may be voltage sense amplifiers or current sense amplifiers.

10 shows an open bit line structure, but it can also be applied to a folded bit line structure.

In the embodiment shown in FIG. 10, the memory cell array may include a plurality of memory cell blocks as shown in FIGS. 4 and 7, and may write and read data to at least one selected memory cell block. In an embodiment, the row control unit 52 " selects at least one memory block, a source line and a word line in the selected memory block in response to a write command WR, a read command RD and / or an address signal ADD And supply appropriate voltages to selected source lines and word lines.

Further, the row control section 52 " selects at least one memory block in response to the refresh command REF and supplies the refresh voltage to at least two source lines in the selected memory block. In addition, the row control section 52 " may perform a block refresh operation when supplying the refresh voltage to all of the source lines SL1 to SLk in the selected memory block. Also, all memory blocks of the memory device may be refreshed by supplying a refresh voltage to all of the source lines SL1-k in each memory block.

In an embodiment, the column control unit 54 " controls the bit line voltage level according to one row operation or data information according to one cell operation. In addition, the column control section 54 " can control the refresh operation by supplying a predetermined voltage to at least one bit line. If a predetermined voltage is applied to all the bit lines BL1 to j, all memory cells in the memory cell array can be refreshed. The predetermined voltage may be the same as the refresh voltage applied to the source line.

In the embodiment shown in Fig. 10, each of the sense amplification blocks SA1 to n supplies data information to the corresponding bit line during a write operation, and can sense and amplify data of the memory cell. For a single row operation, the number of sense amplifiers in each sense amplifier block (SA1-n) may be equal to the number of bit lines. For random access operation, The number of sense amplifiers can be reduced.

The operation of a bipolar junction transistor for a memory device including a capacitorless memory cell will be described in accordance with an embodiment. Although the memory cell structures of Figures 1A and 1B may be used for memory devices such as the Figures 4, 7, and 10 described above. Additional new memory cell structures for the memory devices of Figs. 4, 7 and 10 according to embodiments will be described hereinafter. In the figure, the same elements of memory cells have the same reference numerals.

11A and 11B show a memory cell structure according to an embodiment of the present invention. As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In an embodiment, the first and second nodes 14 and 16 in the silicon layer may be N-type impurities. In an embodiment, the emitter / source E / S may be an N-type impurity (e.g., N +) having a higher impurity concentration than the collector / drain (C / D). In an embodiment, the gate, emitter / source E / S and / or collector / drain (C / D) are not superimposed, as shown in FIG. 11A, the boundary between the floating body region 18, the emitter / source E / S and / or the collector / drain C / D includes a gate, emitter / source E / / / Collector / drain (C / D) are not superimposed and can have any form.

As shown in Fig. 3, the sensing margin can be determined by the voltage (Vds) between data " 1 " and data " 0 ". The capacitance of the gate G between the gate and the floating body region must be reduced in proportion to the drain capacitance Cd or the source capacitance Cs in order to increase the sensing margin.

As a result, the gate and source and / or drain must not overlap. Since the spacing between the gate G and the emitter / source E / S and the collector / drain C / D is large, the non-overlapping memory cell structure has a lower energy band slope than the memory cell structure of FIG. . As a result, as compared to the memory cell structure of FIG. 1A, the maximum field (E-field) can be reduced and the recombination rate can be reduced. Due to this characteristic, the non-overlapping memory cell structure of Figure 11A exhibits better retention time and / or better leakage characteristics.

Additionally, the gate induced drain leakage (GIDL) phenomenon, which can damage the data " 0 ", can be reduced because the capacitance Cgd between the gate and the drain is reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner to stabilize the coupling capacitance between the gate and the floating body region 18.

Although not shown in FIG. 11A, the gate may overlap only one of the first node 14 and the second node 16. For example, the gate may overlap only one of the first node 14 and the second node 16 that receives a higher voltage during the bipolar junction operation.

The sensing margin may vary depending on the charge difference stored in the floating body area between the cell where data "1" is stored and the cell where data "0" is stored. Since the cell storing the data " 1 " has more charge than the cell storing the data " 0 ", and the cell potential of the cell storing the data " 1 " is higher than the cell potential of the cell storing the data " The operation is triggered in a cell where data "1" is stored earlier than in the cell where data "0" is stored. This can be seen from the fact that, for all gate voltages Vg, the cell where data " 1 " is stored is on the left of the cell where data " 0 " is stored, as shown in FIG.

As a result, if more charge can be stored in the floating body area of the cell where data " 1 " is stored during the write operation, a better sensing margin is secured.

In addition, the average free path of electrons between the base and the collector can be longer than the mean free path of FIG. 1A. As a result, avalanche can occur more easily. Further, more charge can be stored in the floating body region of the data " 1 " cell. In an embodiment, the impurity concentration between the emitter / source (E / S) may be greater than the impurity concentration between the collector / drain (C / D). Additionally, as described in the embodiments, the holes accumulated by the bipolar junction transistor operation can be held near the gate due to the negative word line holding voltage. As shown in FIG. 11A, if the floating body region 18 near the gate G is wider than at least one other portion of the floating body region 18, the retention time can be improved.

11B shows a memory cell of a vertical structure according to an embodiment of the present invention. 11B, a memory cell without a capacitor in a vertical structure has a substrate 10, a first node 14 vertically stacked on the substrate 10, a floating body region 18, and a second node (not shown) 16). The floating body region 18 may be electrically floating. As shown in FIG. 11B, the floating body region 18 may have a floating body length L1.

The gate insulating layer 20 and the gate 22 may be formed so as to surround the floating body region 18. For example, the gate insulating layer 20 and the gate 22 may be in contact with the front surface of the floating body region 18 or with two or more portions of the surface. If the memory cell without a vertical structure capacitor is an NMOS transistor, then the first and second nodes 14 and 16 may be of a first conductivity type, for example N conductive, and the floating body region 18 may be of a first conductivity type, 2 conductive type, for example, a P conductive type. In addition, a memory cell without a vertical structure capacitor may have an SOI substrate or a general bulk substrate as shown in Fig. 11B.

As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In the embodiment, there is no overlap between the gate electrode and the emitter / source E / S and / or the collector / drain C / D, as shown in FIG. 11B. The features mentioned with respect to Fig. 11A may be present in the memory cell of the vertical structure of Fig. 11B.

12A and 12B illustrate a memory cell structure according to an embodiment of the present invention. As shown in FIGS. 12A and 12B, in order to improve the multiplication and avalanche occurrence, a buffer region 24 is formed in the floating body region 18, And the collector / drain (C / D). In the embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D) and / or the floating body region 18. In an embodiment, an intrinsic semiconductor may be used as the buffer region 24. In an embodiment, the buffer region 24 may have the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

In an embodiment, the buffer region 24 increases the average free path of electrons from the base to the collector / drain (C / D). By increasing the average free path, the impact ionization for avalanche generation can be improved. Thus, more charge can be stored in the data " 1 " cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be greater than the impurity concentration of the collector / drain (C / D). In an embodiment, if buffer region 24 is an N- impurity concentration, L2 may be greater than L1. On the other hand, if buffer region 24 is an impurity concentration of P-, then L2 may be less than L1.

As shown in FIG. 12B, the vertical cell structure can be implemented without increasing the layout area of the buffer region 24. This is because, as shown in FIG. 12B, the buffer region 24 is formed in the vertical direction.

12B shows a memory cell of a vertical structure according to an embodiment of the present invention. As shown in FIG. 12B, a memory cell without a vertical structure capacitor includes a substrate 10, A floating body region 18, a buffer region 24, and a second node 16. The first node 14, the floating body region 18, the buffer region 24, The floating body region 18 is electrically floating, and the floating body region 18 may have a floating body length L1, as shown in FIG. 12B.

The gate insulating layer 20 and the gate 22 may surround the floating body region 18. For example, the gate insulating layer 20 and the gate 22 may be in contact with all faces of the floating body region 18 or with faces of two or more portions. If the memory cell without a vertical structure capacitor is an NMOS transistor, then the first and second nodes 14 and 16 may be of a first conductivity type, for example N conductive, and the floating body region 18 may be of a first conductivity type, 2 conductive type, for example, a P conductive type. In addition, a memory cell without a capacitor in a vertical structure may have an SOI substrate or a general bulk substrate as shown in Fig. 12B.

As shown, to improve multiplication and avalanche occurrence, a buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D). In the embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D) and / or the floating body region 18. In an embodiment, an intrinsic semiconductor may be used as the buffer region 24. In an embodiment, the buffer region 24 may have one impurity concentration of N-, N, or P-. In an embodiment, the buffer region 24 has the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

The boundary between the floating body region 18, the emitter / source E / S, the collector / drain C / D, and / or the buffer region 24, as shown in Figures 12A and 12B, Lt; / RTI >

Other features described above with respect to FIG. 12A may also exist for the memory cell of the vertical structure of FIG. 12B.

In an embodiment, a memory cell with no vertical capacitor may have an SOI substrate or a conventional bulk substrate such as that shown in Figure 12B.

13A and 13B show a memory cell structure according to an embodiment of the present invention, and FIGS. 13A and 13B show a structure combining features shown in FIG. 11 and FIGS. 12A and 12B. In the embodiment shown in Figs. 13A and 13B, L1 is greater than L2 even when the buffer region 24 is N-. Compared to Figs. 11A and 11B, the embodiment shown in Figs. 13A and 13B can lead to a reduction in the gate induced drain leakage phenomena and / or an increase in the average free path.

As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In the embodiment, there is no overlap between the gate electrode G, the collector / drain (C / D), and the emitter / source E / S, as shown in Fig. As shown in FIG. 3, the sensing margin can be determined by the voltage difference (Vds) between the drain and source between the data "1" cell and the data "0" cell. In order to increase the sensing margin, the gate capacitance Cg for the drain capacitance Cd or the source capacitance Cs must be reduced.

As a result, there is no overlap between the gate and the source or the drain, and additionally, the gate-induced drain leakage phenomenon, which can damage the data " 0 " cell, can be reduced because the capacitance Cgd between the gate and the drain is reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner, stabilizing the coupling capacitance between the gate and the body. In an embodiment, the gate length L2 is less than the floating body length L1. These parameters can improve scalability.

The sensing margin may vary depending on the charge difference stored in the floating body region 18 between the data "1" cell and the data "0" cell. The data " 1 " cell has more charge than the data " 0 " cell. Accordingly, the body potential of the data "1" cell is higher than the body potential of the data "0" cell. The bipolar junction transistor operation occurs faster in the data "1" cell than in the data "0" cell. This is because the graph of the data " 1 " cell is to the left of the graph of the data " 0 " cell, as shown in FIG.

As a result, if a more charge in the write operation can be stored in the floating body area 18, which is a data " 1 " cell, it will have a better sensing margin.

Additionally, the average free path of holes between the base and the collector / drain (C / D) may be longer than the mean free path of FIG. 1A. Thus, impact ionization for avalanche generation can occur more rapidly. As a result, more charge can be stored in the data " 1 " cell. As an example, the impact ionization of the emitter / source (E / S) may be larger than the impact ionization of the collector / drain (C / D).

13A and 13B, a buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D) to improve the multiplication and avalanche occurrence. In the embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D). In an embodiment, an intrinsic semiconductor may be used as the buffer region 24. In an embodiment, the buffer region 24 may have one impurity concentration of N-, N, or P-. In an embodiment, the buffer region 24 has the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12. In an embodiment, the buffer region 24 increases the average free path of holes from the base to the collector / drain (C / D). The impact ionization for avalanche generation can be improved by increasing the average free path. Thus, more charge can be stored in the data " 1 " cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D).

As shown in Fig. 13B, the memory cell of the vertical structure can be implemented without increasing the layout area of the buffer region 24. [ This is because, as shown in FIG. 13B, the buffer region 24 is formed in a vertical structure.

The boundary between the floating body region 18, the emitter / source E / S, the collector / drain C / D, and / or the buffer region 24, as shown in Figures 13A and 13B, Lt; / RTI >

In an embodiment, a memory cell without a capacitor in a vertical structure may have an SOI substrate or a general bulk substrate such as that shown in Figure 13B.

14A and 14B show a memory cell structure according to an embodiment of the present invention. As shown in FIGS. 14A and 14B, the auxiliary body region 26 is provided to increase the electron injection efficiency from the emitter / source E / S to the floating body region 18. In an embodiment, the impurity concentration of the auxiliary body region 26 may be less than the impurity concentration of the floating body region 18. [ In an embodiment, the floating body region 18 may be longer than the auxiliary body region 26. In an embodiment, the auxiliary body region 26 is in contact with the emitter / source E / S.

In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thereby achieving a more efficient bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

As shown in Fig. 14B, the memory cell of the vertical structure can be implemented without increasing the layout of the auxiliary body region 26. [ This is because, as shown in Fig. 14B, the auxiliary body region 26 is formed in the vertical direction.

14A and 14B, the boundary between the floating body region 18, the emitter / source E / S, the collector / drain C / D, and / or the auxiliary body region 26, Lt; / RTI >

In an embodiment, the memory cell of the vertical structure may have an SOI substrate or a general substrate as shown in Fig. 14B.

Figures 15A-15C illustrate a memory cell structure of an embodiment that combines the features of Figures 11A-14B. 15A shows a memory cell structure that combines the features of FIGS. 11A and 14A, and in particular FIG. 15A shows gate 22 and floating body region 18, where L1 may be greater than L2 and auxiliary body region 26 Is provided to increase the electron injection efficiency from the emitter / source (E / S) to the floating body region 18.

As shown, the source line may be connected to the collector / drain (C / D) and the bit line may be connected to the emitter / source (E / S). In the embodiment, there is no overlap between the gate 22, the collector / drain (C / D), and the emitter / source E / S, as shown in Fig. As shown in FIG. 3, the sensing margin can be determined by the voltage difference (Vds) between the drain and source between the data "1" cell and the data "0" cell. In order to increase the sensing margin, the gate capacitance Cg for the drain capacitance Cd or the source capacitance Cs must be reduced.

As a result, there is no overlap between the gate 22 and the emitter / source E / S or the collector / drain C / D, and additionally the capacitance Cgd between the gate and the drain is reduced, "Gate-induced drain leakage that can damage cells can be reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner, stabilizing the coupling capacitance between the gate and the body. In an embodiment, the gate length L2 is less than the floating body length L1. These parameters can improve scalability.

The sensing margin may vary depending on the charge difference stored in the floating body region 18 between the data "1" cell and the data "0" cell. The data " 1 " cell has more charge than the data " 0 " cell. Accordingly, the body potential of the data "1" cell is higher than the body potential of the data "0" cell. The bipolar junction transistor operation occurs faster in the data "1" cell than in the data "0" cell. This is because the graph of the data " 1 " cell is to the left of the graph of the data " 0 " cell, as shown in FIG.

As a result, if a more charge in the write operation can be stored in the floating body area 18, which is a data " 1 " cell, it will have a better sensing margin.

Additionally, the average free path of holes between the base and the collector / drain (C / D) may be longer than the mean free path of FIG. 1A. Thus, impact ionization for avalanche generation can occur more rapidly. As a result, more charge can be stored in the data " 1 " cell. In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D).

In an embodiment, the impurity concentration of the auxiliary body region 26 may be lower than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 may be longer than the auxiliary body region 26. In an embodiment, the auxiliary body region 26 is in contact with the emitter / source E / S.

In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thereby achieving a more efficient bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

The memory cell of the vertical structure can be implemented without increasing the layout of the auxiliary body region 26. [ This is because, as shown in Fig. 14B, the auxiliary body region 26 is formed in the vertical direction.

In an embodiment, the memory cell of the vertical structure may have the characteristics of 15a, and the memory cell of the vertical structure may have the SOI substrate or a general substrate as shown in Fig. 15A.

Figure 15B shows a memory cell having a combination of features shown in Figures 12A and 14A. The buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D) to improve the multiplication and avalanche occurrence, as shown in Fig. 15B. In the embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D). In an embodiment, an intrinsic semiconductor may be used as the buffer region 24. In an embodiment, the buffer region 24 may have one impurity concentration of N-, N, or P-. In an embodiment, the buffer region 24 has the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

In an embodiment, the buffer region 24 increases the average free path of holes from the base to the collector / drain (C / D). The impact ionization for avalanche generation can be improved by increasing the average free path. Thus, more charge can be stored in the data " 1 " cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D). In an embodiment, if the buffer region 24 is N-, L2 may be longer than L1, whereas if the buffer region 24 is P- then L2 may be less than L1.

As shown in FIG. 15B, the auxiliary body region 26 is provided to increase the electron injection efficiency from the emitter / source E / S to the floating body region 18. In an embodiment, the impurity concentration of the auxiliary body region 26 may be lower than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 may be longer than the auxiliary body region 26. In an embodiment, the auxiliary body region 26 is in contact with the emitter / source E / S.

In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thereby achieving a more efficient bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

The memory cell of the vertical structure can be implemented without increasing the layout of the buffer region 24 and the auxiliary body region 26. [ This is because the buffer region 24 and the auxiliary body region 26 are formed in the vertical direction, as shown in Figs. 13B and 14B.

In an embodiment, a vertically structured memory cell may have the characteristics of 15b, and in an embodiment, the vertically structured memory cell may have an SOI substrate or a general substrate as shown in FIG. 15A.

15C shows a memory cell of an embodiment that combines the features of FIGS. 11A, 12A, and 14A, in which a source line SL is connected to a collector / drain (C / D) ) Can be connected to the emitter / source (E / S). In the embodiment, there is no overlap between the gate 22, the collector / drain (C / D), and the emitter / source E / S, as shown in Fig.

As shown in FIG. 3, the sensing margin can be determined by the voltage difference (Vds) between the drain and source between the data "1" cell and the data "0" cell. The gate 22 and the emitter / source E / S or the collector / source E / S must be reduced in order to increase the sensing margins. As a result, the gate capacitance Cg must be reduced with respect to the drain capacitance Cd or the source capacitance Cs. There is no overlap between the drain (C / D) and additionally, the capacitance (Cgd) between the gate and the drain is reduced, so that the gate-induced drain leakage phenomenon which can damage the data " 0 " cell can be reduced.

In addition, the reduced gate capacitance Cg can be compensated for by making the insulating layer 20 thinner, stabilizing the coupling capacitance between the gate and the body. In an embodiment, the gate length L2 is less than the floating body length L1. These parameters can improve scalability.

The sensing margin may vary depending on the charge difference stored in the floating body region 18 between the data "1" cell and the data "0" cell. The data " 1 " cell has more charge than the data " 0 " cell. Accordingly, the body potential of the data "1" cell is higher than the body potential of the data "0" cell. The bipolar junction transistor operation occurs faster in the data "1" cell than in the data "0" cell. This is because the graph of the data " 1 " cell is to the left of the graph of the data " 0 " cell, as shown in FIG.

As a result, if a more charge in the write operation can be stored in the floating body area 18, which is a data " 1 " cell, it will have a better sensing margin.

Additionally, the average free path of holes between the base and the collector / drain (C / D) may be longer than the mean free path of FIG. 1A. Thus, impact ionization for avalanche generation can occur more rapidly. As a result, more charge can be stored in the data " 1 " cell. In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D).

As shown in FIG. 15C, a buffer region 24 may be formed between the floating body region 18 and the collector / drain (C / D) to improve multiplication and avalanche occurrence. In the embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter / source E / S. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector / drain (C / D) and / or the floating body region 18. In an embodiment, an intrinsic semiconductor may be used as the buffer region 24. In an embodiment, the buffer region 24 may have the same height as the adjacent second node 16. In an embodiment, the buffer region 24 may cover all of the boundaries of the adjacent second node 16. In an embodiment, the buffer region 24 is in contact with the insulating layer 12.

In an embodiment, the buffer region 24 increases the average free path of electrons from the base to the collector / drain (C / D). By increasing the average free path, the impact ionization for avalanche generation can be improved. Thus, more charge can be stored in the data " 1 " cell.

In an embodiment, the impurity concentration of the emitter / source (E / S) may be higher than the impurity concentration of the collector / drain (C / D). As shown in Fig. 15C, the auxiliary body region 26 is provided to increase the electron injection efficiency from the emitter / source E / S to the floating body region 18. [ In an embodiment, the impurity concentration of the auxiliary body region 26 may be lower than the impurity concentration of the floating body region 18. In an embodiment, the floating body region 18 may be longer than the auxiliary body region 26. In an embodiment, the auxiliary body region 26 is in contact with the emitter / source E / S. In an embodiment, the auxiliary body region 26 allows more holes to be injected into the floating body region 18 and to be obtained at the base and collector / drain (C / D), thereby achieving a more efficient bipolar junction transistor operation This can happen. In an embodiment, the impurity concentration of the emitter / source (E / S) is higher than the impurity concentration of the collector / drain (C / D) and / or base.

The memory cell of the vertical structure can be implemented without increasing the layout of the buffer region 24 and the auxiliary body region 26. [ This is because the buffer region 24 and the auxiliary body region 26 are formed in the vertical direction, as shown in Figs. 13B and 14B.

As shown in Figs. 11A and 14B, the boundary between the regions may have any form.

In an embodiment, a memory cell of a vertical structure may have the features of FIG. 15C, and a memory cell of a vertical structure may have an SOI substrate or a general substrate as shown in FIG. 14B.

16A illustrates a plan view of a memory cell structure according to an embodiment of the present invention. As shown in FIG. 16A, a memory cell structure includes a first node 14 (e.g., emitter / source E / S) ), A second node 16 (e.g., a collector / drain (C / D)), a floating body region 18, a word line 21, an extended body region 27, a first contact 30, A second contact 32, a source line 34, and / or a bit line 36. In an embodiment, the extended body region 27 may be disposed under the word line 21 and extend from one side of the floating body region 18 to serve as an additional charge accumulation region. In an embodiment, the extended body region 27 can improve the charge retention capability of a capacitor-free memory.

16B shows a cross-sectional view of a memory cell cut along a line I-I 'in FIG. 16A. As shown in FIG. 16B, a memory cell structure includes a substrate 10, an insulating layer 12, (Emitter / source E / S), a second node 16 (e.g., collector / drain C / D), and a floating body region 18. The memory cell may further include isolation layers 44 adjacent the first node 14 and the second node 16. [ The memory cell includes a gate 21 including a first contact 30 and a source line 34, a second contact 48 and a bit line 36, a gate insulating layer 20 and a gate layer 22, And insulating layers 42 and 46. [ As shown in Fig. 16B, L1 is larger than L2, and the extended body region 27 is not shown in Fig. 16B.

16C is a sectional view of the memory cell taken along the line II-II 'in FIG. 16A. FIG. 16C is a cross-sectional view of the memory cell taken along line II-II' ), Isolation layers 44, gate 21, insulating layers 42 and 46, and bit line 36, and extended body region 27 is shown as an extension of floating body region 18, Respectively.

The extended body region 27 of Figs. 16A-16C can be used in combination with all or a portion of the features described in Figs. 11A-C.

Additionally, as shown in FIG. 17, a hole reservoir 140 may be formed below the floating body region 18. The hole reservoir 140 may be buried in the insulating layer 12. The hole reservoir 140 may have a valence band higher than that of silicon (Si). For example, the hole reservoir 140 may include one of Ge, Si-Ge, Al-Sb, and Ga-Sb. Since the valence electron band of the hole reservoir 140 is higher than the valence electron band of silicon, the holes can be more easily accumulated in the hole reservoir 140. The hole retainer 140 can be separated from the emitter / source E / S and the collector / drain C / D, and thus the data retention characteristic can be improved by reducing the junction leakage current. Thus, the capacitorless memory according to the embodiment may have improved data retention characteristics. Further details regarding the hole reservoir can be found in US Application No. 12 / 005,399 filed on December 27, 2007 entitled " Capacitorless Dynamic Semiconductor Memory Device and Method for Manufacturing the Device ".

In addition, typical CMOS technology based on bulk silicon substrates exhibits a fatal short channel effect at gate channel lengths shorter than 40 nm. Due to the limitations of general MOS devices, active research has been conducted in the field of fin field effect transistors (FinFET) devices.

18 shows a memory cell structure according to an embodiment of the present invention. The pin field effect transistor memory cell shown in Fig. 18 is fabricated on the insulating layer 12 on the substrate 10. [ A pin field effect transistor memory cell includes a silicon pattern on an insulating layer 12 having a first node 14, a second node 16, and / or a floating body region 18. The pin field effect transistor memory cell additionally includes a gate insulating layer 20 and a gate 22. The gate 22 surrounds the floating body region 18 and the gate insulating layer 20 and the gate 22 may be in contact with all faces of the floating body region 18 or faces of two or more portions. As shown in Fig. 18, the gate insulating layer 20 and the gate 22 are in contact with the faces of three portions of the floating body region 18.

In the embodiment, there is no overlap between the gate 22 and the first node 14 or the second node 16, as shown in Fig. That is, the gate length L 2 may be shorter than the floating body length L 1, as shown in FIG. 11A. In another embodiment, the gate 22 may be superimposed on one or more of the first node 14 and the second node 16.

Likewise, the buffer region 24 and / or the auxiliary body region 26 shown in the above embodiment can be used in combination with the pin field effect transistor of FIG.

FIG. 19 shows a memory cell structure according to an embodiment of the present invention. The memory cell structure in FIG. 19 has the same structure as the memory cell structure in FIG. Except that the extended body region 27 is provided at the top of the floating body region 18 and at the bottom of the gate structures 20 and 22. The gate structures 20 and 22 surround the floating body region 18 and the extended body region 27. The extended body region 27, which functions as an additional charge storage region, can improve the charge retention capability of the memory device. 18, the memory device may include a buffer region 24 and / or an auxiliary body region 26 between the first node 14 and the second node 16. In this embodiment,

Although embodiments have been described above, these embodiments may be modified in various ways. The modification and / or replacement in combination with Figs. 11A to 19 can be applied to the embodiment shown in Figs. 1A to 10. This specification discloses many different embodiments having many different features, and each of these features can be used in various combinations.

FIG. 20 illustrates a memory system according to an embodiment of the present invention. As shown in FIG. 20, the memory system includes a memory controller 1800 and a capacitorless memory device 1802. In an embodiment, the capacitorless memory device 1802 may be one of the memories described above in FIGS. 4, 7, and 10. In addition, the memory controller 1800 may be included in an integrated circuit, for example, a central processing unit (CPU) or a graphics controller that performs other specific functions.

20, memory controller 1800 provides instructions CMD and address ADDR to memory device 1802 and memory controller 1800 and memory device 1802 provide data (DATA) Exchange in both directions.

The memory controller 1800 may include a register 211 and the memory device 1802 may include a register 221. [ Each of the registers 211 and 221 may store information indicating whether the memory device 1802 is operating in a block refresh mode or a partial refresh mode. In addition, if the memory 1802 is determined to be in the partial refresh mode, each of the registers 211 and 221 may store the number of source lines and bit lines activated at one time in the partial refresh mode.

As shown in FIG. 21, in an embodiment, a capacitorless memory device 1802 includes a plurality of capacitorless memory devices 1802, for example, x memory devices 1802 ₁ to _x ) where x is an integer greater than or equal to one.

In an embodiment, the memory module 1804 includes a register 231, for example, an identification that specifies the casterity CL, the time tRCD (delay time from RAS to CAS), the partial refresh mode or the block refresh mode Information, and / or an EEPROM that stores the number of source lines and / or the number of bit lines refreshed at one time during a partial refresh operation.

In an embodiment, the memory controller 1800 reads the stored value from the register 231 of the memory module 1804 after the memory system is turned on and writes the value read into the register 211 of the memory controller 1800. Accordingly, the mode with the register set (MRS) command to write one or more values to the corresponding memory device (1802 ~ _{1 x),} each register (221 ₁ ~ _x) of the memory module (1804). For example, the memory controller 1800 may provide an MRS instruction to determine one of a block refresh mode and a partial refresh mode, and provide a refresh command in a refresh operation. If the partial refresh mode is determined, the mode register set command may include the number of source lines (or bit lines) that must be activated at one time in the memory device 1801 _{1 -x} during a refresh operation.

The registers 211 in the memory controller 1800 and the registers 221 ₁ to _x in the memory devices 1801 ₁ to _x may be set as part of the initialization process that occurs when the memory system is powered up or reset.

22A shows a general operation timing diagram of a conventional memory system. As shown in FIG. 22A, in accordance with a clock signal CLK, a conventional memory controller sets a row address R-ADDR) to provide an active command (ACT). After time tRCD, the memory controller 1800 generates a write command WR, a column address C-ADDR and write data WD and the memory devices 1801 ₁ - _x generate a row address R-ADDR ) And the column address (C-ADDR). During a read operation from a memory cell connected to the word line activated by the row address R-ADDR, the memory controller 1800 generates a read command RD together with the column address C-ADDR, 1801 ₁ to _x ). If the read command RE is not the same row address, the memory controller 1800 must generate another active command (ACT) for the read command.

FIG. 22B shows an operation timing diagram of the memory system according to FIGS. 20 and 21. As shown in FIG. 22B, the memory controller 1800 does not need to generate the word line activation command ACT. Instead, the memory controller 1800 sets the write command WR together with an address ADDR that includes a row address specifying a word line to be activated and a column address selecting a memory cell having no capacitor connected to the word line to be activated Can be output. The memory cell without the capacitor may be the memory cell of the above-described embodiment.

Additionally, the memory controller 1800 may output the read command RE with an address ADDR including a row address and a column address without an active command ACT. Thus, the memory system according to the embodiment of the present invention does not require time (tRCD) as in conventional memory devices. Thus, it is possible to implement a high-speed operation system than a conventional memory system. In addition, since the memory controller 1800 according to the embodiment of the present invention outputs the row address and the column address at once, the control can be simplified and the implementation can be facilitated. Conventional memory controllers require separate controls to output row and column addresses.

22B, in an embodiment, the memory controller may generate a mode setting register instruction MRS to select one of the block refresh mode and the partial refresh mode, and if the partial refresh mode is selected, The instruction MRS may include the number of source lines SL or bit lines BL activated at one time during the partial refresh operation. The memory controller 1800 may generate a refresh command REF after the mode register setting command MRS.

The above-described modification and / or replacement in combination with Figs. 20 to 22B can be applied to the embodiment shown in Figs. 1A to 10 or 11A to 19. This specification discloses many embodiments with many different features, each of which may be used in combination.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

FIG. 1A shows a capacitorless memory cell of a horizontal structure according to an embodiment of the present invention.

FIG. 1B shows a capacitorless memory cell in a vertical structure according to an embodiment of the present invention.

Fig. 2 shows the equivalent of a capacitorless memory cell according to an embodiment of the present invention.

3 illustrates the DC characteristics of a capacitorless memory cell according to an embodiment of the present invention.

4 illustrates a memory device having a separate source line structure according to an embodiment of the present invention.

5 is an operation timing diagram for explaining the operation for one row of the memory device of FIG.

6 is an operation timing chart for explaining an operation for one cell of the memory device of FIG.

7 shows a memory device having a common source line structure according to an embodiment of the present invention.

8 is an operation timing diagram for explaining the operation for one row of the memory device of FIG.

FIG. 9 is an operation timing chart for explaining the operation for one cell of the memory device of FIG. 7; FIG.

10 shows a memory device according to another embodiment of the present invention.

11A and 11B illustrate the structure of a capacitorless memory cell according to an embodiment of the present invention.

12A and 12B illustrate the structure of a capacitorless memory cell according to an embodiment of the present invention.

13A and 13B show a structure of a memory cell without a capacitor according to an embodiment of the present invention.

14A and 14B illustrate the structure of a capacitor-free memory cell according to an embodiment of the present invention.

15A, 15B, and 15C illustrate the structure of a capacitorless memory cell according to an embodiment of the present invention.

16A shows a plan view of a memory cell structure according to an embodiment of the present invention.

16B is a sectional view taken along the line I-I 'in Fig. 16A.

16C is a sectional view taken along line II-II 'of FIG. 16A.

17 is a cross-sectional view of a capacitorless memory cell according to an embodiment of the present invention.

18 illustrates a memory cell having a fin field effect transistor structure according to an embodiment of the present invention.

19 shows a memory cell having a fin field effect transistor structure according to another embodiment of the present invention.

20 shows a memory system according to an embodiment of the present invention.

21 shows a memory system according to an embodiment of the present invention.

22A shows an operation timing chart of a conventional memory system.

22B shows an operational timing diagram of a memory system according to an embodiment of the present invention.

Claims (56)

A plurality of memory cells, each of the plurality of memory cells having a first node, a second node and a gate node connected to at least one bit line, at least one source line and at least one word line, A memory array having a plurality of memory cells; And And a control unit for controlling to perform a refresh operation in response to a refresh command by selecting one of the at least one source line and the at least one bit line, If the first data is stored in the memory cell connected to the selected line, the first current is caused by the bipolar junction operation, The control unit applies a bit line write voltage to the at least one bit line according to data information, applies a source line write voltage to the at least one source line, and then applies a word line write voltage to the at least one word line The write operation is further performed, Wherein the source line write voltage is greater than the bit line write voltage and the word line write voltage, and Wherein a difference between the source line write voltage and the bit line write voltage causes the bipolar junction operation in accordance with the data information. The memory device of claim 1, wherein if the second data is stored in the memory cell connected to the selected line, no current is caused by the bipolar junction operation. 2. The memory device of claim 1, wherein each of the plurality of memory cells includes a floating body region between the first node and the second node. 4. The memory device of claim 3, wherein the floating body region has a floating body length, the gate has a gate length, and the floating body length is shorter than the gate length. 2. The memory device of claim 1, wherein the number of source lines is equal to the number of word lines. 6. The memory device of claim 5, wherein a difference between a voltage applied to the at least one source line and the at least one bit line and a voltage applied to the at least one word line induces a bipolar junction operation. . The memory device of claim 1, wherein the control unit comprises a row control unit for controlling the at least one source line and the at least one word line, and a column control unit for controlling the at least one bit line. . 2. The memory device of claim 1, wherein the number of source lines is less than the number of bit lines. The memory device according to claim 8, wherein the memory cells adjacent in the bit line direction share one of the at least one source lines, and the control unit performs the refresh operation by further controlling the at least one word line . delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete A plurality of memory cells, each of the plurality of memory cells having a first node, a second node and a gate node connected to at least one bit line, at least one source line and at least one word line, A memory array having a plurality of memory cells; And And a control unit for controlling to perform a refresh operation in response to a refresh command by selecting one of the at least one source line and the at least one bit line, If the first data is stored in the memory cell connected to the selected line, the first current is caused by the bipolar junction operation, Wherein the control unit further performs a read operation by selecting one of the at least one source line without selecting any one of the at least one word lines, Wherein if the first data is stored in a memory cell connected to the selected source line, the first current is caused by the bipolar junction operation. 45. The memory device of claim 44, wherein if a second data is stored in a memory cell connected to the selected memory cell, no second current caused by the bipolar junction operation flows. 45. The memory device of claim 44, wherein the controller applies a source line read voltage to the selected at least one source line and applies a word line hold voltage to at least one word line. 47. The memory device of claim 46, wherein the controller performs a write operation by selecting the at least one source line, the at least one bit line, and the at least one word line. 48. The memory device of claim 47, wherein the controller applies a source line write voltage to the selected at least one source line during a write operation and applies a word line write voltage to the selected at least one word line. . 49. The memory device according to claim 48, wherein the source line read voltage is equal to the source line write voltage. 48. The memory device of claim 47, wherein the controller is configured to perform a refresh operation by selecting at least two source lines and not selecting the at least one word line. 51. The memory device of claim 50, wherein the controller applies a source line refresh voltage to the selected at least one source line during a refresh operation and applies the word line hold voltage to the at least one word line. . 52. The memory device of claim 51, wherein the source line read voltage is equal to the source line write voltage and the source line refresh voltage. The memory device according to claim 51, wherein the control unit performs the write operation, the read operation, and the refresh operation by applying a word line holding voltage and a word line write voltage to at least one word line. 45. The memory device of claim 44, wherein the memory device Wherein the sensing unit is one of a voltage sense amplifier for sensing the first and second currents and a current sense amplifier. delete delete

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