KR20100089683A - Semiconductor memory device comprising capacitor-less dynamic memory cells - Google Patents

Abstract

PURPOSE: A semiconductor memory device including a dynamic memory cell without a capacitor is provided to simplify the structure of a controller for read and/or write operations by applying one fixed level of voltage to a source line. CONSTITUTION: A memory cell array includes a plurality of memory cells with transistors. A transistor includes a floating body which is connected through a plurality of word-lines, a plurality of source-lines, and a plurality of bit-lines. A controller applies a bit-line writing voltage to a selected bit-line from the bit-lines in a write-operating state. The controller applies a second word-line controlling voltage, which is higher than a first word-line controlling voltage, to a selected word-line from the word-lines. The controller stores data in the memory cells by inducing the bipolar junction transistor operation of the memory cells.

Description

Semiconductor memory device comprising capacitor-less dynamic memory cells

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a dynamic memory cell without a capacitor.

A typical memory, for example a dynamic semiconductor memory device (DRAM), has one transistor and one capacitor. However, due to the size of capacitors, especially capacitors, there is a limit to the size reduction of a general memory. Thus, memories have been developed that include a memory cell with one transistor 1T and no capacitor, referred to as "capacitor-less" memories. The 1T DRAM without the capacitor mentioned in may include an electrically floating body.

In general, conventional capacitorless memory utilizes an SOI wafer with silicon on an insulator and accumulates multiple carriers (holes or electrons) in the floating body region, or emits multiple carriers from the floating body region. Identifies data that controls the area voltage. If a majority carrier is accumulated in the floating body region, this state is represented as data "1", and conversely, if a majority carrier is emitted from the floating body region, this state is represented as data "0".

There are two kinds of operation of a general capacitorless memory device. One uses metal oxide semiconductor transistor (MOS) operating characteristics and the other uses bipolar junction transistor (BJT) operating characteristics. In general, it is disclosed that bipolar junction transistor operation has high speed operation and / or better charge retention properties than MOS operation.

It is an object of the present invention to provide a semiconductor memory device having a capacitorless dynamic memory cell for bipolar junction transistor operation.

One aspect of the semiconductor memory device of the present invention for achieving the above object is a plurality of memory cells comprising a transistor having a floating body connected between each of a plurality of word lines, a plurality of source lines and a plurality of bit lines And a bit line write voltage applied to a selected bit line among the bit lines according to data information during a write operation, and controlling a voltage applied to a selected word line among the word lines. A control unit configured to change a voltage from a voltage to a second word line control voltage higher than the first word line control voltage to induce a bipolar junction transistor operation of the memory cell according to the data information, and to store data in the memory cell; The control unit always uses the bit line as the source lines. Characterized in that for supplying a high voltage than the write voltage source line control.

The controller of one embodiment of the semiconductor memory device of the present invention for achieving the above object is to change the voltage applied to the selected word line from the second word line control voltage to the first word line control voltage during the write operation. After that, the voltage of the selected bit line is changed from the bit line write voltage to a data holding voltage higher than the bit line write voltage.

The controller of one embodiment of the semiconductor memory device of the present invention for achieving the above object is characterized by applying the data holding voltage to unselected bit lines of the bit lines during the write operation.

The controller of one embodiment of the semiconductor memory device of the present invention for achieving the above object precharges a selected bit line among the bit lines to a predetermined precharge voltage during a read operation, and selects the selected word line among the word lines. A third word line control voltage higher than the first word line control voltage and lower than the second word line control voltage may be applied for a predetermined time to cause bipolar junction transistor operation of the memory cell to read data.

In one aspect of the semiconductor memory device of the present invention for achieving the above object, the precharge voltage is higher than the bit line write voltage corresponding to the data "1".

Another aspect of the semiconductor memory device of the present invention for achieving the above object is a plurality of memory cells comprising a transistor having a floating body connected between each of a plurality of word lines, a plurality of source lines and a plurality of bit lines And a precharge of a selected bit line of the bit lines to a predetermined precharge voltage during a read operation, and to the selected word line of the word lines than the first word line control voltage for a predetermined time. And a control unit configured to apply a third word line control voltage higher than the second word line control voltage to cause a bipolar junction transistor of the memory cell to read data, wherein the control unit is always connected to the source lines. Supplying a source line control voltage higher than the precharge voltage It is characterized by.

The control unit of the semiconductor memory device of the present invention for achieving the above object is a data holding voltage higher than the precharge voltage to the bit lines before and after the write operation and / or read operation, the first line to the word line; A data hold operation may be performed by applying a word line control voltage to the source lines and applying the source line control voltage to the source lines.

In the semiconductor memory device of the present invention for achieving the above object, the data holding voltage is the same as the source line control voltage.

Therefore, the semiconductor memory device including the capacitor-free dynamic memory cell of the present invention can simplify the configuration of the controller for read and / or write operations by applying only one voltage level fixed to the source line.

Hereinafter, a semiconductor memory device including a dynamic memory cell without a capacitor of the present invention will be described with reference to the accompanying drawings.

1 illustrates the structure of an embodiment of a dynamic memory cell without a capacitor in a horizontal structure. As shown in FIG. 1, a memory cell without a capacitor having a horizontal structure includes a substrate 1, an insulating layer 2 formed on the substrate 1, and a first node 3 formed separately from each other on the insulating layer 2. ) And a floating body region 5 between the second node 4, the separated first node 3 and the second node 4, a gate insulating layer 6 formed on the floating body region 5, and The gate region 7 is formed on the gate insulating layer 6.

The substrate 1 may be a P conductive type or an N conductive type substrate. If the dynamic memory cell is an NMOS transistor, the substrate 1 is a P conductivity type substrate. The insulating layer 2 is an insulator in a silicon on insulator (SOI) arrangement.

In the MOS operation, each of the first node 3 and the second node 4 may be referred to as a source S and a drain D. FIG. In bipolar junction transistor BJT operation, each of first node 3 and second node 4 may be referred to as emitter E and collector C. The first node 3 and the second node 4 may be interchanged with each other. As an example, the first and second nodes 3 and 4 may be of N conductivity type or P conductivity type. If the dynamic memory cell is an NMOS transistor, the first and second nodes 3 and 4 may be of N conductivity type.

The conductivity type of the floating body region 5 may be different from that of the first and second nodes 3 and 4. In an embodiment of an NMOS transistor, the floating body region 5 may be of P conductivity type. Therefore, the bipolar junction transistor BJT shown in FIG. 1 is an NPN conductive bipolar junction transistor. The floating body region 5 is electrically separated from the substrate 1 by the insulating layer 2 and floated. As shown in FIG. 1, the floating body region 5 may have a floating body length L1.

The dynamic memory cell may include a gate structure including a gate insulating layer 6 and a gate 7, and the gate 7 may have a gate length L2. As shown in FIG. 1, a capacitorless dynamic memory cell having a floating body region 5 may be formed on the insulating layer 2 additionally formed on the silicon substrate 1. As described above, the emitter (source) E (S) or collector (drain) C (D) may be changed relative to each other.

In general, L1 represents the distance between emitter (source) E (S) and collector (drain) C (D), and L2 represents the gate length. In an embodiment, L2 is longer than L1. It is commonly used to form emitter (source) (E (S)) and collector (drain) (C (D)) self-alignment technology or lightly doped drain (LDD) technology. Is applied for stabilization.

FIG. 2 shows an equivalent circuit of the dynamic memory cell without the capacitor of FIG. 1. As shown in FIG. 2, the equivalent circuit includes one NMOS transistor (NMOS) and one NPN bipolar junction transistor (NPN). For example, the emitter (source) E (S), collector (drain) C (D) and gate G of FIG. 1 form an NMOS transistor. Similarly, the emitter (source) E (S), collector (drain) C (D) and electrically floating floating body region 5 (floating body region 5) of FIG. May form an NPN-type bipolar junction transistor. As shown in FIG. 2, a coupling capacitor CC is formed between the gate G of the NMOS transistor and the base B of the bipolar junction transistor.

In an embodiment, bipolar junction transistors NPN are used to read and write dynamic memory cells. The bipolar junction transistor NPN generates a bipolar transistor current that is used to write data to a dynamic memory cell or to read the data state of the dynamic memory cell.

Although not shown, in a semiconductor memory device having a dynamic memory cell without a capacitor, the emitter (source) E (S) of the dynamic memory cell shown in FIGS. 1 and 2 is connected to a source line, and a collector (drain) is provided. C (D) is connected to the bit line and gate G is connected to the word line.

3 illustrates an embodiment of a semiconductor memory device of the present invention, and FIG. 3 illustrates a semiconductor memory device including a memory cell array 10, a row controller 20, and a column controller 30.

The function of each of the blocks shown in FIG. 3 is as follows.

The memory cell array 10 includes dynamic memory cells MC11 ˜ MCij without a plurality of capacitors, and each of the dynamic memory cells MC11 ˜ MCij has a corresponding word line WL1 ˜WLi and a source line SL1 ˜. SLi) and bit lines BL1 to BLj. That is, each of the memory cells of the memory cell array 10 writes or reads data in response to signals transmitted to corresponding word lines, source lines, and bit lines.

Each of the row controller 20 and the column controller 30 receives the write command WR, the read command RD, and the address signals ADDR, and receives the word lines WL1 to WLi and the source lines SL1. ~ SLi) and the bit lines BL1 to BLj. That is, the row controller 20 applies a predetermined voltage fixed to the source lines SL1 to SLi, and writes the write command WR, the read command RD, and the address to each of the word lines WL1 to WLi. A predetermined voltage is applied in response to the signals ADDR. The column controller 30 applies a predetermined voltage to each of the bit lines BL1 to BLj in response to the write command WR, the read command RD, and the address signals ADDR, or applies the bit lines BL1 to BL1 to BLj. Precharge the corresponding bit line of BLj) and sense and amplify the data transmitted to the corresponding bit line.

As shown in FIG. 3, the word lines WL1,..., WLi and the source lines SL1,..., SLi may be disposed in the same direction, and the bit lines BL1,..., BLj are word lines. And WL1,..., WLi and the source lines SL1,..., SLi.

As shown in FIG. 3, the row controller 20 selects one of the word lines WL1,..., WLi in response to the write command WR or the read command RD. ) Can be received. In addition, the column controller 30 may receive the address signal ADDR to select one bit line among the bit lines BL1,..., BLj in response to the write command WR or the read command RD. have.

In addition, the column controller 30 may provide data information to the selected bit line during the write operation and receive data information from the selected bit line during the read operation.

In FIG. 3, although the row control unit 20 and the column control unit 30 are illustrated separately, the row control unit 20 and the column control unit 30 may be implemented as one control unit that performs the functions of the two control units.

FIG. 4 is a timing diagram illustrating a write operation of the semiconductor memory device of FIG. 3 according to an embodiment of the present invention, wherein one memory cell is connected to a word line WL1, a source line SL1, and a bit line BL1. When the data is written to the MC11, that is, in response to the address signal ADDR, the row controller 20 selects one word line WL1, and the column controller 30 selects one bit line BL1. It shows the case of selecting. In FIG. 4, BL1 (W "0") denotes the voltage of the selected bit line when the data "0" is written in the memory cell MC11, that is, the voltage of the bit line BL1 connected to the memory cell MC11. W " 1 " is a voltage of the bit line BL1 connected to the memory cell MC11 when the data " 1 " is written to the memory cell MC11, and WL1 is connected to the memory cell MC11 during the write operation. The bit line BL1 connected to the memory cell MC11 and the memory cell MC11 when the voltage of the word line WL1 and iBL1 (W "0") writes data "0" to the memory cell MC11. The bipolar current flowing through the iBL1 (W "1") is transmitted through the memory cell MC11 and the bit line BL1 connected to the memory cell MC11 when the data "1" is written to the memory cell MC11. The flowing bipolar current, BL2 to BLj, voltages of the bit lines BL2 to BLj that are not connected to the memory cells MC11 during the write operation, and SL1 to SLi, the source lines SL1 to SLi during the write operation. The voltage, WL2 ~ WLi are respectively the voltage of the word lines that are not associated with the memory cell (MC11) during the write operation (WL2 ~ WLi).

Referring to FIGS. 1 to 4, a write operation of a semiconductor memory device having a capacitorless dynamic memory cell of the present invention will be described as follows.

In the period T0, the row controller 20 supplies the first word line control voltage (eg, −1 V) to the word lines WL1 to WLi and the source lines SL1 to SLi in order to maintain data. The source line control voltage (for example, 2V) is applied, and the column controller 30 applies a data sustain voltage (for example, 1V) to the bit lines BL1 to BLj.

In the period T1, the column controller 30 applies a first write voltage (for example, 0V) to the selected bit line BL1 if it is desired to write data “1” to the memory cell MC11. If it is desired to write data "0", a second write voltage (for example, 0.5V) is applied to the selected bit line BL1, and the data is not selected to the unselected bit lines BL2 to BLj. The sustain voltage (for example, 1V) is continuously applied.

The row controller 20 may set a voltage applied to the selected word line WL1 to a second word line control voltage higher than the first word line control voltage at the first word line control voltage (for example, −1 V). For example, the first word line control voltage (for example, −1 V) is continuously applied to the unselected word lines WL2 to WLi. The row controller 20 continuously applies the source line control voltage (for example, 2V) to the source lines SL1 to SLi. That is, a rising pulse having a first amplitude is applied to the selected word line WL1. The first amplitude may be a value corresponding to a difference between the first word line control voltage (eg, −1 V) and the second word line control voltage (eg, 0.3 V).

The write operation will be described with reference to FIGS. 1 and 2 as follows.

When data "1" is written to the memory cell MC11, a predetermined first write voltage (for example, 0V) is applied to the bit line BL1, and then a second word is applied to the word line WL1. A line control voltage (e.g., 0.3V) is applied. That is, a rising pulse is applied to the word line WL1.

The rising pulse applied to the word line WL1 is applied to the gate G of the memory cell, and the potential of the floating body region 5 or the base B is increased by the coupling effect of the coupling capacitor CC. This results in a forward bias between emitter (source) E (S) and base B and a reverse bias between base B and collector (drain) C (D). Thus, the bipolar junction transistor NPN is turned on. As a result, irrespective of the data stored in the dynamic memory cell, electrons are transferred from the emitter (source) E (S) to the base B and the collector (drain) C (D) through the floating body region 5. Moving to the junction of, these electrons collide with the silicon barrier at the junction and generate electron-hole pairs. This may be referred to as impact ionization. That is, the bipolar junction transistor NPN is turned on by the rising pulse applied to the gate G through the word line WL1, and the base B and the collector of the dynamic memory cell are independent of data stored in the dynamic memory cell. Impact ionization between the drain) (C (D)) takes place actively to generate electron-hole pairs.

For each electron-hole pair, electrons move from the junction to the collector (drain) C (D), and holes move from the junction to the base B. And more electrons from the emitter (source) E (S) reach the junction between the base B and the collector (drain) C (D) through the floating body region 5. The above-described operation is repeatedly performed, and due to the positive feedback, the multiplication can be large. This may be referred to as "avalanche generation". As a result of the positive feedback, holes are accumulated in the floating body region 5 so that data "1" is written in the memory cell MC11.

That is, when data “1” is written in the memory cell MC11, the first bipolar current i1 is generated in the period T1 through the bit line BL1 connected to the memory cell MC11 and the memory cell MC11. It is caused by the occurrence of avalanche of bipolar junction transistor operation.

If data "0" is written to the memory cell MC11, a predetermined second write voltage (for example, 0.5V) is applied to the bit line BL1, and then to the word line WL1. A third word line control voltage (eg 0V) is applied. That is, a rising pulse is applied to the word line WL1.

Since the second write voltage (for example, 0.5V) is applied to the bit line BL1, the bipolar junction transistor NPN is not turned on even when a rising pulse is applied to the word line WL1, so that the bipolar junction transistor NPN is applied. Avalanche of the floating body region 5 is not induced, and holes in the floating body region 5 are emitted to the bit line BL1 due to the gate coupling effect of the coupling capacitor CC, thereby causing data " 0 " "This is light.

In the period T2, the row controller 20 applies a first word line control voltage (eg, −1 V) to the word line WL1 connected to the memory cell MC11. When data "1" is written to the memory cell MC11, as illustrated in FIG. 4, the bipolar flows through the bit line BL1 connected to the memory cell MC11 and the memory cell MC11 during the period T2. The current iBL1 (W ″ 1 ″) is smaller than the first bipolar current i1 flowing through the bit line BL1 connected to the memory cell MC11 and the memory cell MC11 in the period T1. This is because the body potential decreases as a result of the coupling effect of the coupling capacitor CC.

In the period T3, each of the row control unit 20 and the column control unit 30 applies the first word line control voltage (for example, −1 V) to the word lines WL1 to WLi in the same manner as the period T0. The data holding operation may be performed by applying a source line control voltage (for example, 2V) to the source lines SL1 to SLi and a data holding voltage (for example, 1V) to the bit lines BL1 to BLj. do.

As shown in FIG. 4, the row control unit 20 and the column control unit 30 are sequentially formed into word lines WL1 to WLi and bit lines BL1 to BLj to prevent a malfunction of the semiconductor memory device. It can be configured to apply a control voltage. That is, as shown in the section T1 of FIG. 4, the row control unit 20 and the column control unit 30 sequentially apply the control voltage to the bit line BL1 and the word line WL1, and the section T2. As shown in FIG. 2, the control voltage may be sequentially applied to the word line WL1 and the bit line BL1.

Although FIG. 4 illustrates a case where data is written to one memory cell MC11, at least one or more of memory cells arranged in the same row, that is, memory cells connected to the same word line and the same source line are selected. It is also possible to write data to selected memory cells simultaneously. In this case, the column controller 30 applies the first write voltage or the second write voltage to each of the selected bit lines of the bit lines BL1 to BLj to respectively select the selected bit lines of the bit lines BL1 to BLj. And write data "1" or data "0" to memory cells connected to the memory cell.

In FIG. 4, the data holding voltage applied to the bit line is lower than the source line control voltage applied to the source lines, but the data holding voltage may have the same level as the source line control voltage.

FIG. 5 is a graph illustrating DC characteristics of a dynamic memory cell without a capacitor, wherein the data stored in the memory cell is " 1 " when the gate voltage Vg is -1V and when the gate voltage Vg is -0.5V. Collector for voltage Vds (ce) between collector (drain) C (D) and emitter (source) E (S) in the state and the state where data stored in the memory cell is "0", respectively. It is a graph showing the change of the current Ids (ce) between (drain) C (D) and emitter (source) E (S). In FIG. 5, the solid line is a gate voltage Vg applied to the gate G of the memory cell through the word line, and the first word line control voltage (eg, −1 V) applied to the word line in the data retention operation. In some cases, the dotted line indicates a second word line control voltage (eg, a gate voltage Vg higher than the first word line control voltage and lower than a second word line control voltage (eg, 0.3V) applied during the write operation). For example, -0.5V) is shown, respectively.

As shown in Fig. 5, when the voltage Vds (ce) between the collector (drain) C (D) and the emitter (source) E (S) becomes equal to or greater than the predetermined voltage V1 or V2. A sharp current increase appears. That is, when the voltage Vds (ce) is equal to or higher than a predetermined voltage, holes are introduced into the base B by drain coupling, so that the potential of the base region increases, so that the base B and the emitter (source A forward voltage is applied between (E (S)), which causes impact ionization as described above. Holes flow into the base B by impact ionization, and the bipolar current Ids (ce) increases rapidly due to the above-described avalanche breakdown phenomenon, and the first bipolar current i1 flows through the memory cell. It becomes.

However, when the voltage Vds (ce) between the collector (drain) C (D) and the emitter (source) E (S) is less than or equal to the predetermined voltage V1 or V2, the bipolar transistor NPN. The second bipolar current i2 that is smaller than the first bipolar current i1 flows because the second state remains off. The second bipolar current i2 may be nearly zero.

As shown in Fig. 5, the voltage V1 at which the bipolar junction transistor NPN is turned on when the data "1" is stored in the memory cell is the bipolar junction transistor when the data "0" is stored in the memory cell. NPN is lower than the voltage V2 on. That is, the case where data "1" is stored in the memory cell is lower than the collector (drain) C (D) and the emitter (source) E (S) that are lower than when data "0" is stored. The bipolar junction transistor NPN is turned on at the voltage Vds (ce), so that the bipolar current Ids (ce) becomes large, and the body potential itself is high due to the hole in the floating body region 5. This is because the forward bias between the emitter (source E (S) and base B) is first formed so that the bipolar junction transistor NPN can operate faster than when data " 0 " is stored.

In addition, as shown in FIG. 5, when the gate voltage Vg becomes high, the voltage Vds (ce) between the lower collector (drain) C (D) and the emitter (source) E (S). ), The bipolar junction transistor NPN is turned on to increase the bipolar current Ids (ce), because when the gate voltage Vg increases, the potential of the body, that is, the potential of the base B increases. This is because the bipolar junction transistor NPN can be turned on by the voltage Vds (ce) between the lower collector (drain) C (D) and the emitter (source) E (S). .

FIG. 6 is a timing diagram illustrating an exemplary embodiment of a read operation of the semiconductor memory device of FIG. 3, wherein one is connected to a word line WL1, a source line SL1, and a bit line WL1. The case where data stored in the memory cell MC11 is read is illustrated. In FIG. 6, BL1 denotes a voltage of a selected bit line, that is, a bit line connected to the memory cell MC11, and WL1 denotes a voltage of a selected word line, that is, a word line connected to the memory cell MC11, iBL1 (W ″). 0 ") represents the bipolar current flowing through the memory cell MC11 and the bit line BL1 connected to the memory cell MC11 when the data" 0 "is stored in the memory cell MC11, iBL1 (W" 1 "). Is a bipolar current flowing through the memory cell MC11 and the bit line BL1 connected to the memory cell MC11 when the data “1” is stored in the memory cell MC11, and BL2 to BLj are bit lines that are not selected. That is, voltages of bit lines not connected to the memory cell MC11, SL1 to SLi are voltages of the source lines, and WL2 to WLi are word lines that are not selected, that is, not connected to the memory cell MC11. Indicate the voltage of the word lines, respectively.

An embodiment of a read method of a semiconductor memory device of the present invention will be described with reference to FIGS. 1 to 3, 5, and 6 as follows.

In the period T0, each of the row controller 20 and the column controller 30 receives the first word line control voltage (for example, −1 V) through the word lines WL1 to WLi and the source lines SL1 to. The data holding operation is performed by applying a source line control voltage (for example, 2V) to SLi and a data holding voltage (for example, 1V) to the bit lines BL1 to BLj.

In the period T1, the column controller 30 decodes the input address signal ADDR to select a predetermined precharge voltage (for example, a bit line BL1 connected to the memory cell MC11). , 0V). The precharge voltage may be at the same level as the first write voltage (eg, 0V) for writing data “1”. In addition, the column controller 30 may be configured to apply a data sustain voltage (for example, 1V) to unselected bit lines BL2 to BLj.

In the period T1, the row controller 20 decodes the input address signal ADDR to control the first word line for a predetermined time with a selected word line, that is, a word line WL1 connected to the memory cell MC11. A third word line control voltage (eg, -0.5V) that is higher than the voltage (eg, -1V) and lower than the second word line control voltage (eg, 0.3V) is applied. In addition, the row controller 20 continuously applies the first word line control voltage (eg, −1 V) to the unselected word lines WL2 to WLi, and the source line to the source lines SL1 to SLi. It can be configured to continue to apply a control voltage (eg 2V).

When the data "1" is stored in the memory cell, the voltage V1 at which the bipolar transistor NPN is turned on is the voltage of the source line control voltage (for example, 2V) and the precharge voltage (for example, 0V). Assuming that the memory cell is designed to be substantially equal to the difference (for example, 2V), the operation of the semiconductor memory device of the present invention in the section T1 will be described below with reference to FIG. 5.

When the bit line BL1 is precharged to 0 V, the voltage Vds (ce) between the collector (drain) C (D) and the emitter (source) E (S) of the memory cell MC11 is the source. The value corresponding to the difference between the line control voltage and the precharge voltage is 2V. When data “1” is stored in the memory cell MC11, when the third word line control voltage (for example, −0.5 V) is applied to the word line WL1, the bipolar transistor NPN is turned on and the memory cell MC11 is turned on. ) And a first bipolar current flows through the bit line BL1 connected to the memory cell MC11. However, if data "0" is stored in the memory cell MC11, the bipolar transistor NPN is not turned on even when the third word line control voltage is applied to the word line WL1, and therefore, the memory cell MC11 And a second bipolar current i2 flows through the bit line BL1 connected to the memory cell MC11. As described above, the second bipolar current i2 may be nearly zero.

Thereafter, a sense amplifier (not shown) may sense and amplify the bipolar current flowing through the bit line BL1 to read data stored in the memory cell.

As shown in FIG. 6, when the voltage of the selected word line WL1 becomes the first word line control voltage (for example, −1 V), the memory cell MC11 when data “1” is stored in the memory cell MC11. ) And the bipolar current iBL1 (W "1") flowing to the bit line BL1 connected to the memory cell MC11 is slightly reduced. This will be easily understood with reference to the description of FIG. 4.

In the period T2, each of the row controller 20 and the column controller 30 applies the first word line control voltage (eg, −1 V) to the word lines WL1 to WLi in the same manner as the period T0. The data holding operation may be performed by applying a source line control voltage (for example, 2V) to the source lines SL1 to SLi and a data holding voltage (for example, 1V) to the bit lines BL1 to BLj. do.

In addition, as indicated by a dotted line in the period T1 of FIG. 6, the precharge voltage may be at a level higher than a first write voltage (eg, 0V) for writing data “1”. As shown in FIG. 5, when the third word line control voltage (eg, -0.5V) is slightly higher than the first word line control voltage (eg, -1V), the collector is applied to the word line. Read even if the voltage between (drain) C (D) and emitter (source) E (S) is lower than when the first word line control voltage (e.g., -1V) is applied to the word line This is because the operation can be performed. When the precharge voltage is increased, power consumption can be reduced because the voltage difference between the signal applied to the bit line during the data retention and read operations is reduced.

Although FIG. 6 illustrates a case where data stored in one selected memory cell MC11 is read, two or more memories among memory cells arranged in the same row, that is, memory cells connected to the same word line and the same source line, are illustrated. The cells may be selected to read data stored in the selected memory cells. In this case, the column controller may be configured to precharge the bit lines connected to the selected memory cells with a precharge voltage. In this case, the precharge voltage may be equal to a first write voltage (for example, 0V) applied to the bit line to store data “1”, or may have a level higher than the first write voltage.

6 illustrates a case where the data holding voltage applied to the bit line is lower than the source line control voltage (for example, 2V), the data holding voltage may have the same level as the source line control voltage.

In FIG. 6, a description has been made on the assumption that a current sense amplifier for sensing and amplifying a current flowing through a bit line is used as a sense amplifier. However, in the semiconductor memory device of the present invention, a voltage sense amplifier may be used. In the case of using the voltage sense amplifier, during the read operation, the column controller 30 may precharge the selected bit line to the precharge voltage and then electrically float the selected bit line. Also in this case, the voltage of the selected bit line changes in accordance with the data stored in the memory cell. That is, if data "1" is stored in the memory cell MC11, the voltage of the bit line BL1 gradually increases, and the bipolar current iBL1 (W "1") gradually decreases. If data "0" is stored in the memory cell MC11, the voltage of the bit line BL1 is maintained at the precharge voltage level.

FIG. 7 illustrates a configuration of another embodiment of the semiconductor memory device of the present invention, and unlike the semiconductor memory device of FIG. 4, which shows a separate source line structure, common memory cells share adjacent source lines. Source line structure is shown.

The functions of the memory cell array 11, the row control unit 21, and the column control unit 31 shown in FIG. 7 are the functions of the memory cell array 10, the row control unit 20, and the column control unit 30 described in FIG. 4. Is the same as

As shown in FIG. 7, when the semiconductor memory device having a dynamic memory cell without a capacitor has a common source line structure, the number of source lines can be reduced. Therefore, the layout area of the semiconductor memory device can be reduced.

Although described above with reference to embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that.

Figure 1 illustrates the configuration of one embodiment of a capacitorless dynamic memory cell.

FIG. 2 shows an equivalent circuit diagram of the dynamic memory cell without the capacitor shown in FIG. 1.

Figure 3 illustrates a configuration of one embodiment of a semiconductor memory device having a capacitorless dynamic memory cell of the present invention.

FIG. 4 is an operation timing diagram for describing a write operation of the semiconductor memory device of the present invention shown in FIG. 3.

5 is a graph showing the DC characteristics of a dynamic memory cell without a capacitor.

FIG. 6 illustrates an operation timing diagram for describing an example of a read operation of the semiconductor memory device of the present invention illustrated in FIG. 3.

Figure 7 illustrates a configuration of one embodiment of a semiconductor memory device having a dynamic memory cell without a capacitor of the present invention.

Claims (10)

A memory cell array having a plurality of memory cells including a transistor having a floating body coupled between each of a plurality of word lines, a plurality of source lines, and a plurality of bit lines; And In the write operation, a bit line write voltage is applied to a selected bit line among the bit lines according to data information, and the voltage applied to the selected word line among the word lines is controlled by the first word line control voltage. A control unit configured to change a second word line control voltage higher than a voltage to induce a bipolar junction transistor operation of the memory cell according to the data information, and to store data in the memory cell; And the control unit supplies a source line control voltage higher than the bit line write voltage to the source lines. The method of claim 1, wherein the control unit The voltage applied to the selected word line is changed from the second word line control voltage to the first word line control voltage during the write operation, and then the voltage of the selected bit line is changed from the bit line write voltage to the bit line write. And changing the data retention voltage higher than the voltage. The method of claim 2, And the data holding voltage and the source line control voltage are the same. The method of claim 2, wherein the control unit And applying the data sustain voltage to unselected bit lines among the bit lines during the write operation. The method of claim 1, wherein the control unit During the read operation, the selected bit line of the bit lines is precharged to a predetermined precharge voltage, and the selected word line of the word lines is higher than the first word line control voltage for a predetermined time and the second word line control voltage. And applying a lower third word line control voltage to cause a bipolar junction transistor operation of the memory cell to read data. The method of claim 5, And the precharge voltage is higher than a bit line write voltage corresponding to data " 1 ". The method of claim 4 or 5, wherein the control unit Before and after the write operation and the read operation, the data holding voltage is applied to the bit lines, the first word line control voltage is applied to the word lines, and the source line control voltage is applied to the source lines. The semiconductor memory device, characterized in that for performing. A memory cell array having a plurality of memory cells including a transistor having a floating body coupled between each of a plurality of word lines, a plurality of source lines, and a plurality of bit lines; And During the read operation, the selected bit line of the bit lines is precharged to a predetermined precharge voltage, and the selected word line of the word lines is higher than the first word line control voltage for a predetermined time and the second word line control voltage. A control unit which applies a lower third word line control voltage to induce bipolar junction transistor operation of the memory cell to read data; And the controller supplies a source line control voltage higher than the precharge voltage to the source lines at all times. The method of claim 8, wherein the control unit Before and after the read operation, the data holding voltage higher than the precharge voltage is applied to the bit lines, the first word line control voltage is applied to the word lines, and the source line control voltage is applied to the source lines. And a sustain operation. 10. The method of claim 9, And the data retention voltage is the same as the source line control voltage.

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