KR20090009699A - Semiconductor memory device comprising capacitor-less dynamic memory cells, dynamic memory cell for the same, and memory system comprising the same - Google Patents

Abstract

A semiconductor memory device including capacitor-less dynamic memory cell, a dynamic memory cell for the same, and a memory system including the same are provided to reduce refresh operation time by supplying refresh control signals to all bit lines and all source lines at the same time. A memory cell array(50) writes/reads data 1 or data 0. A row control part(52) selects memory cells by controlling word lines(WL1-WLi) and source lines(SL1-SLi) in response to write signals(WR)/read signals(RD) and address signals(ADD), and refreshes the memory cells by controlling the source lines in response to refresh orders(REF). A column control part(54) prevents write/read operation of data in non-selected memory cells by controlling the bit lines in response to the write signals/the read signals and the address signals, writes/reads data 1 or data 0 from the selected memory cell, and refreshes the memory cells by controlling the bit lines(BL1-BLj) in response to the refresh orders.

Description

Semiconductor memory device comprising capacitor-less dynamic memory cells, dynamic memory cell for the same, and memory system comprising the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a capacitorless dynamic memory cell, a dynamic memory cell for the device, and a memory system having the device.

A memory cell of a typical dynamic semiconductor memory device is composed of one cell capacitor and one access transistor.

Efforts have been made to continuously increase the capacity of semiconductor memory devices without increasing the layout area. However, there is a limit in increasing capacity without increasing layout area by using memory cells of a general dynamic semiconductor memory device.

Therefore, recently, a dynamic memory cell having a floating body transistor without a capacitor has been introduced, and thus, it is possible to integrate a larger number of memory cells in the same area as compared to memory cells of a general dynamic semiconductor memory device.

However, a dynamic memory cell having a floating body transistor without a capacitor accumulates charges in the floating body, and charges accumulated in the floating body, like a typical dynamic memory cell, lose their charge after a certain time.

Therefore, the performance of a dynamic memory cell having a capacitorless floating body transistor is to increase the charge retention time and to allow read and write operations to be performed at high speed.

The technique disclosed in U.S. Patent Publication No. 2007/0058427 discloses a memory cell array that writes and reads data using bipolar junction transistor operation, but the technique disclosed herein is complicated to control for write and read operation. Do.

An object of the present invention is to provide a semiconductor memory device having an easy-to-control capacitor-free dynamic memory cell for bipolar junction transistor operation.

It is another object of the present invention to provide a dynamic memory cell having a capacitorless floating body that can increase data retention time and improve bipolar junction transistor operation to improve operation speed.

Another object of the present invention is to provide a memory system having a semiconductor memory device for achieving the above object.

A semiconductor memory device of the present invention for achieving the above object comprises a plurality of memory cells having a transistor having a floating body connected between each of a plurality of word lines, a plurality of source lines and a plurality of bit lines Applying a first write control signal to a memory cell array and at least one of said source line and at least one said word line in a first period during a write operation, a read control signal during a read operation, and a refresh operation. And a control unit for applying a refresh control signal to at least one of the bit lines or at least two of the source lines, wherein a voltage corresponding to a first data state is applied to the bit lines in the first period during the write operation. When applied, a first bipolar current flows through the selected at least one memory cell, respectively. If the first data state is stored in the selected at least one memory cell during a read operation, a second bipolar current flows, and the first data state is stored in the selected at least one memory cell during the refresh operation. If so, the third bipolar current flows.

The control unit may apply a data retention control signal to each of the plurality of word lines and the plurality of source lines during a data holding operation.

The semiconductor memory device may read data by sensing a current flowing through the bit line during the read operation, or read data by sensing a voltage of the bit line.

The controller may apply a write and read prohibition control signal to a bit line of at least one memory cell which is unselected during the write operation and the read operation.

In an embodiment, the memory cell array may include the plurality of word lines and the plurality of source lines in the same direction, and the plurality of bit lines may be disposed in a direction orthogonal to the plurality of word lines. Drains of the two floating body transistors adjacent in a line direction are commonly connected, a source and a gate of the floating body transistors arranged in the word line direction are respectively commonly connected, and the source of the transistor having the floating body is Connected to a corresponding one of a plurality of source lines, the gate connected to a corresponding one of the plurality of word lines, and the drain connected to a corresponding one of the plurality of bit lines. It features.

In one embodiment, the control unit applies a second write control signal to the at least one source line and the at least one word line in a second period during the write operation, and in the second period during the write operation. The second bipolar current is characterized by flowing. After the data is applied to the plurality of bit lines, the controller sequentially applies the first write control signal to each of the at least one source line and the at least one word line, and then performs a second operation during the write operation. And sequentially applying the second write control signal to the at least one word line and the at least one source line in the period and to apply data to the plurality of bit lines.

The first write control signal includes a signal having a first voltage applied to the at least one source line and a signal having a second voltage lower than the first voltage applied to the at least one word line. The two-light control signal may include a signal having the first voltage applied to the at least one source line and a signal having a third voltage lower than the second voltage applied to the at least one word line. . The read control signal may include a signal having the first voltage applied to the at least one source line and a signal having the third voltage applied to the at least one word line. The signal includes a signal having the second voltage applied to the plurality of source lines, a signal of the third voltage applied to the plurality of word lines, and the second voltage applied to the plurality of bit lines. Characterized in that it comprises a signal having.

The refresh control signal may include a signal having the second voltage and a signal having the third voltage applied to each of the plurality of source lines and the plurality of word lines, and the at least one of the plurality of bit lines. Or a signal having the first voltage sequentially applied to the bit lines, or the second applied to the plurality of source lines, the plurality of word lines, and the plurality of bit lines, respectively. And a signal having a voltage, a signal having the third voltage, and a signal having the first voltage. Alternatively, the refresh control signal may include a signal having the second voltage and a signal having the third voltage applied to each of the plurality of bit lines and the plurality of word lines, and the at least one of the plurality of source lines. Or the refresh control signal comprises the plurality of bit lines, the plurality of word lines, and the plurality of source lines. And a signal having the second voltage applied to each of them, a signal having the third voltage, and a signal having the first voltage.

The memory cell array may include a plurality of memory cell array blocks, and the refresh control signal may include the plurality of source lines, the plurality of word lines, and the plurality of bit lines of each of the plurality of memory cell array blocks. Or a signal having the second voltage, a signal having the third voltage, and a signal having the first voltage, respectively, or the plurality of bit lines of each of the plurality of memory cell array blocks. For example, a signal having the second voltage, a signal having the third voltage, and a signal having the first voltage may be applied to each of the plurality of word lines and the plurality of source lines.

The controller is a bit line of at least one memory cell that is unselected during the read operation and the first period and the second period during the write operation, and a signal having a fourth voltage lower than the first voltage and higher than the second voltage. Characterized in that the application.

In another aspect, the memory cell array may include the plurality of word lines and the plurality of source lines in the same direction, and the plurality of bit lines may be disposed in a direction orthogonal to the plurality of word lines. A drain and a source of the floating body transistors adjacent in a line direction are respectively connected in common, a source and a gate of the floating body transistors arranged in the word line direction are respectively connected in common, and the source of the transistor having the floating body is A gate is connected to a corresponding one of a plurality of source lines, the gate is connected to a corresponding one of the plurality of word lines, and the drain is connected to a corresponding one of the plurality of bit lines. It is done.

In another embodiment, after the data is applied to the plurality of bit lines, the controller sequentially applies the first write control signal to each of the at least one source line and the at least one word line, and the at least one And sequentially terminating the first write control signal applied to the word line and the at least one source line, and ending the application of data to the plurality of bit lines.

The first write control signal includes a signal having a first voltage applied to the at least one source line and a signal having a second voltage lower than the first voltage applied to the at least one word line. The control signal includes a signal having the first voltage applied to the at least one source line and a signal having a third voltage lower than the second voltage applied to the at least one word line, and the data retention control signal. Is a signal having the first voltage applied to the plurality of source lines, a signal having a fourth voltage lower than the third voltage applied to the plurality of word lines, and the plurality of bit lines. And a signal having the second voltage.

The refresh control signal may include a signal having the second voltage and a signal having the fourth voltage applied to each of the plurality of source lines and the plurality of word lines, and at least one of the plurality of bit lines. Or a signal having the first voltage sequentially applied to the bit lines, or the second applied to the plurality of source lines, the plurality of word lines, and the plurality of bit lines, respectively. And a signal having a voltage, a signal having the fourth voltage, and a signal having the first voltage. Alternatively, the refresh control signal may include a signal having the second voltage and a signal having the fourth voltage applied to each of the plurality of bit lines and the plurality of word lines, and the at least one of the plurality of source lines. Or a signal having the first voltage sequentially applied to two source lines, or applied to each of the plurality of bit lines, the plurality of word lines, and the plurality of source lines. And a signal having the second voltage, a signal having the fourth voltage, and a signal having the first voltage.

The memory cell array may include a plurality of memory cell array blocks, and the refresh control signal may include the plurality of source lines, the plurality of word lines, and the plurality of bits of each of the plurality of memory cell array blocks. A signal having the second voltage applied to each of the lines, a signal having the fourth voltage, and a signal having the first voltage, or the plurality of each of the plurality of memory cell array blocks. And a signal having the second voltage, a signal having the fourth voltage, and a signal having the first voltage applied to bit lines, the plurality of word lines, and the plurality of source lines, respectively. do.

The controller may be configured to apply a signal having a fourth voltage lower than the first voltage and higher than the second voltage to the bit line of the at least one memory cell that is unselected during the write operation and the read operation. It features.

According to one or more embodiments of the present invention, there is provided a capacitorless dynamic memory cell including a semiconductor pattern provided in the form of a floating body on a substrate, and a second conductive material different from the first conductive type in the semiconductor pattern. First and second impurity regions provided to have a shape and spaced apart from each other, a first body region of the first conductive type provided in the semiconductor pattern between the first and second impurity regions, and the first body region And a gate pattern of the first conductivity type provided on and having a width smaller than that of the first body region.

The first conductivity type may be p-type, the second conductivity type may be n-type, the first impurity region may be an emitter of a bipolar junction transistor, and the second impurity region may be a collector of a bipolar junction transistor. .

The dynamic memory cell may further include an extended semiconductor pattern extending from at least one sidewall of both sidewalls of the first body region and having the first conductivity type.

In a first aspect, the dynamic memory cell is characterized in that the gate pattern and the semiconductor pattern do not overlap each other.

In a second aspect, the dynamic memory cell further includes a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region. And the gate pattern overlaps the first body region and the second body region and extends to overlap a portion of the first impurity region and a portion of the second impurity region so that the width of the gate pattern is the first body region. And a width greater than the sum of the widths of the second body regions. The second body region has a lower impurity concentration than the first body region.

In a third aspect, the dynamic memory cell further includes a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region. The gate pattern extends to overlap a portion of the first impurity region, and the gate pattern does not overlap the second impurity region. The second body region has a lower impurity concentration than the first body region.

In a fourth aspect, the dynamic memory cell may further include a buffer region interposed between the first body region and the second impurity region, and the gate pattern may include a portion of the first impurity region and a portion of the buffer region. And the buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a second conductivity type. The impurity concentration is lower than that of the impurity region.

In a fifth aspect, the dynamic memory cell further includes a buffer region interposed between the first body region and the second impurity region, wherein the gate pattern overlaps a portion of the first impurity region, and the buffer region. It is characterized in that it is formed so as not to overlap. The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. It is characterized by having.

In another embodiment of the present invention, a capacitorless dynamic memory cell having a vertical structure is provided on a semiconductor pattern provided on a substrate of a first conductivity type, and provided in a lower region of the semiconductor pattern. The first impurity region having another second conductivity type, the second impurity region of the second conductivity type provided in the upper region of the semiconductor pattern, the semiconductor pattern provided between the first impurity region and the second impurity region And a first conductive type gate pattern provided on the first body region of the first conductive type and a sidewall of the first body region and having a width smaller than that of the first body region.

The first conductivity type may be p-type, the second conductivity type may be n-type, the first impurity region may be an emitter of a bipolar junction transistor, and the second impurity region may be a collector of a bipolar junction transistor.

In a first aspect, the gate pattern, the first impurity region and the second impurity region do not overlap each other.

In a second aspect, the dynamic memory cell further includes a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region. And the gate pattern overlaps the first body region and the second body region and extends to overlap a portion of the first impurity region and a portion of the second impurity region so that the width of the gate pattern is the first body region. And a width greater than the sum of the widths of the second body region, wherein the second body region has a lower impurity concentration than the first body region.

In a third aspect, the dynamic memory cell further includes a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region. And the gate pattern extends to overlap with a portion of the first impurity region, and the gate pattern does not overlap with the second impurity region, wherein the second body region is a lower impurity than the first body region. It is characterized by having a concentration.

In a fourth aspect, the dynamic memory cell may further include a buffer region interposed between the first body region and the second impurity region, and the gate pattern may include a portion of the first impurity region and a portion of the buffer region. The buffer region is extended to overlap, and the buffer region has the same conductivity type as that of the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and is less than the second impurity region. It is characterized by having a low impurity concentration.

In a fifth aspect, the dynamic memory cell further includes a buffer region interposed between the first body region and the second impurity region, wherein the gate pattern overlaps a portion of the first impurity region, and the buffer region. And the buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region. It is characterized by having a lower impurity concentration than the second impurity region.

According to another aspect of the present invention, a memory system of the present invention transmits an address signal including a row address and a column address and write data together with the write command if the command signal is a write command. And a control unit which transmits the address signal including the row address and the column address together and receives read data, and receives the command signal, the address signal and the write data, and transmits the read data. And a memory cell array having a plurality of memory cells including a transistor having a floating body connected between each of the plurality of word lines, the plurality of source lines, and the plurality of bit lines. It is done.

The semiconductor memory device applies a first write control signal to the column address in a first period during a write operation to the at least one source line and at least one word line corresponding to the row address when the write command is applied. The write data is transmitted to at least one corresponding bit line, and if the read command, the read control signal is applied to at least one source line corresponding to the row address, and the at least one bit line corresponding to the column address. Data is transmitted as the read data, and when a voltage corresponding to a first data state is applied to the bit line in the first period during the write operation, a first bipolar current flows through the selected at least one memory cell, respectively. At least one of the selected at the read operation If the first data state stored in a memory cell characterized in that the second bipolar current flows.

The controller applies the refresh command when the command signal is a refresh command, and applies the refresh control signal to the at least one bit line or the at least two source lines when the refresh command is applied. When the first data state is stored in the selected at least one memory cell, a third bipolar current flows.

The semiconductor memory device may apply a data holding control signal to each of the plurality of word lines and the plurality of source lines during a data holding operation for holding data stored in the plurality of memory cells.

In one aspect, the semiconductor memory device applies a second write control signal to the at least one source line and the at least one word line in a second period during the write operation, and the second period during the write operation. And the second bipolar current flows in the semiconductor memory device, and after the data is applied to the plurality of bit lines, the first write to each of the at least one source line and the at least one word line. A control signal is sequentially applied, and the second write control signal is sequentially applied to the at least one word line and the at least one source line in a second period during the write operation, and data is transmitted to the plurality of bit lines. Characterized in that the termination of the application.

The semiconductor memory device may apply a write and read prohibition control signal to a bit line of at least one memory cell that is unselected during the first and second periods of the write operation and the read operation.

In another aspect, the semiconductor memory device sequentially applies the first write control signal to each of the at least one source line and the at least one word line after data is applied to the plurality of bit lines. After sequentially terminating the first write control signal applied to at least one word line and the at least one source line, the data is applied to the plurality of bit lines.

The semiconductor memory device may apply a write and read prohibition control signal to a bit line of at least one memory cell that is unselected during the first period and the read operation during the write operation.

The semiconductor memory device having the capacitor-free dynamic memory cell of the present invention can easily control the operation of the bipolar junction transistor, and in particular, the refresh operation can be easily performed by controlling at least one bit line or at least two source lines during the refresh operation. It is possible to carry out. In addition, it is possible to simultaneously apply the refresh control signal to all the bit lines and all the source lines for every memory cell, each memory cell array block, or every memory cell array bank, thereby simultaneously performing a refresh operation. The refresh operation time is reduced.

In addition, in the dynamic memory cell for the semiconductor memory device of the present invention, since the gate pattern, the first impurity region and the second impurity region are not overlapped with each other, the sensing margin is increased and the generation of the gate induced drain leakage current is reduced. As a result, data read errors are reduced. The addition of the extended semiconductor pattern increases the charge retention time, which results in a longer refresh cycle. In addition, the bipolar junction transistor may be more smoothly operated due to the addition of the buffer region or the second body region.

The memory system including the semiconductor memory device of the present invention does not require a separate command signal for transmitting a row address, and a semiconductor memory because a row address and a column address may be simultaneously transferred during a write command and a read command. The control of the control unit controlling the device is simplified.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a semiconductor memory device of the present invention, a memory cell for the device, and a memory system having the device, the dynamic memory cell without a general capacitor will be described with reference to the accompanying drawings.

1A and 1B illustrate an example of a configuration of a dynamic memory cell without a general capacitor, in which FIG. 1A illustrates a memory cell having a floating body transistor having a horizontal structure, and FIG. 1B illustrates a memory cell having a floating body transistor having a vertical structure. Indicates.

In FIG. 1A, a memory cell having a floating body having a horizontal structure includes a substrate 10, an insulating layer 12 formed on the substrate 10, and a first conductive emitter formed separately from each other on the insulating layer 12. The second conductivity type different from the first conductivity type between the (source) region 14 and the collector (drain) region 16, the separated emitter (source) region 14 and the collector (drain) region 16. And a floating body region 18, an insulating layer 20 formed on the floating body region 18, and a gate region 22 of the second conductive type formed on the insulating layer 20. That is, the second conductive semiconductor pattern may be provided on the substrate 10 in the form of a floating body, the substrate 10 may be a p-type silicon substrate, and the semiconductor pattern may be formed of a semiconductor material such as silicon. The second conductivity type may be p-type. An emitter (source) region 14 which is a first impurity region and a collector (drain) region 16 which is a second impurity region are provided in the semiconductor pattern, and the first impurity region and the second impurity region are the second conductive type. The first conductivity type may be different from that of the first conductivity type. In addition, a gate pattern may be provided on the semiconductor pattern, and the gate pattern may include an insulating layer 20 and a gate region 22 that are sequentially stacked. The emitter (source) region 14, the collector (drain) region 16, and the gate pattern partially overlap so that the length L2 of the gate region 22 is wider than the length L1 of the floating body region 18.

In FIG. 1B, a dynamic memory cell having a floating body transistor having a vertical structure includes a substrate 10, an emitter (source) region 14 of a first conductive type formed on the substrate 10, and an emitter of a first conductive type ( Floating body region 18 of the second conductive type different from the first conductive type formed on the source) region 14, collector (drain) region 16 of the first conductive type formed on the floating body region 18, The insulating layer 20 formed on the sidewall of the floating body region 18 and the gate region 22 of the second conductive type formed on the insulating layer 20 are formed. That is, the semiconductor pattern may be provided on the substrate of the first conductive type, the substrate 10 may be a p-type silicon substrate, the semiconductor pattern may be formed of a semiconductor material such as silicon, and the second conductive type may be It may be p-type. An emitter (source) region 14 which is a first impurity region formed in the lower region of the semiconductor pattern and a collector (drain) region 16 which is a second impurity region formed in the upper region of the semiconductor pattern are provided, and the first impurity region is provided. The second impurity region may be a first conductive type different from the second conductive type, and the first conductive type may be n-type. In addition, a gate pattern may be provided while surrounding the floating body region 18 of the semiconductor pattern, and the gate pattern may include an insulating layer 20 and a gate region 22 that are sequentially stacked. The emitter (source) region 14, the collector (drain) region 16, and the gate pattern partially overlap so that the length L2 of the gate region 22 is wider than the length L1 of the floating body region 18.

FIG. 2 shows an equivalent diagram of a dynamic memory cell having the floating body transistors shown in FIGS. 1A and 1B, wherein an NMOS field effect transistor (NMOS) (hereinafter referred to as an NMOS transistor) and an NPN bipolar junction transistor (NPN) NPN transistor). The source (S) of the NMOS transistor (NMOS) and the emitter (E) of the NPN transistor (NPN) are shared, the drain (D) of the NMOS transistor (NMOS) and the collector (C) of the NPN transistor (NPN) are shared. The base B of the NPN transistor NPN is electrically floating. A coupling capacitor CC is present between the gate G and the base B of the NMOS transistor.

In Figs. 1A, 2B and 2, the collector (drain) and emitter (source) of the floating body transistor are not fixed, but the higher voltage becomes collector (drain) during operation, and the lower voltage emie Become a source.

3 is a graph showing DC characteristics of an embodiment of a dynamic memory cell having a floating body transistor of the present invention, in which the data "1" state and the data "0" state when the gate voltage Vg is 0V and -1V, respectively. It is a graph showing the change of the current Ids (ce) between the collector (drain) and the emitter (source) with respect to the voltage Vds (ce) between the collector (drain) and the emitter (source) of the in transistor.

In FIG. 3, the data "1" state refers to a state in which a large number of carriers, i.e., NMOS transistors, are accumulated in the floating body region 18 in comparison with the data "0" state. The "state" refers to a state in which a small number of minority carriers, that is, electrons, are accumulated in the floating body region 18 in comparison with the data "1" state.

From the graph of Fig. 3, when the gate voltage Vg is 0V, the voltage between the drain (collector) and the source (emitter) (regardless of whether the floating body transistor is in the data "1" state or the data "0" state) It can be seen that there is a sudden increase in current before Vds (ce)) becomes 2V or more, that is, between 1.5V and 2V.

This rapid increase in current is initially caused by drain coupling when the voltage difference (Vds (ce)) between the drain (collector) and the source (emitter) is above a certain voltage between 1.5V and 2V. The base B flows into the base B, and the potential of the base region increases, and a forward voltage is applied between the base B and the emitter E, whereby the emitter current starts to flow. A large portion of the emitter current flows to the collector C, which passes through the band bending region between the base B and the collector C, and then band-to-band tunneling. to-band tunneling) and / or impact ionization. Holes generated by band-to-band tunneling and / or impact ionization are injected from the collector C into the base B, thereby increasing the potential of the base B again. As such, when the voltage Vds (ce) between the drain and the source increases and the NPN transistor is turned on, the bipolar current Ids (ce) is rapidly generated by the forward feedback system of the NPN transistor itself. In addition, when the multiplication factor due to impact ionization is large enough, the bipolar current Ids (ce) increases rapidly due to the avalanche breakdown phenomenon. By this bipolar current Ids (ce), the data " 1 " state in which holes are accumulated in the floating body is written. When the floating body transistor is in the data "1" state, the voltage Vds (ce) between the drain (collector) and the source (emitter) is lower than that of the data "0" state (Vds). At (ce)), the NPN transistor is turned on, resulting in a large bipolar current (Ids (ce)), because the forward potential between the emitter and the base is high because the body potential itself is formed by holes in the floating body 18. This is because it is formed first and can operate faster than when the NPN transistor is in the data " 0 " state.

In FIG. 3, when the gate voltage Vg is -1V, the voltage Vds (ce) between the drain (collector) and the source (emitter) is relatively higher than when the gate voltage Vg is 0V. The bipolar current increases sharply at. Because the lower the gate voltage (Vg), the lower the potential of the base, the higher the voltage (Vds (ce)) between the drain (collector) and the source (emitter). Tunneling and / or impact ionization allow the NPN transistor to be turned on.

FIG. 4 shows a configuration of an embodiment of a semiconductor memory device of the present invention, which is comprised of a memory cell array 50, a row control unit 52, and a column control unit 54, wherein the memory cell array 50 includes i elements. Word lines WL1, WL2, ..., WL (i-1), WLi, j bit lines BL1, BL2, ..., BLj, and i source lines SL1, SL2, ..., and memory cells MC1, MC2, ..., MCi-1, MCi having a gate, a drain, a source, and a floating body connected to each of SL (i-1) and SLi. In FIG. 4, the row controller 52 and the column controller 54 may be configured as one controller.

Word lines WL1, WL2,..., WL (i-1), WLi of the memory cell array 50 and source lines SL1, SL2,..., SL (i-1), SLi. These lines are arranged in the same direction, and the bit lines BL1, BL2, ..., BLj are arranged in a direction orthogonal to the word line. The gates of the memory cells MC1, MC2,..., And MCi of the memory cell array 50 are connected to corresponding word lines WL1, WL2,..., WL (i-1), and WLi. Each first node is connected to the corresponding source lines SL1, SL2,..., SL (i-1), and SLi, and the second node of two adjacent memory cells MC is common. It is connected to the corresponding bit lines.

The function of each of the blocks shown in FIG. 4 is as follows.

The memory cell array 50 includes one word line selected from among the word lines WL1, WL2,..., WL (i-1) and WLi, and source lines SL1, SL2,..., SL (i -1) data " 1 " or data by flowing or not flowing a bipolar current through a source line selected from one of SLi, and memory cells selected by bit lines BL1, BL2, ..., BLj. Write / lead "0". The row controller 52 may perform word lines WL1, WL2,..., WL (i-1), and WLi in response to the write signal WR or the read signal RD and the address signal ADD. Memory cells are selected by controlling the operations SL1, SL2,..., SL (i-1), and SLi. In addition, the memory cells are refreshed by controlling the source lines SL1, SL2,..., SL (i-1), and SLi in response to the refresh command REF. The column controller 54 controls the bit lines BL1, BL2,..., BLj in response to the write signal WR or the read signal RD and the address signal ADD so that data is stored in unselected memory cells. Prevents writing and reading, and writes / reads data “1” or data “0” to / from the selected memory cell. In addition, the memory cells may be refreshed by controlling the bit lines BL1, BL2,..., BLj in response to the refresh command REF. The address applied to the row controller 52 is a row address, and the address applied to the column controller 54 is preferably a column address.

In FIG. 4, the refresh command REF may be applied from the outside of the memory device. However, the refresh command REF may be internally counted to refresh the memory cells.

FIG. 5 shows an operation timing diagram for explaining the operation of the embodiment of the semiconductor memory device shown in FIG. 4, in which the solid lines of the voltages and currents related to the bit line are indicated by the data " 0 " The lines indicated by dashed lines indicate the lines associated with the data " 1 " lights, respectively. The timing diagram of FIG. 5 illustrates a timing diagram when data write and read operations are performed for all memory cells connected to one selected word line.

The operation of the semiconductor memory device of the present invention will be described with reference to the timing diagram shown in FIG.

The periods T0, T3, and T5 may be in a data retention period, that is, a precharge or standby state.

First, an operation of writing data "0" into the memory cells MC1 will be described.

In the period T1, the column controller 54 sequentially applies the bit lines BL1 to BLj to have a voltage of 0 V to 0.5 V, and then the row controller 52 goes to 0 V as the source line SL1. A voltage of 2V and a voltage of -1V to 0V are applied to the word line WL1. If data "0" is stored in the memory cell MC1 in the period T0, the voltage Vds (ce) between the drain (collector) and the source (emitter) of the memory cells MC1 is 1.5V. In addition, the coupling capacitor between the gate and the base maintains the data " 0 " state by emitting or not emitting a small number of holes in the floating body of the memory cells MC1. That is, as can be seen from the graph of Fig. 3, the NPN transistor is turned off so that the bipolar current Ids hardly flows. If the data "1" is stored in the memory cells MC1 in the period T0, the voltage Vds (ce) between the drain (collector) and the source (emitter) of the memory cells MC1 is 1.5V. As a result, there is a slight band-to-band tunneling and / or impact ionization between the base and the collector (drain) of the memory cells MC1, so that a small amount of holes may be injected into the floating body, but the coupling capacitor between the gate and the base As more holes are released through the bit line, the memory cells MC1 store data “0”. The time points at which the voltages of the bit lines BL1 to BLj, the source line SL1, and the word line WL1 increase are preferably sequentially formed as shown in the timing diagram.

Next, an operation in the case of writing data "1" into the memory cells MC1 will be described.

In the period T1, the column controller 54 sequentially applies a voltage of 0 V to the bit lines BL1 to BLj, and the row controller 52 applies a voltage of 0 V to 2 V as the source line SL1, a word line. A voltage of -1V to 0V is applied to (WL1). When the voltage Vds (ce) between the drain (collector) and the source (emitter) of the memory cells MC1 becomes 2V and the gate voltage becomes 0V, regardless of the data stored in the memory cells MC1 in the period T0. Therefore, band-to-band tunneling and / or impact ionization between the base and the collector (drain) of the memory cells MC1 is actively performed to increase the injection of holes into the floating body, thereby turning on the NPN transistor to turn on the bipolar current ) Flows and data "1" is written to the memory cells MC1. The time points at which the voltages of the bit lines BL1 to BLj, the source line SL1, and the word line WL1 rise are preferably sequentially formed as shown in the timing diagram.

In the period T2, if the row control section 52 applies a voltage of 0V to -1V, to the word line WL1. In the period T1, a current smaller than the bipolar current flowing through the NMOS transistor flows.

The time points at which the voltages of the word line WL1, the source line SL1, and the bit line BL1 fall are preferably sequentially formed as shown in the timing chart. In the period T2, when the voltage of the source line SL1 first drops to 0V, holes injected into the floating body exit through the bit line and the source line, thereby writing data “1” written in the memory cells MC1. Can't keep up The period T2 is a period necessary for data "1" write, and may proceed to the period T3 without performing the period T2 for data "0" write. However, the timing of the bit lines, the source lines, and the word lines in accordance with the data "1" write operation are not performed because only the data "1" write operation or the data "0" write operation is performed to the memory cell array. It is preferred that this be adjusted. The bipolar current i1 flowing through the memory cells MC1 in the period T2 becomes smaller than the bipolar current i2 in the period T1.

In the period T3, the column controller 54 applies a voltage of 0V to the bit lines BL1 to BLj, and the row controller 52 applies a voltage of 0V to the source line SL1 and a word line WL1. Applying a voltage of -1V turns off the NPN transistor and turns off the NMOS transistor to maintain the charge stored in the floating body.

In the period T4, the row controller 52 applies a voltage of -1V to the word line WL1 and a voltage of 2V to the source line SL1, and the column controller 54 applies a voltage of 0V to the bit line BL1. When the voltage is applied, the voltage Vds between the drain (collector) and the source (emitter) of the memory cells MC1 becomes 2V. As a result, if the data "1" is stored in the memory cells MC1, the NPN The transistor is turned on to flow the bipolar current i1, and if the data "0" is stored, the NPN transistor is turned off so that the bipolar current Ids does not flow. In this period T4, the bipolar current i1 flowing through the memory cells MC1 is smaller than the bipolar current i2 in the period T1. As described above, the data “1” and the data “0” read operations are performed according to the presence or absence of bipolar current according to the data. In addition, in this period T4, the restoration of the data stored in the memory cells MC1 is performed.

In the period T5, the same data retention operation as in the period T3 is performed.

In the period T6, the row control unit 52 applies a voltage of 2V to all the source lines SL1 to SLi at the same time when the refresh period is reached or the refresh command REF is applied, or at least two source lines. Apply a voltage of 2V sequentially. Accordingly, the refresh operation is performed on all the memory cells of the memory cell array at the same time, or the refresh operation is sequentially performed on the memory cells connected to at least two source lines. That is, a refresh operation is performed by applying a voltage capable of turning on the NPN transistor to source lines of the memory cells. The refresh operation is performed in the same manner as the operation in the period T4.

FIG. 6 is an operation timing diagram for explaining the operation of another embodiment of the memory cell array including the floating body transistors shown in FIG. 4, in which signals representing voltages and currents related to bit lines are indicated by solid lines; "A line associated with the light, and a dotted line indicate the line associated with the data" 1 "light, respectively. 6 is a timing diagram when data write and read operations are performed for one memory cell connected between the selected word line and the selected source line.

The operation of the memory cell array of the present invention will be described with reference to the timing diagram shown in FIG.

In the period T1, the operation in the case of writing data " 0 " and data " 1 " to the memory cells MC1 connected to the word line WL1, the source line SL1 and the bit line BL1, is described in the above-mentioned figure. The operation description of 5 will be easily understood. The only difference is that the column controller 54 applies a voltage of 1V to the bit lines BL2 to BLj to prevent data write operations on the memory cells MC1 connected to the bit lines BL2 to BLj. will be. Accordingly, the voltage Vds (ce) between the drain (collector) and the source (emitter) of the memory cells MC1 connected to the bit lines BL2 to BLj becomes 1V, and 0V to the word line WL1. Since a voltage of is applied, data "1" and data "0" writing to the memory cells MC1 connected to the bit lines BL2 to BLj are prevented. That is, if data "1" is written in the memory cells MC1 connected to the bit lines BL2 to BLj, the forward voltage of the NPN transistor is not sufficient, so that the holes accumulated in the floating body do not escape and the data "0". "Write is prevented, and if data" 0 "was written, holes are not injected into the floating body and data" 1 "write is prevented.

In the period T2, in the operation and the period T3 of holding the data " 1 " stored in the memory cell MC1 connected to the word line WL1, the source line SL1 and the bit line BL1, the word line ( The operation of retaining the data " 0 " and the data " 1 " stored in the memory cell MC1 connected to the WL1, the source line SL1 and the bit line BL1 is also easily described with reference to the operation description of FIG. Will be understood.

In the period T4, the operation in the case where data "0" and data "1" are read to the memory cell MC1 connected to the word line WL1, the source line SL1, and the bit line BL1 is described in the above-mentioned figure. The operation description of 5 will be easily understood. The only difference is that the column controller 54 applies a voltage of 1V to the bit lines BL2 to BLj to prevent data write operations on the memory cells MC1 connected to the bit lines BL2 to BLj. will be. The period for which the voltage of 1 V is applied to the bit lines BL2 to BLj is set from before the voltage of 2 V is applied to the source line SL1 until after the application of the voltage of 2 V to the source line SL1 is finished. It is preferable to be. In the period T4, reading of data "0" and data "1" from the memory cells MC1 connected to the bit lines BL2 to BLj is prohibited is the data "0" and the data "1" in the period T1. "It will be easily understood by referring to the explanation of what light is prohibited. In the period T4, it is possible to read data by sensing the current of the bit line or sensing the voltage during the data read operation.

The operation of the period T5 and the period T6 will be easily understood with reference to the operation description of FIG. 5 described above.

Although not shown, the column control unit 54, not the row control unit 52 of the semiconductor memory device shown in FIG. 4, performs a refresh operation by applying a voltage of 2V to the bit lines in response to the refresh command REF. It is also possible. That is, in response to the refresh command REF, a voltage of 2V is applied to all the bit lines BL1 to BLj, or a voltage of 2V is sequentially applied to at least two bit lines, thereby performing a refresh operation on all the memory cells. It is possible to carry out.

In addition, it is also possible to perform a refresh operation on all memory cells by sequentially applying a voltage of 2V to at least one bit line of the semiconductor memory device shown in FIG.

5 and 6, a method of operating a memory cell array having a floating body transistor according to the present invention can control a word line at two voltage levels, a source line at two voltage levels, and operate at a low voltage level. In addition to reducing power consumption, it is possible to perform the refresh operation in a simple manner. In addition, the operation method illustrated in FIG. 6 enables write and read operations only to memory cells connected to a selected word line, a selected source line, and a selected bit line.

Fig. 7 is a graph showing DC characteristics of another embodiment of the floating body transistor of the present invention, in which the transistor is in the data " 1 " state and the data " 0 " state when the gate voltage Vg is 0V, -1V, and -2V, respectively. It is a graph showing the change of the current Ids (ce) between the drain (collector) and the source (emitter) with respect to the voltage Vds (ce) between the drain (collector) and the source (emitter).

As shown in Fig. 3, the data "1" state means a state in which a large number of carriers, that is, holes are relatively accumulated in the floating body region 18, as compared with the data "0" state, and the data "0" state means data. Compared to the " 1 " state, this refers to a state in which a small number of minority carriers, that is, electrons are accumulated in the floating body region 18 relatively.

A description of the case where the gate voltage Vg is 0V and −1V will be easily understood with reference to the description of FIG. 3.

From the graph of FIG. 7, when the gate voltage Vg is -2V, the voltage Vds (ce) between the drain (collector) and the source (emitter) is relative to the case where the gate voltage Vg is -1V. At high voltages, for example, voltages above 2V, the bipolar current increases rapidly, which means that the lower the gate voltage, the lower the potential of the base, and therefore the voltage between the drain (collector) and the source (emitter) (Vds ( ce)) must be large so that the NPN transistor can be turned on by band-to-band tunneling and / or impact ionization. Therefore, when the gate voltage Vg is -2V, when the voltage Vds (ce) between the drain (collector) and the source (emitter) is 2V or less, the memory cell storing data "1" and data "0" Of the NPN transistors are all off.

The structure of the floating body transistor of the present invention is not limited to the structure of the embodiment shown in FIG. 1 and may be in various forms. That is, if the floating body transistor has the circuit configuration modeled in FIG. 2 and has the characteristics of FIG. 7, the floating body transistor may have any structure as long as the floating body transistor has the modeled circuit configuration in FIG.

Fig. 8 shows the construction of another embodiment of the semiconductor memory device of the present invention, which is comprised of a memory cell array 50 ', a row control unit 52' and a column control unit 54 ', and a memory cell array 50'. Denotes i word lines WL1, WL2, ..., WL (i-1), WLi, j bit lines BL1, BL2, ..., BLj, and k source lines SL1. Is composed of memory cells MC1, MC2, ..., MCi-1, MCi having a gate, drain, source, and floating body connected to each of SL2, ..., SL (k-1), SLk. .

8, i word lines WL1, WL2, ..., WL (i-1), WLi and k source lines SL1, SL2, ..., SL of the memory cell array 50 '. (k-1) and SLk are arranged in the same direction, and j bit lines BL1, BL2, ..., BLj are arranged in a direction orthogonal to the word line. The drains (collectors) of the two adjacent memory cells MC are commonly connected to the corresponding bit lines, and the sources (emitters) of the two adjacent memory cells MC are commonly connected to each other. It is connected to the line. Accordingly, if the number of word lines is i, k is disposed, which is about half the number of word lines.

In the memory cell array shown in FIG. 8, the number of source lines is reduced compared to the number of word lines, so that line arrangement is easier than that of the memory cell array shown in FIG.

The functions of the memory cell array 50 ', the row control unit 52' and the column control unit 54 'shown in FIG. 8 are performed by the memory cell array 50, the row control unit 52 and the column control unit 54 shown in FIG. Since it is similar to the function of Figure 5 will be easily understood with reference to the functional description.

FIG. 9 is an operation timing chart for explaining the operation of the embodiment of the semiconductor memory device shown in FIG. 8, wherein solid lines of the timings and voltages related to the bit line are indicated by the line related to the data " 0 " Denoted by a dotted line indicates a line associated with the data " 1 " 9 illustrates a timing diagram when data write and read operations are performed on all of the memory cells connected to one selected word line.

The operation of the semiconductor memory device of the present invention will be described with reference to the timing diagram shown in FIG.

Unlike the timing diagram shown in FIG. 5, the operation timing diagram shown in FIG. 9 differs from that of applying a voltage of 0 V in the period T1 and a voltage of -2 V in the periods T0, T2, and T5 with word lines. This is a word line of non-selected memory cells, unlike-the semiconductor memory device of FIG. 4, because the source lines are not connected to each of the memory cells, but are configured to be shared to adjacent memory cells. This is because the NPN transistors of the non-selected memory cells are all turned off during the write and read operations of the selected memory cells. It can be seen from the characteristic graph of FIG. 3 that when the gate voltage Vg is -2V, all of the memory cells in which data "1" and data "0" are stored are turned off.

The operations of the periods T0 and T1 of FIG. 9 are made the same as the operations of the periods T0 and T1 of FIG. 5, and the operations of the periods T2, T3, T4 and T5 are the periods of FIG. 5. The same operation as in the fields T3, T4, T5, and T6.

FIG. 10 shows an operation timing diagram for explaining the operation of another embodiment of the semiconductor memory device shown in FIG. 8, in which the solid lines of the timings and voltages related to the bit lines are related to the data " 0 " The lines indicated by dotted lines indicate the lines associated with the data "1" lights, respectively. 9 is a timing diagram when data write and read operations are performed on one memory cell connected between the selected word line and the selected source line.

The operation of the semiconductor memory device of the present invention will be described with reference to the timing diagram shown in FIG.

Unlike the timing diagram shown in FIG. 6, the operation timing diagram shown in FIG. 10 differs from that of applying a voltage of 0 V in the period T1 and a voltage of -2 V in the periods T0, T2, and T5 with word lines. This is a word line of non-selected memory cells, unlike-the semiconductor memory device of FIG. 4, because the source lines are not connected to each of the memory cells, but are configured to be shared to adjacent memory cells. This is because the NPN transistors of the non-selected memory cells are all turned off during the write and read operations of the selected memory cells. It can be seen from the characteristic graph of FIG. 3 that the memory cells in which data “1” and data “0” are stored are all turned off when the gate voltage Vg is −2V.

The operation of the periods T0 and T1 of FIG. 10 is the same as the operation of the periods T0 and T1 of FIG. 5, and the operation of the periods T2, T3, T4 and T5 is the period of FIG. 6. The same operation as in the fields T3, T4, T5, and T6.

Although not shown, not the row controller 52 'of the semiconductor memory device shown in FIG. 8, the column controller 54' performs a refresh operation by applying a voltage of 2V to the bit lines in response to the refresh command REF. It is also possible. That is, in response to the refresh command REF, a voltage of 2V is applied to all of the bit lines BL1 to BLj, or a voltage of 2V is sequentially applied to at least two bit lines to refresh all memory cells. It is possible to perform an operation.

In addition, it is also possible to perform a refresh operation on all memory cells by sequentially applying a voltage of 2V to at least one bit line of the semiconductor memory device shown in FIG.

Although not shown, the semiconductor memory device shown in FIGS. 4 and 8 is preferably provided with a sense amplifier for sensing the current or voltage of the bit line. 6 and 10, the semiconductor memory device shown in FIGS. 4 and 8 can read / write data to / from memory cells connected to one selected bit line. It is possible to have the bit lines or a predetermined number of bit lines share one sense amplifier (not shown).

Therefore, the semiconductor memory device shown in FIG. 8 can reduce the layout area because the number of source lines of the memory cell array includes only about half of the number of word lines, and the sense amplifiers do not have to be provided for each bit line. .

9 and 10, a method of operating a memory cell array having a floating body transistor according to the present invention can control a word line at three voltage levels, a source line at two voltage levels, and operate at a low voltage level. In addition to reducing power consumption, it is possible to perform the refresh operation in a simple manner. In addition, the operation method illustrated in FIG. 10 enables write and read operations only to memory cells connected to a selected word line, a selected source line, and a selected bit line.

Fig. 11 is a block diagram showing the construction of still another embodiment of the semiconductor memory device of the present invention, which is comprised of the memory cell array 100, the row control unit 102, and the column control unit 104, and the memory cell array 100 It is composed of memory cell array blocks BK1 to BKn and sensing blocks SA1, SA12,..., SAn. Each of the memory cell array blocks BK1 to BKn may have a configuration shown in FIG. 4 or 7.

The functions of each of the blocks shown in FIG. 11 will be described below.

The memory cell array 100 writes / reads data to / from the selected at least one memory cell array block. The row controller 102 controls one word line by controlling the word lines WL11 to WLni and the source lines SL11 to SLni in response to the write signal WR or the read signal RD and the address signal ADD. Select. In addition, in response to the refresh command REF, the source lines SL11 to SLni are controlled to refresh the connected memory cells. In this case, the source lines SL11 to SLni are controlled to refresh all the memory cells at once, the source lines are controlled by the memory cell array block to perform block-by-block refresh, or at least two source lines are sequentially controlled. The memory cells connected to at least two source lines may be sequentially refreshed to perform refresh on all memory cells. The column controller 104 controls the bit lines BL1 to BLj in response to the write signal WR or the read signal RD and the address signal ADD to prevent data from being written to and read from unselected memory cells. And write / read data "1" or data "0" to / from a memory cell connected to the selected bit line. The address applied to the row control unit 102 is a row address, and the address applied to the column control unit 104 is preferably a column address. Each of the sensing blocks SA1 to SAn applies a voltage corresponding to a write data state to a corresponding bit line, or amplifies and outputs read data of the bit line. Each of the sensing blocks SA1 to SAn includes a current sense amplifier or a voltage sense amplifier to amplify the current difference or the voltage difference of the bit line.

In the case of performing the operations illustrated in FIGS. 5 and 9, each of the sensing blocks SA1 to SAn should be configured to include a sense amplifier for all bit lines, but in the case of performing the operations illustrated in FIGS. 6 and 10. Each sensing block SA1 to SAn may be configured to have one bit for a predetermined number of bit lines smaller than the number of bit lines.

Similar to the semiconductor memory device shown in FIGS. 4 and 8, the column control unit 54 instead of the row control unit 52 of the semiconductor memory device shown in FIG. 11 applies a voltage of 2V to the bit lines in response to the refresh command REF. It is also possible to perform a refresh operation by applying. That is, it is possible to perform the refresh operation on all the memory cells by applying a voltage of 2V to all the bit lines BL1 to BLj in response to the refresh command REF. Even in this case, it is possible to sequentially perform the refresh operations at least one by one without performing the refresh operation on all the bit lines BL1 to BLj.

In addition, in the above-described embodiments, at least two source lines (or at least one bit lines), all source lines (or all bit lines) of the memory cell array block, or all source lines of the memory cell array. Although the refresh operation is performed on the memory cells connected to the (or all of the bit lines) at the same time, all the source lines of the memory cell array bank (or It is also possible to perform a refresh operation on memory cells connected to all bit lines at the same time. Therefore, since it is possible to perform the refresh operation for a large number of memory cells at once, the time required for the refresh operation for all the memory cells is reduced, so that the write operation and the read operation can be performed at a higher speed.

The refresh operation of a semiconductor memory device having a capacitor-free dynamic memory cell of the present invention performs a refresh operation on the memory cells connected thereto by applying a refresh control voltage to a bit line or a source line.

The voltage levels of the above-described embodiment may be applied by substituting other voltage levels at which the operation of the bipolar junction transistor is possible.

In the above-described embodiment, the column controller 54 applies a voltage corresponding to the data state to the bit lines during the write operation. However, other data not shown are not applied to the column controller 54 during the write operation. The voltage corresponding to the data state may be applied to the bit lines through the means.

The dynamic memory cell of the semiconductor memory device of the present invention may have the structure shown in Figs. 1A and B, but the above-described bipolar junction transistor operation can be performed more smoothly, and a floating body transistor capable of increasing data retention time can be obtained. The structure of a preferred embodiment of a memory cell provided is as follows.

12A and 12B show a configuration of a first embodiment of a memory cell having a floating body transistor of the present invention. The floating body transistor of FIG. 12A has an emitter (source) region of the first conductivity type unlike the structure of FIG. 14 and the collector (drain) region 16 have the same structure as that of FIG. 1A except that the gate region 22 of the second conductivity type is not overlapped. Unlike the structure of FIG. 1B, the floating body transistor of FIG. 12B also does not overlap the emitter (source) region 14 and the collector (drain) region 16 of the first conductive type with the gate region 22 of the second conductive type. It is not formed. That is, the semiconductor pattern and the gate pattern are formed so that they do not overlap, and thus the length L2 of the gate region 22 is smaller than the length L1 of the floating body region 18.

Like the FIGS. 1A and 1B, the floating body region 18 may have a second conductivity type. The substrate 10 may be a silicon substrate, the first conductive type may be n type, and the second conductive type may be p type. In addition, the impurity concentration of the emitter (source) region 14 may have a higher impurity concentration than that of the collector (drain) region 16.

In the memory cells shown in FIGS. 12A and 12B, the gate region 22, the emitter (source) region 14, and the collector (drain) region 16 do not overlap, and the gate induced drain leakage current (GIDL) is used. Since the phenomenon is small, the thickness of the insulating layer 20 may be reduced, thereby compensating for the gate base coupling capacitance due to the reduction of the gate pattern.

In addition, the voltage difference of Vds between data " 1 " and data " 0 " for the same gate voltage Vg in the graphs of FIGS. The larger the capacitance between the C and the emitter (source) region 14, the larger the capacitance between the floating body region 18 and the collector (drain) region 16 will be. In the memory cells shown in Figs. 3A and 3B, since the gate region 22, the emitter (source) region 14, and the collector (drain) region 16 do not overlap, the gate region 22 and the emitter (source) region Since the capacitance between (14) and between the gate region 22 and the collector (drain) region 16 becomes small, the gate capacitance becomes small, thereby ensuring a large sensing margin, and thus an error during data read operation. Can be reduced.

Further, the distance between the gate region 22 and the emitter (source) region 14 and the distance between the gate region 22 and the collector (drain) region 16 become farther away, so that the generation of the gate induced drain leakage current occurs. It can be reduced, so that damage to data "0" is reduced.

13A and 13B show a configuration of a second embodiment of a memory cell having a floating body transistor of the present invention. The floating body transistors of FIGS. 13A and 13B are different from the structures of FIGS. A first conductive type or a second conductive type buffer region 24 is formed between the drain) region 16 and the floating body region 18, and the impurity concentration of the buffer region 24 is an emitter of the first conductive type. It may be lower than the impurity concentration of the (source) region 14 or the impurity concentration of the second conductivity type of the floating body region 18.

In addition, the floating body region 18 may have a second conductivity type. The substrate 10 may be a silicon substrate, the first conductive type may be n type, and the second conductive type may be p type. In addition, the impurity concentration of the emitter (source) region 14 may have an impurity concentration higher than that of the collector (drain) region 16.

In the above-described embodiment, the buffer region 24 exists between the floating body region 18 and the collector (drain) region 16, but exists between the emitter (source) region 14 and the floating body region 18. It may be.

The buffer region 18 may be used as an acceleration section of charge moving from the emitter (source) region 14 to the collector (drain) region 16 in the operation of the bipolar junction transistor. In other words, the buffer region 18 increases the mean free path of electrons, thereby increasing the possibility of collision of charges and generation of avalanche multiplication. Accordingly, a large amount of current is generated due to the avalanche breakdown phenomenon, thereby enabling high speed operation.

FIG. 13B is a vertical memory cell structure that minimizes an increase in layout area and has the same effect as the memory cell of FIG. 15A.

13A and 13B show that a portion of the gate region 22 and an emitter (source) region 14 overlap each other, and a portion of the gate region 22 and the buffer region 24 overlap each other. Part 22 of the emitter (source) region 14 overlaps with each other, and the gate region 22 and the buffer region 24 do not overlap, and in this case, it is more preferable that the buffer region is of the first conductivity type. can do.

14A and 14B show the structure of the third embodiment of the memory cell including the floating body transistor of the present invention. The features of FIG. 12 and the features of the structures of FIGS. 13A and 13B are applied together. The emitter (source) region 14 is not overlapped, and the gate region 22 and the buffer region 24 are formed so as not to overlap.

Figures 15a and b show a structure of a fourth embodiment of a memory cell having a floating body transistor of the present invention, wherein the floating body transistors of Figures 15a and b show the emitter (source) region 14 and floating body of Figure 1a. An auxiliary body region 26 of the second conductive type having an impurity concentration different from that of the floating body region 18 of the second conductive type is formed between the regions 18 and the collector (drain) region 16 is formed. An emitter (source) region 14 of the first conductivity type having an impurity concentration higher than the impurity concentration is formed. The impurity concentration of the auxiliary body region 26 may have an impurity concentration lower than that of the floating body region 18.

15A and 15B increase the electron injection efficiency because the secondary body region 26 having a lower impurity concentration than the floating body region 18 increases the number of carriers, that is, electrons, from the emitter to the base. do. Thus, the current gain of the bipolar junction transistor is increased, resulting in more impact ionization and thus faster avalanche breakdown.

Although not shown, the gate region 22 and the emitter (source) region 14 may be configured to overlap each other, and the gate region 22 and the collector (drain) region 16 may be configured not to overlap.

16A, B, and C are plan and cross-sectional views of a structure of a fifth embodiment of a dynamic memory cell having a floating body transistor having a horizontal structure of the present invention, showing an embodiment including a connection of a dynamic memory cell, a source line, and a bit line. To indicate. Fig. 16B is a cross sectional view taken along the line II ′ and Fig. 16C is a cross sectional view taken along the line II-II ′.

Referring to Figures 16A, B, and C, a second portion extending from at least one of the sidewalls of the floating body region 18 between the emitter (source) region 14 and the collector (drain) region 16 A conductive auxiliary body region 26 is additionally formed. The auxiliary body region 26 extends the floating body region 18 and may be a charge storage region. Thus, the charge storage region becomes large, which makes it possible to store a large amount of charge, thereby increasing the charge retention time. Increased charge retention time results in longer refresh cycles.

In addition, the gate region 22 and the auxiliary body region 26 may overlap as illustrated. It may be insulated from the auxiliary body region 26 or the substrate 10. The auxiliary body region 26 is formed by the expansion semiconductor pattern 27, and the emitter (source) region 14, the collector (drain) region 16, and the floating body region 18 are the semiconductor pattern 15. The gate pattern 21 is formed in the semiconductor pattern 15. The gate pattern 21 may include an insulating layer 20 and a gate region 22.

A gate spacer 40 may be provided on the sidewall of the gate pattern 21, and a lower interlayer insulating layer 42 covering the emitter (source) region 14 and the collector (drain) region 16 may be provided. Can be. In addition, a first contact structure 30 penetrating the lower interlayer insulating layer 42 and electrically connected to the emitter (source) region 14 may be provided. The first contact structure 30 may be provided on the lower interlayer insulating layer 42. A source line SL, which is the first conductive line 34 covering the contact structure 30, may be provided.

An upper interlayer insulating layer 46 may be provided on the first conductive line 34 and the lower interlayer insulating layer 42. A second contact structure 48 may be provided that penetrates the upper interlayer insulating film 46 and the lower interlayer insulating film 42 and is electrically connected to the collector (drain) region 16. A bit line BL, which is the second conductive line 36, covering the second contact structure 48 may be provided on the upper interlayer insulating layer 46.

In addition, an isolation region 44 may be provided to surround sidewalls of the semiconductor pattern 15 and the expansion semiconductor pattern 27.

Although FIG. 16B illustrates a cross-sectional view of the dynamic memory cell of FIG. 14A as an example, the extended semiconductor pattern 27 of FIGS. 16A, B, and C may be applied to each of the dynamic memory cells of the above-described embodiments.

The operation method of a semiconductor memory device having a memory cell having a capacitor-free floating body transistor of the present invention is easy to control during operation of a bipolar junction transistor, and the bipolar junction transistor operation is smoothly performed by adopting the structure of the embodiment. As a result, the sensing margin is increased and is suitable for high speed operation.

Fig. 17 shows a configuration of an embodiment of a memory system having a semiconductor memory device of the present invention, and is composed of a control unit 200 and a semiconductor memory device 210. As shown in FIG.

In FIG. 17, the controller 200 transmits a command signal COM, an address signal ADD, and write data DATA to the semiconductor memory device 210, and read data DATA to the semiconductor memory device 210. ).

The control unit 200 transmits the write command WR, the read command RD, the refresh command, etc. as the command signal COM, and the address signal ADD when the write command WR and the read command RD are transmitted. Send together. At this time, as the address signal ADD, a row address for accessing a word line and a source line and a column address for accessing a bit line are simultaneously transmitted. When the write command WR is transmitted, the write data DATA is transmitted together with the address signal ADD. When the refresh command REF is transmitted, only the refresh command REF is transmitted without transmitting the address signal ADD and the write data WR.

When the address signal ADD including the row and column addresses and the write data DATA are transmitted together with the write command WR, the semiconductor memory device 210 internally classifies the row address and the column address in the above-described operating method. Accordingly, the word line and the source line corresponding to the row address are controlled, and the write data DATA is transmitted to the bit line corresponding to the column address to perform the write operation. In addition, when the address signal ADD including the row and column addresses is transmitted together with the read command RD, the word line and the source line corresponding to the row address according to the above-described operation method by dividing the row address and the column address internally. The control operation is performed, and the read operation is performed by controlling the bit line corresponding to the column address. When the refresh command REF is applied, a refresh row address or a column address is internally generated according to the refresh method described above to control the source line or the bit line to perform the refresh operation.

Since the memory system of the present invention transmits the address signal ADD including the row address and the column address at the time of the write command and the read command of the memory cell of the semiconductor memory device 210, the control of the controller 200 is controlled. Is simplified. That is, in the case of a semiconductor memory device having a general dynamic memory cell, the controller transmits a row address with an active command, transmits a column address and write data with a write command, and transmits a column address with a read command. In the case of a semiconductor memory device having a capacitor-free dynamic memory cell of the present invention, the controller does not need to apply an active command, and does not need to apply an address signal separately from a row address signal and a column address signal.

The system of FIG. 17 is illustrated so that the controller 200 does not apply the clock signal, but the clock signal may be configured to be applied to the semiconductor memory device 210 by the controller 200.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

1A and 1B show an example of a configuration of a dynamic memory cell without a general capacitor.

Fig. 2 shows an equivalent diagram of a dynamic memory cell having the floating body transistors shown in Figs. 1A and 1B.

Figure 3 is a graph showing the DC characteristics of one embodiment of a dynamic memory cell having a floating body transistor of the present invention.

Fig. 4 shows the structure of one embodiment of the semiconductor memory device of the present invention.

FIG. 5 shows an operation timing diagram for explaining the operation of one embodiment of the semiconductor memory device shown in FIG.

FIG. 6 is an operation timing diagram for explaining the operation of another embodiment of the memory cell array including the floating body transistor shown in FIG.

7 is a graph showing DC characteristics of another embodiment of the floating body transistor of the present invention.

Fig. 8 shows the construction of another embodiment of the semiconductor memory device of the present invention.

FIG. 9 shows an operation timing diagram for explaining the operation of the embodiment of the semiconductor memory device shown in FIG.

FIG. 10 shows an operation timing diagram for explaining the operation of another embodiment of the semiconductor memory device shown in FIG.

Fig. 11 is a block diagram showing the construction of still another embodiment of the semiconductor memory device of the present invention.

12A and 12 show the configuration of the first embodiment of the memory cell including the floating body transistor of the present invention.

13A and 13B show the configuration of the second embodiment of the memory cell including the floating body transistor of the present invention.

14A and 14B show the structure of the third embodiment of the memory cell including the floating body transistor of the present invention.

15A and 15B show the structure of the fourth embodiment of the memory cell including the floating body transistor of the present invention.

Figures 16A, B and C are plan and cross-sectional views of the structure of the fifth embodiment of a dynamic memory cell having a floating body transistor of the horizontal structure of the present invention.

Fig. 17 shows the construction of an embodiment of a memory system including the semiconductor memory device of the present invention.

Claims (88)

A memory cell array having a plurality of memory cells including a transistor having a floating body coupled between each of a plurality of word lines, a plurality of source lines, and a plurality of bit lines; And Applying a first write control signal to the at least one source line and the at least one word line in a first period during a write operation, applying a read control signal during a read operation, and at least one of the above A control unit for applying a refresh control signal to a bit line or at least two said source lines, When a voltage corresponding to a first data state is applied to the bit line in the first period during the write operation, a first bipolar current flows through the selected at least one memory cell, respectively, and the at least one selected during the read operation. A second bipolar current flows when the first data state is stored in a memory cell of the second cell; and a third bipolar current flows when the first data state is stored in the at least one selected memory cell during the refresh operation. A semiconductor memory device. The method of claim 1, wherein the control unit And a data retention control signal applied to each of the plurality of word lines and the plurality of source lines during a data retention operation. The method of claim 2, wherein the control unit Applying a second write control signal to the at least one source line and the at least one word line in a second period during the write operation; And the second bipolar current flows in the second period during the write operation. The method of claim 3, wherein the control unit After data is applied to the plurality of bit lines, the first write control signal is sequentially applied to each of the at least one source line and the at least one word line, and in the second period during the write operation. And sequentially applying the second write control signal to at least one word line and the at least one source line and applying data to the plurality of bit lines. The method of claim 4, wherein the first light control signal is A signal having a first voltage applied to the at least one source line and a second voltage lower than the first voltage applied to the at least one word line, The second light control signal is And a signal having a third voltage lower than the second voltage applied to the at least one word line and a signal having the first voltage applied to the at least one source line. The method of claim 5, wherein the read control signal is And a signal having the first voltage applied to the at least one source line and a signal having the third voltage applied to the at least one word line. The method of claim 6, wherein the data retention control signal is A signal having the second voltage applied to the plurality of source lines, a signal of the third voltage applied to the plurality of word lines, and a signal having the second voltage applied to the plurality of bit lines A semiconductor memory device comprising a. The method of claim 7, wherein the refresh control signal is And a signal having the second voltage and a signal having the third voltage applied to each of the plurality of source lines and the plurality of word lines, and sequentially into at least one bit line of the plurality of bit lines. And a signal having the first voltage applied to the semiconductor memory device. The method of claim 7, wherein the refresh control signal is And a signal having the second voltage, a signal having the third voltage, and a signal having the first voltage applied to each of the plurality of source lines, the plurality of word lines, and the plurality of bit lines. A semiconductor memory device, characterized in that. The method of claim 7, wherein the refresh control signal is A signal having the second voltage and a signal having the third voltage applied to each of the plurality of bit lines and the plurality of word lines, and including at least two source lines of the plurality of source lines. And a signal having the first voltage applied sequentially. The method of claim 7, wherein the refresh control signal is And a signal having the second voltage, a signal having the third voltage, and a signal having the first voltage applied to each of the plurality of bit lines, the plurality of word lines, and the plurality of source lines. A semiconductor memory device, characterized in that. The method of claim 7, wherein the memory cell array A plurality of memory cell array blocks, The refresh control signal is A signal having the second voltage, a signal having the third voltage, applied to each of the plurality of source lines, the plurality of word lines, and the plurality of bit lines of each of the plurality of memory cell array blocks; And a signal having the first voltage. The method of claim 7, wherein the memory cell array A plurality of memory cell array blocks, The refresh control signal is A signal having the second voltage, a signal having the third voltage, applied to each of the plurality of bit lines, the plurality of word lines, and the plurality of source lines of each of the plurality of memory cell array blocks; And a signal having the first voltage. The method of claim 5, wherein the control unit Applying a write and read prohibition control signal to at least one bit line unselected during the write operation and the read operation, The write and read prohibition control signal is A fourth voltage lower than the first voltage and higher than the second voltage applied to the bit line of the unselected at least one memory cell during the first period and the second period and the read operation during the write operation. A semiconductor memory device comprising a signal. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And reading data by sensing a current flowing through the bit line during the read operation. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And reading data by sensing the voltage of the bit line during the read operation. The memory cell array of claim 3, wherein the memory cell array comprises: The plurality of word lines and the plurality of source lines are disposed in the same direction, and the plurality of bit lines are disposed in a direction orthogonal to the plurality of word lines, and the two adjacent floating portions are arranged in the bit line direction. Drains of the body transistors are commonly connected, and sources and gates of the floating body transistors arranged in the word line direction are respectively commonly connected; The source of the transistor having the floating body is connected to a corresponding source line of the plurality of source lines, the gate is connected to a corresponding word line of the plurality of word lines, and the drain is the plurality of bit lines And connected to the corresponding bit line. The method of claim 2, wherein the control unit After data is applied to the plurality of bit lines, the first write control signal is sequentially applied to each of the at least one source line and the at least one word line, and the at least one word line and the at least one And sequentially terminating the first write control signal applied to the source line of the data, and ending the application of data to the plurality of bit lines. 19. The method of claim 18, wherein the first light control signal is And a signal having a first voltage applied to the at least one source line and a second voltage lower than the first voltage applied to the at least one word line. The method of claim 19, wherein the read control signal is And a signal having a third voltage lower than the second voltage applied to the at least one word line and a signal having the first voltage applied to the at least one source line. 21. The apparatus of claim 20, wherein the data retention control signal is The signal having the first voltage applied to the plurality of source lines, the signal having a fourth voltage lower than the third voltage applied to the plurality of word lines, and the signal applied to the plurality of bit lines. And a signal having a second voltage. The method of claim 21, wherein the refresh control signal is And a signal having the second voltage and a signal having the fourth voltage applied to each of the plurality of source lines and the plurality of word lines, and sequentially into at least one bit line of the plurality of bit lines. And a signal having the first voltage applied to the semiconductor memory device. The method of claim 21, wherein the refresh control signal is And a signal having the second voltage, a signal having the fourth voltage, and a signal having the first voltage applied to each of the plurality of source lines, the plurality of word lines, and the plurality of bit lines. A semiconductor memory device, characterized in that. The method of claim 21, wherein the refresh control signal is A signal having the second voltage and a signal having the fourth voltage applied to each of the plurality of bit lines and the plurality of word lines, and including at least two source lines of the plurality of source lines And a signal having the first voltage applied sequentially. The method of claim 21, wherein the refresh control signal is And a signal having the second voltage, a signal having the fourth voltage, and a signal having the first voltage applied to each of the plurality of bit lines, the plurality of word lines, and the plurality of source lines. A semiconductor memory device, characterized in that. 22. The memory cell of claim 21, wherein the memory cell array is A plurality of memory cell array blocks, The refresh control signal is A signal having the second voltage, a signal having the fourth voltage, applied to each of the plurality of source lines, the plurality of word lines, and the plurality of bit lines of each of the plurality of memory cell array blocks; And a signal having the first voltage. 22. The memory cell of claim 21, wherein the memory cell array is A plurality of memory cell array blocks, The refresh control signal is A signal having the second voltage, a signal having the fourth voltage, applied to each of the plurality of bit lines, the plurality of word lines, and the plurality of source lines of each of the plurality of memory cell array blocks; And a signal having the first voltage. The method of claim 20, wherein the control unit Applying a write and read prohibition control signal to at least one bit line unselected during the write operation and the read operation, The write and read prohibition control signal is And a signal having a fourth voltage lower than the first voltage and higher than the second voltage applied to the bit line of the at least one memory cell selected during the write operation and during the read operation. A semiconductor memory device characterized by the above-mentioned. 19. The method of claim 18, wherein the memory cell array is The plurality of word lines and the plurality of source lines are disposed in the same direction, and the plurality of bit lines are disposed in a direction orthogonal to the plurality of word lines, and the floating body transistors are adjacent to the bit line direction. A drain and a source of the floating body transistors are connected in common, and the source and the gate of the floating body transistors arranged in the word line direction are respectively connected in common, The source of the transistor having the floating body is connected to a corresponding source line of the plurality of source lines, the gate is connected to a corresponding word line of the plurality of word lines, and the drain is the plurality of bit lines And connected to the corresponding bit line. The method of claim 1, wherein each of the plurality of memory cells A first conductive semiconductor pattern provided in the form of a floating body on the substrate; First and second impurity regions provided in the semiconductor pattern to have a second conductivity type different from the first conductivity type, and spaced apart from each other; A first body region of the first conductive type provided in the semiconductor pattern between the first and second impurity regions; And A gate pattern of the first conductive type provided on the first body region and having a width smaller than that of the first body region, And the first impurity region is connected to the bit line, the second impurity region is connected to the source line, and the gate pattern is connected to the word line. The semiconductor memory device of claim 30, wherein the gate pattern, the first impurity region, and the second impurity region do not overlap each other. 31. The semiconductor memory device according to claim 30, wherein the first conductivity type is p-type and the second conductivity type is n-type. 31. The semiconductor memory device of claim 30, wherein the first impurity region is an emitter of a bipolar junction transistor and the second impurity region is a collector of a bipolar junction transistor. 32. The semiconductor memory device of claim 30, further comprising an extended semiconductor pattern extending from at least one sidewall of both sidewalls of the first body region and having the first conductivity type. 31. The method of claim 30, wherein each of the plurality of memory cells is And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, The gate pattern overlaps the first body region and the second body region and extends to overlap a portion of the first impurity region and a portion of the second impurity region such that the width of the gate pattern is increased in the first body region and And a width greater than the sum of the widths of the second body regions. 36. The semiconductor memory device of claim 35, wherein the second body region has a lower impurity concentration than the first body region. 31. The method of claim 30, wherein each of the plurality of memory cells is And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, And the gate pattern extends to overlap a portion of the first impurity region, and the gate pattern does not overlap the second impurity region. 38. The semiconductor memory device of claim 37, wherein the second body region has a lower impurity concentration than the first body region. 38. The method of claim 37, wherein each of the plurality of memory cells is And a buffer region interposed between the first body region and the second impurity region, And the gate pattern extends to overlap a portion of the first impurity region and a portion of the buffer region. The method of claim 39, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. A semiconductor memory device, characterized in that. 31. The method of claim 30, wherein the dynamic memory cell is And a buffer region interposed between the first body region and the second impurity region, And the gate pattern overlapping a portion of the first impurity region and not overlapping the buffer region. The method of claim 41, wherein The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. A semiconductor memory device, characterized in that. The method of claim 1, wherein each of the plurality of memory cells A semiconductor pattern provided on the substrate of the first conductive type; A first impurity region provided in a lower region of the semiconductor pattern and having a second conductive type different from the first conductive type; A second impurity region of the second conductivity type provided in an upper region of the semiconductor pattern; A first body region of the first conductivity type provided in the semiconductor pattern between the first impurity region and the second impurity region; A gate pattern of a first conductivity type provided on a sidewall of the first body region and having a width smaller than that of the first body region, And the first impurity region is connected to the bit line, the second impurity region is connected to the source line, and the gate pattern is connected to the word line. The semiconductor memory device of claim 43, wherein the gate pattern, the first impurity region, and the second impurity region do not overlap each other. 44. The semiconductor memory device according to claim 43, wherein the first conductivity type is p-type and the second conductivity type is n-type. 44. The semiconductor memory device of claim 43, wherein the first impurity region is an emitter of a bipolar junction transistor and the second impurity region is a collector of a bipolar junction transistor. 44. The method of claim 43, wherein each of the plurality of memory cells And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, The gate pattern overlaps the first body region and the second body region and extends to overlap a portion of the first impurity region and a portion of the second impurity region such that the width of the gate pattern is increased in the first body region and And a width greater than the sum of the widths of the second body regions. 48. The semiconductor memory device of claim 47, wherein the second body region has a lower impurity concentration than the first body region. 46. The memory cell of claim 43, wherein the plurality of memory cells And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, And the gate pattern extends to overlap a portion of the first impurity region, and the gate pattern does not overlap the second impurity region. 50. The semiconductor memory device of claim 49, wherein the second body region has a lower impurity concentration than the first body region. 44. The method of claim 43, wherein each of the plurality of memory cells And a buffer region interposed between the first body region and the second impurity region, And the gate pattern extends to overlap a portion of the first impurity region and a portion of the buffer region. The method of claim 51, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity concentration. A semiconductor memory device, characterized in that. 44. The method of claim 43, wherein each of the plurality of memory cells Further comprising a buffer region interposed between the first body region and the second impurity region, And the gate pattern overlapping a portion of the first impurity region and not overlapping the buffer region. The method of claim 53, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. A semiconductor memory device, characterized in that. A first conductive semiconductor pattern provided in the form of a floating body on the substrate; First and second impurity regions provided in the semiconductor pattern to have a second conductivity type different from the first conductivity type, and spaced apart from each other; A first body region of the first conductivity type provided in the semiconductor pattern between the first and second impurity regions; And And a gate pattern of the first conductive type provided on the first body region and having a width smaller than that of the first body region. 56. The dynamic memory cell of claim 55, wherein the gate pattern, the first impurity region and the second impurity region do not overlap each other. 57. The dynamic memory cell of claim 56, wherein the first conductivity type is p-type and the second conductivity type is n-type. 56. The dynamic memory cell of claim 55 wherein the first impurity region is an emitter of a bipolar junction transistor and the second impurity region is a collector of a bipolar junction transistor. 56. The dynamic memory cell of claim 55, further comprising an expansion semiconductor pattern extending from at least one sidewall of both sidewalls of the first body region and having the first conductivity type. 56. The system of claim 55, wherein the dynamic memory cell is And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, The gate pattern overlaps the first body region and the second body region and extends to overlap a portion of the first impurity region and a portion of the second impurity region such that the width of the gate pattern is increased in the first body region and And the width of the second body region is greater than the sum of the widths of the second body regions. 61. The dynamic memory cell of claim 60, wherein the second body region has a lower impurity concentration than the first body region. 56. The system of claim 55, wherein the dynamic memory cell is And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, And the gate pattern extends to overlap a portion of the first impurity region, and the gate pattern does not overlap the second impurity region. 63. The dynamic memory cell of claim 62, wherein the second body region has a lower impurity concentration than the first body region. 56. The system of claim 55, wherein the dynamic memory cell is And a buffer region interposed between the first body region and the second impurity region, And the gate pattern extends to overlap a portion of the first impurity region and a portion of the buffer region. 65. The method of claim 64, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. Characterized by a dynamic memory cell. 56. The system of claim 55, wherein the dynamic memory cell is And a buffer region interposed between the first body region and the second impurity region, And the gate pattern overlapping a portion of the first impurity region and not overlapping the buffer region. 67. The method of claim 66, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. Dynamic memory cell, characterized in that. A semiconductor pattern provided on the substrate of the first conductive type; A first impurity region provided in a lower region of the semiconductor pattern and having a second conductive type different from the first conductive type; A second impurity region of the second conductivity type provided in an upper region of the semiconductor pattern; A first body region of the first conductivity type provided in the semiconductor pattern between the first impurity region and the second impurity region; And a gate pattern of a first conductivity type provided on a sidewall of the first body region and having a width less than that of the first body region. 69. The dynamic memory cell of claim 68, wherein the gate pattern, the first impurity region and the second impurity region do not overlap each other. 69. The dynamic memory cell of claim 68, wherein the first conductivity type is p-type and the second conductivity type is n-type. 69. The dynamic memory cell of claim 68 wherein the first impurity region is an emitter of a bipolar junction transistor and the second impurity region is a collector of a bipolar junction transistor. 69. The system of claim 68, wherein the dynamic memory cell is And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having an impurity concentration different from the first body region, The gate pattern overlaps the first body region and the second body region and extends to overlap a portion of the first impurity region and a portion of the second impurity region such that the width of the gate pattern is increased in the first body region and And the width of the second body region is greater than the sum of the widths of the second body regions. 73. The dynamic memory cell of claim 72, wherein the second body region has a lower impurity concentration than the first body region. 69. The system of claim 68, wherein the dynamic memory cell is And further comprising a second body region of the first conductivity type interposed between the first impurity region and the first body region and having a different impurity concentration from the first body region, And the gate pattern extends to overlap a portion of the first impurity region, and the gate pattern does not overlap the second impurity region. 75. The dynamic memory cell of claim 74, wherein the second body region has a lower impurity concentration than the first body region. 69. The system of claim 68, wherein the dynamic memory cell is And a buffer region interposed between the first body region and the second impurity region, And the gate pattern extends to overlap a portion of the first impurity region and a portion of the buffer region. 77. The method of claim 76, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. Dynamic memory cell, characterized in that. 69. The system of claim 68, wherein the dynamic memory cell is And a buffer region interposed between the first body region and the second impurity region, And the gate pattern overlapping a portion of the first impurity region and not overlapping the buffer region. The method of claim 78, The buffer region has the same conductivity type as the first body region and has a lower impurity concentration than the first body region, or has the same conductivity type as the second impurity region and has a lower impurity concentration than the second impurity region. Dynamic memory cell, characterized in that. If the command signal is a write command, an address signal and write data including a specific row address and a column address are transmitted together with the write command. If the command signal is a read command, an address including a specific row address and the column address together with the read command. A controller for transmitting a signal together and receiving read data; And A transistor configured to receive the command signal, the address signal and the write data, transfer the read data, and have a floating body coupled between each of a plurality of word lines, a plurality of source lines, and a plurality of bit lines And a semiconductor memory device having a memory cell array having a plurality of memory cells. 81. The semiconductor memory device of claim 80, wherein the semiconductor memory device is The write command applies a first write control signal to the at least one source line and at least one word line corresponding to the row address in a first period during a write operation, and at least one corresponding to the column address. The write data is transmitted to a bit line, and if the read command, a read control signal is applied to at least one source line corresponding to the row address, and the data of the at least one bit line corresponding to the column address is read. Send it as data, When a voltage corresponding to a first data state is applied to the bit line in response to the write data in the first period during the write operation, a first bipolar current flows through the selected at least one memory cell, respectively, and the read And operating the second bipolar current when the first data state is stored in the selected at least one memory cell during operation. 82. The method of claim 81, wherein the control unit If the command signal is a refresh command, apply the refresh command, The semiconductor memory device When the refresh command is applied, a refresh control signal is applied to the at least one bit line or the at least two source lines, and when the first data state is stored in the at least one selected memory cell, a third bipolar current is applied. A memory system, characterized by flowing. 82. The semiconductor memory device of claim 81, wherein the semiconductor memory device And a data retention control signal applied to each of the plurality of word lines and the plurality of source lines during a data holding operation for holding data stored in the plurality of memory cells. 85. The semiconductor memory device of claim 82, wherein the semiconductor memory device Applying a second write control signal to the at least one source line and the at least one word line in a second period during the write operation; And the second bipolar current flows in the second period during the write operation. 85. The semiconductor memory device of claim 84, wherein the semiconductor memory device is After data is applied to the plurality of bit lines, the first write control signal is sequentially applied to each of the at least one source line and the at least one word line, and in the second period during the write operation. And sequentially applying the second write control signal to at least one word line and the at least one source line and applying data to the plurality of bit lines. 85. The semiconductor memory device of claim 84, wherein the semiconductor memory device is And applying a write and read prohibition control signal to the bit lines of the at least one memory cell which are unselected during the read operation and the first and second periods during the write operation. 84. The semiconductor memory device of claim 83, wherein the semiconductor memory device After data is applied to the plurality of bit lines, the first write control signal is sequentially applied to each of the at least one source line and the at least one word line, and the at least one word line and the at least one Sequentially terminating the first write control signal applied to the source line of the memory device, and ending the application of data to the plurality of bit lines. 85. The semiconductor memory device of claim 84, wherein the semiconductor memory device is And applying a write and read prohibition control signal to a bit line of at least one memory cell which is unselected during the read operation and the read operation during the write operation.

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