JPS59110158A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate the drive of a word line by a method wherein the movement of carriers is controlled by a field effect transistor driven by a transfer gate connected to the word line. CONSTITUTION:Since a p type region 3 which constitutes the junction type gate of the field effect transistor is surrounded, in the entire periphery, with an n- channel region 2 and an insulation film 4, it is in electrically floating state. The charge accumulated in the region 3 keeps its potential unless neutralized by the carrier thermally generated at the part of the p-n junction, and then exhibits memory function. The movement of the carrier is controlled by using the field effect transistor driven by the transfer gate 7 connected to the word line 10. Thereby, the drive of the word line can be facilitated without passing a large current through the word line.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement in a semiconductor memory device constituted by a dynamic RAM cell having a conversion conductance for stored charges therein.

Conventional technology and problems Conventionally, switching of only one dynamic RAM cell
Many devices consist of a memory cell consisting of a transistor and a memory capacitor (storage capacitor). The output voltage of this type of memory cell is 1/20 or less of the power supply voltage because the charge in the storage capacitor is divided by the bit line parasitic capacitance and the storage capacitance of the memory cell itself. becomes an extremely small value.

Therefore, in addition to requiring a highly sensitive sense amplifier,
Due to the noise signal mixed into the bit line, the read data may be erroneously amplified. In recent years, a particular problem has been the generation of minority carriers due to alpha rays emitted from packages in which memories are mounted, which causes a large noise component to bit lines.

To solve this problem, a cell called a tapered isolated dynamic gain cell has been proposed in recent years, which has a conversion conductance for the accumulated charge inside the cell (if necessary, P , K , Ch
Paper by atterjee et al.: I.

S, S, C, C, D, igest of Te
Chnical Papers, p 22.19
79).

This cell does not read out the accumulated charge itself, but rather detects the channel conductance of the transistor modulated by the charge, so the cell output is large and non-destructive readout is possible. Since the size of the cell is the size of one transistor, there are advantages such as miniaturization.

However, in this cell, the drain of the transistor in the memory cell is directly connected to the word line, and the source is directly connected to the bit line, so the following problem occurs.

■ Since all of the cell current flows into the word line, a large current flows through the word line drive circuit, potentially causing electromigration to thin word lines, and a very large word line drive circuit is required. . Then, if the cell current is reduced, the operation becomes slower, which creates a trade-off situation. Furthermore, this problem becomes more noticeable as the number of integrated bits increases.

■ The hole accumulation region and the substrate are separated by a double-diffused pnp structure under a tapered oxide film, and in the case of writing, it is necessary to punch through this pnp structure. Therefore, if not strictly controlled during manufacturing, the punch-through voltage will be non-uniform, and in extreme cases, the data written may vary even within the same memory chip.
Narrow the operating voltage margin of the power supply.

(2) If the isolation structure does not have a tapered portion and is suitable for high integration, the punch-through voltage of the pnp transistor will increase, making it difficult for the cell to operate. In other words, it has elements that do not meet the purpose of high integration.

■ Since the bit line is directly connected to the cell's transistor and there is no transfer gate, if the bit line voltage drops excessively during a read operation, other unselected cells on the same bit line will become conductive. . this is,
Since the retained data depends on the location, the bit line voltage caused by reading does not become constant.

To prevent this, it is necessary to prevent the bit line voltage from fluctuating too much. However, this reduces the memory cell output and loses the cell's inherent advantage of relatively large cell output.

Purpose of the Invention The present invention provides a tapered isolated dynamic
While maintaining the characteristics of the Guinamisoku RAM cell, which has conversion conductance for Mm charges inside like a gain cell, that is, the advantage of being able to obtain a large output voltage despite being a small cell, it is possible to maintain the advantage of being able to obtain a large output voltage even though it is a small cell, and yet without flowing a large current to the word line. It is intended to enable column addressing and facilitate word line driving.

Structure of the Invention The present invention makes the gate of a field effect transistor having a junction type gate electrically floating, and determines the magnitude of the channel conductance of the transistor, which depends on the amount of carriers accumulated here, of the data held. “
0" and "1, and has a structure similar to that of a floating gate ROM. However, the writing method does not rely on avalanche injection or tunnel injection like conventional floating game ROMs, but in order to enable faster writing,
A field effect transistor driven by a transfer gate connected to a word line is used to control the movement of carriers. The transfer gate also functions as a selection gate when reading memory cells.

Examples of the invention FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention.

In the figure, 1 is a p-type silicon semiconductor substrate, 2 is an n-type channel region in a junction gate field effect transistor (floating gate transistor), and 3 is a p-band region for forming the junction gate. , 4 is an insulating film made of, for example, a silicon dioxide film, 5 is an electrode made of, for example, a first layer polycrystalline silicon film that acts as a write bit line (V/-BL), and 6 is a silicon dioxide film, for example. 7 is a transfer gate electrode made of, for example, a second layer of polycrystalline silicon film connected to the word line, and 8 is a drain side supply voltage. , is applied to the n+ type drain region 9 of the floating gate transistor portion, which is connected to the read bit line (R-B
The n+ type region 10 acting as a word line (WL)
), each of which is made of an aluminum film, for example, is shown.

As is clear from the figure, the p-band region 3 constituting the junction type gate (floating gate) is surrounded by the n-type channel region 2 and the insulating film 4, so it is in an electrically floating state. . Therefore, unless the charges accumulated in the p-band region 3 are neutralized by carriers thermally generated at the p-n junction, the potential can be maintained and the memory function can be performed. Note that the electrode 5 on the p-type head region 3 applies a potential to the p-band region 3 through capacitive coupling via the insulating film 4.

Now, when the transfer gate electrode 7 in the memory cell of the selected row is biased to a high level, the n-type channel region 2 in the floating gate transistor part and the n+-type region which is the bit line 9 are connected, and a cell current flows according to the held data. At this time, the drain side supply voltage van is applied to the drain region 8 in the floating gate transistor portion. Therefore, this memory cell is structurally a two-transistor type memory cell. However, in reality, the cell dimensions are not much different from a one-transistor type Taber isolated type dynamic gain cell. The reason for this will be detailed later.

Next, the principle of operation of the embodiment described with reference to FIG. 1 will be explained.

FIG. 2 is an equivalent circuit diagram of one embodiment of the present invention, in which the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.

In the figure, Ql is a junction gate field effect transistor that functions as a memory, C2 is a transfer gate/1 field effect transistor, C3 is a p-channel transistor, C1 is a capacitance, and CB is a parasitic capacitance of the bit line R-BL. It shows.

In this circuit, the floating gate of the junction gate field effect transistor Q1 connects the write bit via the capacitor C1 (capacitance between the p-band region 3 and the write bit line electrode 5 in FIG. 1). It is connected to line W-BL.

Since the drain-side supply voltage van is applied to the drain of the transistor Q1, this increases the potential barrier to holes near the floating gate and prevents holes from being injected from the semiconductor substrate into the floating gate. There is.

Transistor Q2 is connected to the channel region of transistor Q1 (
N-type channel region 2) and bit line R- in FIG.
BL (operates to connect the n+ type region 9 in FIG. 1).

Transistor Q3 will be explained with reference to FIG. 1. The semiconductor substrate 1 is the source (or drain), the p-band region 3 which is the floating gate is the train (or source), and the transfer gate electrode is common to transistor Q2. 7 as the gate, and the hack gate uses an extension of the channel region 3 of transistor Q1.

If the threshold voltage of transistor Q2 is Vt2 and the threshold voltage of transistor Q3 is Vt3, then if the word line voltage when the memory cell is in the holding state is 1s, then Vt3<Vwls<Vt2...i
It is necessary to make it ll. That is, considering that transistor Q3 is a p-channel type and transistor Q3 is an n-channel type, both transistors Q2 and Q3 can be cut.
It means it's off.

Next, a read operation and a write operation will be explained.

"Reading" When reading data from a memory cell, the word line WL is set to high level, and the voltage V wlr is set to Vt3<Vt
2ku Vwlr ・ ・ ・ ・
(2). In this way, transistor Q2 is turned on and current flows through the memory cell to read bit line R-BL through the channel region of junction gate field effect transistor Ql. This current is determined by the data held in the memory cell, and in some cases transistor Q1 may be completely cut off for one data so that no cell current flows, and only for the other data. It is possible to set it to .

When performing the read operation, the rising read bit line R-BL is set in advance to a low level, for example, to a ground potential. In the device of the present invention, the parasitic capacitance CB of the bit line R-BL in such a state is charged with the cell current to raise its potential. Also, while in the read and hold state, 1. The voltage of the write bit line W-BL is an intermediate voltage Vm (Vm'=!4voo) between the power supply voltage and the ground voltage.

“Write” Write data “1” is defined as a state in which holes are accumulated in a junction type gate, that is, a floating gate.

When writing, the voltage of the word line WL is set to a low level (even lower than the holding state), and this voltage V
wlw is Vwlw <Vt3<Vt2...1
3). By doing this, transistor Q2 is turned off and transistor Q3 is turned on. In this state, the voltage of the write bit line W-BL is lowered from Vm to a low level VSS<source supply voltage. Accordingly, holes flow from the semiconductor substrate into the floating gate through the transistor Q3. Next, the voltage of the word line WL is raised to the holding voltage to turn off the transistor Q3. Next, by raising the voltage of the write bit line W-BL to the holding state voltage Vm, the voltage of the floating gate is raised by capacitive coupling via the capacitor C1, and the transistor Q2 is The internal resistance becomes a relatively low bias state and data is retained.

Transistor Q3 sets the voltage of write word line WL of data “0” to a low level.
After turning on, the voltage of write bit line W-BL is raised from voltage Vn+ to high level VDD (drain side supply power supply voltage). Along with this, the holes in the floating gate are released to the semiconductor substrate via the transistor Q3. As a result, if the impurity concentration of the floating gate is relatively low, the entire interior of the floating gate may become depleted. Next, the word line W
After turning off the transistor Q3 with the voltage of L at the holding level, the voltage of the write pin line W-BL is lowered to the holding state voltage Vm, and the potential of the floating gate is reduced by capacitive coupling via the capacitor C1. is pulled down, and transistor Q1 either has its gate deeply negatively biased and is cut off, or has a very high internal resistance.

As can be understood from the above description, the operation of the semiconductor memory device of the present invention is based on a principle somewhat similar to that of a tapered isolated type dynamic gain cell. This is because if only the transistor Q1 is taken out and viewed, it can be considered in the same way as a tapered isolated type dynamic gain cell.

However, the essential difference is that the semiconductor memory device of the present invention does not require a tapered portion, which is an important feature of the tapered tent type gain cell.

Because of these structural differences, their operations are also essentially different. In other words, in a tapered isolated type dynamic gain cell, the potential for holes directly under the tapered isolation film that is generated during selective oxidation is lowered, and this is used to connect the junction type gate, that is, the floating gate, through this part. Injecting holes.

However, in the semiconductor memory device of the present invention, since the transistor Q3 is used to inject holes,
The formation of the tapered isolation film becomes unnecessary. Therefore, not only is there no problem even if isolation is performed using a method that does not form a tapered isolation film, such as a buried isolation process, but the structure of the present invention also allows for higher integration of devices. For example, high integration such as 1 megabit or 4 megabit is possible.

In the semiconductor memory device of the present invention, the size of two transistors is required per memory cell, but since it has a transfer gate, unselected cells can be separated from the bit line. Therefore, adjacent memory cells can share a read bit line.

On the other hand, in a tapered isolated type dynamic gain cell, the read bit line on the same column cannot be shared with adjacent columns, so each cell has its own wiring width and surrounding isolation area. dimensions are required. For this reason, when compared with the cell according to the present invention, they are almost the same. Therefore, the cell according to the present invention, which requires the size of two transistors, is superior to other types of efficient cells in terms of high integration. For example, the conventional one-transistor
Compared to a single-capacitor type memory cell, the cell size is about 60% larger because a storage capacitor is not required and only a small floating gate type transistor is formed instead. It's only a matter of time.

Also, in terms of memory cell output, 1 transistor/1
In a capacitor type memory cell, a sufficient output voltage must be applied to the bit line, so a highly integrated memory requires a large amount of stored charge even if it is small.

Therefore, a very thin insulating film or a special high dielectric constant film such as quantal oxide (Ta205) is required. However, since the semiconductor memory device of the present invention has a conversion conductance for accumulated charges inside the cell, the cell output is large, and if a sufficiently long time can be applied, the read bit line voltage will be close to the drive power supply voltage. Can be made to a large value. Therefore, an extremely thin insulating film is not required, and highly integrated memories can be manufactured with high reliability.

Furthermore, in the cell in the semiconductor memory device of the present invention, word lines can be driven much more easily than in a tapered isolated type dynamic gain cell. That is,
In the cell of the present invention, the word line is the transfer line of each cell.
It connects the gates, and there is no need for direct current to flow through it. On the other hand, in a tapered isolated type dynamic gain cell, all the currents of the cells on the same word line flow to the word line, and the word line driving part has a large amount of current that cannot be driven by the size of the transistor that can be integrated. In some cases, a large current may flow, and this is particularly likely to occur as the number of integrated bits increases. To avoid this, it is possible to reduce the current flowing through the memory cell, but this increases the time required to charge and discharge the bit line, reducing the operating speed. In the present invention, such a thing does not occur.

FIG. 3 is a main part circuit diagram of an embodiment including peripheral circuits that drive memory cells according to the present invention.
The same parts as those described with reference to the figures and FIG. 2 are designated by the same symbols. Further, FIG. 4 is a timing chart of a driving clock for explaining the operation of the embodiment shown in FIG.

In FIG. 3, Qll to Q2'3 are transistors,
MC is a memory cell, DMC is a dummy memory cell,
D and D are data buses, D-WL is a dummy word line, φρ, φS, φt, φy.

φm each indicates a clock. Note that the transistors Qll to Q14 constitute a flip-flop which is a sense amplifier.

Now, in this embodiment, in the initial state of the sense operation,
Transistor Q15 is off and transistor Q
Since 20 and Q21 are conductive, the focus line R-BL is pre-charged to the ground level.

To perform a read operation, after cutting off the pre-charge signal and turning off transistors Q20 and Q21, the row decoder drives the selected word line WL and dummy word line D-WL. When word line WL and dummy word line D-WL rise, memory cell MC and dummy memory cell DMC become conductive, and power supply line (not shown)
The floating bit line R-BL is charged up through cells MC and DMC. Bit line R
- Since the parasitic capacitance of BL is set equal on the cell MC side and the cell DMC side, both cells MC and DMC are conductive when reading data "1", but the dummy memory cell DMC is about the same as the memory cell MC. When set to have half the conductance, the potential of memory cell MC rises approximately twice as fast as that of dummy memory cell DMC. Therefore, at an appropriate timing, the transistor Q
By making the bit line 15 conductive and activating the flip-flops made up of transistors Qll to Q14, the bit line potential difference is amplified, and one goes to the DD level and the other goes to the Vss (ground) level. The potential of the word line WL may be lowered once the sensing operation starts. This point is largely different from the conventional one-transistor/one-capacitor type memory cell. That is, in conventional memory cells, the word line must be kept at a high level until the sensing operation is completed in order to rewrite (refresh) after reading, but in the cell of the present invention, the word line must be kept at a high level until the sensing operation is completed. When writing, the word line WL sends data to the bit line R-BL and then immediately lowers its voltage to the write level V wlw. It takes about 20 to 30 (ns) for the sense amplifier to operate, so if the word line WL is set to the write level during this time, the memory cell of the present invention can perform read and write operations. Even if the word line voltages are different and time is required to set them up, the disadvantage is not a substantial problem. The sense amplifier amplifies the read signal, raises the clock φt, turns on transistors Q26 and Q27, and transfers the sense signal to the bit line W-BL. If the sense output at this time is at a high level, inverted data is transferred to the write bit line W-BL so as to transfer a low level. Transistors Q18 and Q19, which are transfer gate transistors in the column selected by the column decoder, are then made conductive by clock φy to transfer data to data buses D and D and output them. The signal transferred to the write bit line W-BL sets the word line WL to the holding level Vwls, and then resets the bit line W-BL to the holding level ■m by making transistors Q22 and Q23 conductive. Complete writing.

By the way, since the memory cell of the present invention allows non-destructive reading, it is not necessary to rewrite data as described above every time. Furthermore, since the sense amplifier can be used in common for a plurality of columns, even if a relatively complex sense amplifier is used, there is no restriction due to column pinch.

Further, the memory cell of the present invention has a read bit line R-
Since the BL is read from the ground level, the cell data is transferred to the bit line R-B'L as soon as the gate voltage of the transfer gate transistor rises, allowing high-speed operation. If the bit line is pre-charged to a high level, as in the case of a conventional one-transistor/one-capacitor type memory cell, and this charge is extracted by the cell, the bit line becomes a bit Complete data transfer will not be completed unless the word line rises above the line charge level, and a delay in the rise of the word line will reduce the read operation speed of the memory cell.

Furthermore, the cell of the present invention is highly resistant to soft errors caused by alpha ray irradiation. This is not only because the signal appearing on the bit line is large, but also because the charge storage region is surrounded by potential barriers. For example, if electron-hole pairs are generated in a p-type semiconductor substrate by irradiation with alpha rays, the holes are majority carriers and are easily absorbed by the substrate electrode, but the electrons diffuse through the substrate. , which is absorbed by the storage capacitor electrode in a conventional memory cell.
cause an error. However, in the cell of the present invention, the charge storage region is a p-type floating gate surrounded by an n-type region. Therefore, even if electrons that have diffused in the substrate reach the substrate and are immediately taken into the n-type region, they will not be absorbed by the connected n+-type region in FIG.
It is absorbed by the power supply through the drain region 8) and does not cause soft errors. If this n1 type region were used as a bit line, a soft error would occur through the focus line, but in the present invention, it is connected to this n+ type region power supply. ,
That won't happen. This is the reason why the semiconductor memory device of the present invention has particularly high resistance to soft errors.

If a soft error occurs in the cell of the present invention, it would be if α rays directly hit the floating gate, but since the floating gate has a small area, the probability of a direct hit is lower than that of a conventional 1-transistor, 1-capacitor type memory.・
Much lower than Cell. This is also one of the reasons why the semiconductor memory device of the present invention is resistant to irradiation with alpha rays and the like.

Fig. 5 is a cutaway side view of essential parts showing another embodiment of the present invention, and the same parts as those explained in relation to Fig. 1 are indicated by the same symbols. The difference from the embodiment described above is that the threshold voltage of the transfer gate transistor is increased toward the n-channel side, that is, in the direction away from the junction gate field effect transistor (write transistor), and the p-channel In order to maintain the threshold voltage of the write transistor near the ground potential, p-type impurities are introduced into the entire transfer area of the transfer gate transistor to form a p-type channel doped region 11). .

Since only an extremely small current flows through this p-channel write transistor, it is possible to operate it in the punch-through current range or sub-threshold current range.

In this way, when the transfer gate is set to a level that allows writing, for example, the ground level, and the p-channel write transistor is in the on state as a field effect transistor, the floating gate will retain any charge during reading. Even if the write bit line is in a holding state, it is always electrically connected to the semiconductor substrate to reach the substrate potential during writing, and when the write bit line is then set to the holding state, voltage fluctuations on the write bit line can be applied to the floating gate through capacitive coupling. In such a case, the write bit line may be reset to a low level (or high level) in a held state. That is,
The write bit line only needs to have two levels, VDD and VSS, and Vm is not required, so the power supply system in the memory chip can be simplified.

The above operation will be explained in more detail. That is, in the first stage of writing in which the word line is set to low level, data “0” is written.
To write data “1”, the write bit line is set to high level, and to write data “1”, the write bit line is set to low level. At this time, the p-channel write transistor is conductive, so the floating gate is always at the same potential as the substrate. Next, the word line is set to the holding level, the p-channel write transistor is turned off, and the write bit line is set to the ground level.After data "0" is written, the potential of the floating gate decreases due to capacitive coupling. Then, the junction gate transistor is turned off. Therefore, during reading, no cell current flows and data "θ" is detected. Also, the voltage of the write bit line does not change after writing data "1". Therefore, the cell current can flow through the channel and data "1" is detected.

Effect of the invention The effects of the present invention are listed below.

■ The structure has gain within the cell, so a large cell output can be obtained despite its small size.

■ Since the cell is equipped with a transfer gate transistor, there is no need to run a direct current through the word line, making it easy to drive the word line.

(2) For the same reason as (2) above, no matter what value the bit line voltage becomes, there is no influence from unselected cells.

■ The isolation part can be formed into any shape, and an isolation process suitable for high integration that does not cause bird's peaks can be adopted.

■ Due to the structure of the cell, it is difficult to cause soft errors caused by irradiation with alpha rays, etc.

[Brief explanation of the drawing]

Fig. 1 is a cutaway side view of the main part of an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the embodiment of Fig. 1, and Fig. 3 is a main part circuit of the embodiment of the invention including peripheral circuits. 4 is a timing chart for explaining the operation of the circuit shown in FIG. 3, and FIG. 5 is a cutaway side view of a main part of another embodiment of the present invention. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is an n-channel region in a junction gate field effect transistor (floating gate transistor) part, 3 is a p-type region for forming a junction gate, and 4 is a p-type silicon semiconductor substrate. 5 is an insulating film, 5 is a polycrystalline silicon electrode that acts as a write bit line (W-BL), 6 is an insulating film, 7 is a polycrystalline silicon transfer gate electrode connected to the word line, and 8 is a floating gate. - The n+ type drain region 9 of the transistor portion acts as a read bit line (R-BL), and the n+ type region 10 serves as an electrode that acts as a word line (WL). Patent applicant: Fujitsu Ltd. Representative patent attorney: Tools: Kugobe

Claims (1)

[Claims] It is embedded near the surface of a semiconductor substrate of one conductivity type, has a conductivity type opposite to that of the semiconductor substrate, and has one end connected to a transfer gate.
A channel region that constitutes the drain region of the transistor and whose other end is in contact with a high impurity concentration region of the opposite conductivity type connected to a power supply, and is surrounded by the channel region and faces an electrode that is a data writing focus line through an insulating film. a junction gate region in an electrically floating state; a high impurity concentration region of an opposite conductivity type opposite to the drain region of the channel region and connected to the read bit line; and a source region of the transfer gate transistor. a transfer gate electrode formed on a channel region between a high impurity concentration region of opposite conductivity type and the drain region via an insulating film, the transfer gate electrode serving as a gate electrode, the junction gate region and the semiconductor substrate; 1. A semiconductor memory device comprising a field effect transistor having a channel of one conductivity type and having a drain region and a source region.