CN101908371B - Gain cell eDRAM for programmable logic device - Google Patents
Gain cell eDRAM for programmable logic device Download PDFInfo
- Publication number
- CN101908371B CN101908371B CN200910052484A CN200910052484A CN101908371B CN 101908371 B CN101908371 B CN 101908371B CN 200910052484 A CN200910052484 A CN 200910052484A CN 200910052484 A CN200910052484 A CN 200910052484A CN 101908371 B CN101908371 B CN 101908371B
- Authority
- CN
- China
- Prior art keywords
- mos transistor
- write
- edram
- read
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Dram (AREA)
Abstract
The invention belongs to the technical field of embedded dynamic random access memories (eDRAM), and in particular relates to a gain cell eDRAM for a programmable logic device. The gain cell eDRAM in the invention comprises a read MOS transistor, a write MOS transistor, a write word line, a read word line, a write bit line, a read bit line and an equivalent parasitic capacitor, wherein a charge storage end of the equivalent parasitic capacitor controls a switch tube of the programmable logic device; and by using the characteristic of non-destructive read or small destructive read of the gain cell eDRAM, the potential of a storage node does not change or the potential change is small when read operation is performed during updating operation, so the change of the logic state of the switch tube is not influenced. The chip area of the programmable logic device using the gain cell eDRAM can be greatly reduced.
Description
Technical field
The invention belongs to embedded DRAM (eDRM) technical field, be specifically related to a kind of gain unit (Gain Cell) eDRAM that is used for PLD.
Background technology
PLD is the abbreviation of PLD (Programable Logic Device); FPGA is the abbreviation of field programmable gate array (Field Programable Gate Array); Both functions are basic identical, realize that just principle is slightly different, so in the prior art; Sometimes can ignore the two difference, PLD and FPGA are referred to as PLD.PLD can be accomplished the function of any digital device, goes up to high-performance CPU, down to simple 74 circuit, can realize with PLD.PLD is as a blank sheet of paper or a pile building blocks, and the slip-stick artist can be through traditional schematic diagram input method, or hardware description language designs a digital display circuit freely.Through software emulation, can verify the correctness of design in advance.After PCB accomplishes, can also utilize the online modification ability of PLD, modification at any time designs and needn't change hardware circuit.Use PLD to develop digital circuit, can shorten design time greatly, reduce the PCB area, improve the reliability of system.These advantages of PLD make the PLD technology after the nineties, obtain development at full speed, have also promoted the progress of eda software and hardware description language (HDL) simultaneously greatly.
PLD or FPGA PLD include a plurality of MOS switching tubes and the storer that is used to control the MOS switching tube; In the prior art, at first, propose to adopt SRAM as config memory; SRAM is used to control the MOS switching tube of PLD, and it has low in energy consumption, fireballing characteristics.Further,, require its area more and more littler, therefore proposed to adopt DRAM to replace the storer of SRAM, conduct control MOS switching tube along with the development of PLD.
The U.S. Patent number that Xilinx company proposes is to point out in the United States Patent (USP) of US6137714; Be used to control the traditional capacitor element of DRAM memory employing stray capacitance replacement of MOS switching tube; Avoid the complicated shortcoming of manufacturing process of the relative PLD of manufacturing process of capacitor element, and further reduced the shared area of memory portion.Shown in Figure 1 for the DRAM cellular construction synoptic diagram that is used for PLD of prior art.As shown in Figure 1, DRAM unit 10 comprises that MOS gate tube 110, stray capacitance 111,112 are memory node; MOS gate tube 110 is through storage unit outside word line 140 its conductings of control or shutoff; The source end of MOS gate tube 110 connects the outside bit line 130 of storage unit; Word line 140, bit line 130 are connected with Peripheral storage control circuit module 150, through word line 140, bit line 130 and Peripheral storage control circuit module 150 control DRAM unit 10 read-write operations and refresh operations; The charge storage situation of memory node 112 reflection stray capacitances 111; Memory node 112 directly is connected with the grid of the switching tube 120 of PLD, therefore can be through the conducting and the shutoff of DRAM unit 10 CS pipes 120, for example; 10 storages " 1 " of DRAM unit; Switching tube 120 conductings, 10 storages " 0 " of DRAM unit, switching tube 120 turn-offs; Stray capacitance 111 comprises the electric capacity of the active area of the gate capacitance of switching tube 120 and the end that MOS gate tube 110 is connected with memory node 112.For this DRAM unit 10; Read or write or the process that keeps in; Stray capacitance 111 can especially in the read operation process, can discharge electric charge through the MOS gate tube 110 of conducting through the subthreshold value electric leakage of MOS gate tube 110 and the grid leak tele-release electric charge of switching tube 120; Therefore its read operation process is destructive, need constantly carry out refresh operation to the DRAM unit through Peripheral storage control circuit module 150.
Shown in Figure 2 for the another DRAM cellular construction synoptic diagram that is used for PLD of prior art.As shown in Figure 2, DRAM unit 20 comprises MOS gate tube 210, stray capacitance 211 and phase inverter 213; 212 is memory node, the stored charge of reflection stray capacitance 211, and memory node 212 directly is connected with the input end of phase inverter 213, and the output terminal of phase inverter 213 directly connects the grid of switching tube 120.Equally; MOS gate tube 210 is through storage unit outside word line 140 its conductings of control or shutoff; The source end of MOS gate tube 110 connects the outside bit line 130 of storage unit; Word line 140, bit line 130 are connected with Peripheral storage control circuit module 150, through word line 140, bit line 130 and Peripheral storage control circuit module 150 control DRAM unit 20 read-write operations and refresh operations; Read or write or the process that keeps in; Stray capacitance 211 can be through the subthreshold value electric leakage of MOS gate tube 210 and the grid leak tele-release electric charge of switching tube 120; Especially in the read operation process; Can discharge electric charges by the MOS gate tube 210 through conducting, so its read operation process is destructive, need constantly carries out refresh operation through Peripheral storage control circuit module 150 to the DRAM unit.Be different from DRAM unit part shown in Figure 1 and be to increase the phase inverter that is used to isolate, the fluctuation of the electromotive force of memory node 212 can not have influence on the variation of electromotive force of the grid of switching tube 120 to a certain extent like this, guarantees the in stable condition of switching tube 120.
But; More than the DRAM storage unit of embodiment illustrated in figures 1 and 2 when being applied to PLD; Its major defect is: read operation is destructive, is write-after-read during refresh operation, and stray capacitance discharges and recharges (read operation in the refresh operation process also is destructive) through the MOS gate tube to stray capacitance in its read operation process; This moment is because the potential change of stray capacitance can cause state variation (the conducting change shutoff of switching tube; Perhaps turn-off the change conducting, perhaps conducting shutoff degree dies down), the variation of this switching tube state can cause the logic state mistake of PLD.In the prior art; Overcome this shortcoming if desired, generally can adopt the content of another this DRAM unit of shadow memory corresponding storage, write shadow memory to the content of DRAM unit when refreshing with this DRAM unit; Shadow memory makes the switching tube state keep stable; This solution needs extra shadow memory, can increase chip area, and complicated operating process.
Simultaneously, see also Fig. 3, shown in Figure 3ly be the gain cell eDRAM cellular construction synoptic diagram with two metal-oxide-semiconductors of prior art.This eDRAM is proposed in U.S. Pat 7120072 by Intel Company, and it mainly is in order to replace SRAM to realize storing on the high density sheet.As shown in Figure 3; This Gain Cell eDRAM 100 comprise write MOS transistor 101, read MOS transistor 102, write word line (Write Word Line; WWL) 105, readout word line (Read Word Line; RWL) 106, write bit line (Write Bit Line, WBL) 107, sense bit line (Read Bit Line, RBL) 108 and equivalent parasitic capacitances 104.Wherein, the source region of writing MOS transistor 101 is connected in the grid of reading MOS transistor 102, and MN point 103 is a memory node; Equivalent parasitic capacitances 104 1 ends are connected with 103; Other end ground connection, therefore, conducting and shutoff that MOS transistor 102 is read in the high low energy control of the current potential that MN is ordered; For example, during electric capacity 104 stored charges, representative storage " 1 ", MN point 103 is a noble potential, can control and read MOS transistor 102 shutoffs.Read a termination RBL of MOS transistor 102, another termination RWL; Write a termination WBL of MOS transistor 101, another termination is read the grid of MOS transistor 102.In this embodiment, equivalent parasitic capacitances 104 is for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102, also or both combinations.Specify its operating process below in conjunction with the operating list among Fig. 3:
(1) write operation (Write): when writing " 0 ", RWL, RBL put 0 current potential and read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 0V, thus equivalent parasitic capacitances 104 discharges, and memory node 103 current potentials are 0.During one writing, RWL, RBL put 0 current potential and read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 1V, thus equivalent parasitic capacitances 104 chargings, and memory node 103 current potentials are noble potential.
(Hold): RWL, RBL put 0 current potential and read MOS transistor 102 and do not work when (2) data kept, and WWL puts 1V, writes MOS transistor 101 and turn-offs, and the current potential of memory node 103 does not receive ectocine.
(3) read operation (Read): when reading " 0 ", WWL puts 1V, and WBL puts 0V, writes MOS transistor 101 and turn-offs; The RWL biasing is less than 1V, and RBL puts 0V, and read MOS transistor 102 conductings this moment, and RWL charges to RBL through reading MOS transistor, because sensing circuit has clamping action, the electrical potential energy of RBL reaches 200mV, thereby can sense data " 0 ".When reading " 1 ", WWL puts 1V, and WBL puts 0V, writes MOS transistor 101 and turn-offs; The RWL biasing is read MOS transistor 102 this moment and is turn-offed less than 1V, and RWL can not charge to RBL through reading MOS transistor, and RBL keeps the 0V current potential, thereby can sense data " 1 ".
Operating list
From top read operation process, can find out; Equivalent parasitic capacitances does not discharge electric charge through writing MOS transistor; Therefore to read degree low for its destructiveness, and its main destructiveness is read and is that on the one hand equivalent parasitic capacitances can discharge electric charge through the subthreshold value electric leakage of writing the MOS gate tube and the grid leak electricity of reading MOS transistor 120; The variation meeting that is the voltage of readout word line and sense bit line in the readout on the other hand influences the stable of equivalent parasitic electromotive force through the active area and the stray capacitance coupling between the grid of reading MOS transistor; But this influence is reversible; Be that read operation finishes, influence also disappears.
Summary of the invention
The objective of the invention is to propose a kind of gain cell eDRAM, when this gain cell eDRAM can avoid the DRAM of prior art to be applied to PLD, its refresh operation brought the problem of the state variation of switching tube.
Gain cell eDRAM provided by the invention; Be used for configuration of programmable logic devices; It comprises read MOS transistor, write MOS transistor, write word line, readout word line, write bit line, sense bit line and equivalent parasitic capacitances; The grid of writing MOS transistor is connected in write word line, and drain terminal/source end of writing MOS transistor is connected in write bit line, and source end/drain terminal of writing MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; The grid of reading MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; Drain terminal/source end of reading MOS transistor is connected in sense bit line, and source end/drain terminal of reading MOS transistor is connected in readout word line, and the stored charge end of said equivalent parasitic capacitances is controlled the switching tube of said PLD.
Gain cell eDRAM provided by the invention; Wherein, Write word line, readout word line, write bit line and sense bit line all are connected with the Peripheral storage control circuit module, and read operation, write operation, data that said Peripheral storage control circuit module is used for ride gain unit eDRAM keep operation and refresh operation.Said equivalent parasitic capacitances comprises one of gate capacitance of the active area stray capacitance of writing MOS transistor, the gate capacitance of reading MOS transistor and switch mos transistor, perhaps is the combination of writing the gate capacitance of the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, switch mos transistor.Saidly read MOS transistor and write MOS transistor and can be nmos pass transistor, also can be the PMOS transistor.Said PLD is a field programmable gate array.Said switching tube can be nmos pass transistor or PMOS transistor.
As the preferred technique scheme, gain cell eDRAM also comprises phase inverter, and the input end of said phase inverter is connected with the stored charge end of said equivalent parasitic capacitances, and the output terminal of phase inverter is connected with the grid of the switching tube of said PLD.Said equivalent parasitic capacitances is to write the active area stray capacitance of MOS transistor, read one of the gate capacitance of MOS transistor, gate capacitance of the MOS transistor in the phase inverter, perhaps is the combination of the gate capacitance of writing the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, the MOS transistor in the phase inverter.
Technique effect of the present invention is; The memory node of the gain cell eDRAM of this invention is controlled the switching tube of said PLD; Utilize this gain cell eDRAM do not have destructiveness read or destructiveness read features of smaller, in carrying out the refresh operation process, when carrying out read operation; The current potential of memory node does not change, and perhaps potential change is smaller, thereby can not influence the variation of the logic state of switching tube.Therefore the read operation process of this gain cell eDRAM can not cause the logic state mistake of PLD, the contrast prior art, and the shadow memory that does not increase can dwindle the chip area of PLD greatly.
Description of drawings
Fig. 1 is the DRAM cellular construction synoptic diagram that is used for PLD of prior art.
Fig. 2 is the another DRAM cellular construction synoptic diagram that is used for PLD of prior art.
Fig. 3 is the gain cell eDRAM cellular construction synoptic diagram with two metal-oxide-semiconductors of prior art.
Fig. 4 is the structural representation of the first embodiment gain cell eDRAM provided by the invention.
Fig. 5 is the structural representation of the second embodiment gain cell eDRAM provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.
Shown in Figure 4 is the structural representation of an embodiment gain cell eDRAM provided by the invention.This embodiment gain cell eDRAM 300 is used for the config memory of PLD; Be used to control the conducting and the shutoff of its switching tube; Switching tube is one of elementary cell of PLD, and its logic state has reflected the programming state of PLD.In this invention, PLD not only refers to PLD, also comprises the essentially identical PLDs of principle such as FPGA.As shown in Figure 4; Gain cell eDRAM 300 comprise write MOS transistor 301, read MOS transistor 302, write word line (Write Word Line; WWL) 305, readout word line (Read Word Line; RWL) 306, write bit line (WriteBit Line, WBL) 307, sense bit line (Read Bit Line, RBL) 308 and dotted line shown in equivalent parasitic capacitances 304.Because this electric capacity 304 that is used for stored charge is parasitic electric capacity; In its actual device architecture the capacitor element that independent physics exists; Equivalent parasitic capacitances 304 is for to write the active area stray capacitance of MOS transistor 301 or to read the gate capacitance of MOS transistor 302 or the gate capacitance of switching tube 309, also or above three's combination; The concrete equivalent capacitance value size of equivalent parasitic capacitances 304 is not limited by the present invention, and it is relevant with the technology generations of making device MOS transistor device; Any electric capacity one end is the stored charge end; The other end is relative earth terminal; Equivalent parasitic capacitances 304 is no exception, and the one of which termination is low, other end stored charge; Its stored charge end has reflected has stored logical message " 0 " perhaps " 1 ", therefore will be defined as memory node with the direct-connected node 303 of stored charge end.The grid of writing MOS transistor 301 is connected in write word line 305; The drain terminal (or source end) of writing MOS transistor 301 is connected in write bit line 307; The source end (or drain terminal) of writing MOS transistor 301 is connected in the stored charge end of equivalent parasitic capacitances, also is memory node 303.If write MOS transistor 301 conductings, can 304 chargings of equivalent stray capacitance or discharge.The grid of reading MOS transistor 302 is connected in the stored charge end of equivalent parasitic capacitances 304, also is memory node 303, and the drain terminal (perhaps source end) of reading MOS transistor is connected in sense bit line 308, and the source end (perhaps drain terminal) of reading MOS transistor is connected in readout word line 306; Through the stored charge of memory node, can reflect the level of its memory node, thereby can control the conducting or the shutoff of reading metal-oxide-semiconductor 302.In this embodiment; Reading MOS transistor 302 is the PMOS transistor with writing MOS transistor 301; Turn-off when conducting when being its grid low level, high level; But its particular type is not limited by the present invention, reads MOS transistor 302 and writes MOS transistor 301 and can be nmos pass transistor yet, promptly turn-offs when conducting during its grid high level, low level.
Continue as shown in Figure 4; Provided to the property omitted the peripheral control circuit that is used for ride gain unit eDRAM 300; The write word line 305 of this gain cell eDRAM 300, write bit line 307, readout word line 306, sense bit line 308 are direct-connected with its Peripheral storage control circuit module 310; In concrete practical application, Peripheral storage control circuit module 310 comprises line decoder, column decoder, line decoder driving, column decoder driving, reading circuit module, write circuit module, address latch, logical sequence control module or the like.Write word line 305, write bit line 307, readout word line 306 and sense bit line 308 through 310 pairs of these gain cell eDRAMs 300 of storage control circuit module applies signal can carry out read operation, write operation, data to gain cell eDRAM 300 and keep operation and refresh operation or the like; In this embodiment, refresh operation also is the combination of two operating process of write-after-read.EDRAM operating process shown in Figure 3 was basic identical during its specific operation process and background technology were introduced.Need to prove especially; Read current between write word line 308 and the readout word line 306 is through reading 302 of metal-oxide-semiconductor; And through equivalent parasitic capacitances 304, equivalent parasitic capacitances 304 charge stored can remain unchanged basically, the mainly subthreshold value electric leakage through writing MOS gate tube 301 of its charge stored, read the grid leak electricity of MOS transistor 302 and the grid leak electricity of switching tube discharges electric charge; Therefore, its gain cell eDRAM do not have destructiveness read or destructiveness read less.
Continue as shown in Figure 4ly, this gain cell eDRAM 300 is directly to be connected with the switching tube 309 of PLD, and the grid of switching tube 309 is directly connected in the memory node 303 of gain cell eDRAM 300; Switching tube 309 is a nmos pass transistor in this embodiment; Therefore, if gain cell eDRAM 300 is stored " 1 ", memory node is a high level, then switching tube 309 conductings; If gain cell eDRAM 300 storages " 0 ", memory node are low level, then switching tube 309 turn-offs.The logic state of switching tube 309 is directly controlled by gain cell eDRAM 300.In other embodiments, switching tube 309 also can be the PMOS transistor.
Comprehensive above Fig. 4 is said; Can find out; This invention utilize this gain cell eDRAM do not have destructiveness read or destructiveness read features of smaller, in carrying out the refresh operation process, when carrying out read operation; The current potential of memory node 303 does not change, and perhaps potential change is smaller, thereby can not influence the variation of the state of switching tube 309.Therefore the read operation process of this gain cell eDRAM can not cause the logic state mistake of PLD.Need can not reduce the chip area of PLD greatly as the shadow memory of being mentioned in the prior art.
Shown in Figure 5 is the structural representation of another embodiment gain cell eDRAM provided by the invention.Comparison diagram 4 and Fig. 5 embodiment, its difference is that the gain cell eDRAM 400 of Fig. 5 embodiment comprises that also places the phase inverter between memory node and the switching tube.As shown in Figure 5; Gain cell eDRAM 400 comprise write MOS transistor 401, read MOS transistor 402, write word line (Write Word Line; WWL) 405, readout word line (Read Word Line; RWL) 406, write bit line (Write Bit Line, WBL) 407, sense bit line (Read Bit Line, RBL) 408 and dotted line shown in equivalent parasitic capacitances 404.Because this electric capacity 404 that is used for stored charge is parasitic electric capacity; In its actual device architecture the capacitor element that independent physics exists; Equivalent parasitic capacitances 404 is for writing the gate capacitance of metal-oxide-semiconductor in the active area stray capacitance of MOS transistor 301, the gate capacitance of reading MOS transistor 402 or the phase inverter 413, also or above three's combination; The concrete equivalent capacitance value size of equivalent parasitic capacitances 404 is not limited by the present invention, and it is relevant with the technology generations of making device MOS transistor device; Any electric capacity one end is the stored charge end; The other end is relative earth terminal; Equivalent parasitic capacitances 404 is no exception, and the one of which termination is low, other end stored charge; Its stored charge end has reflected has stored logical message " 0 " perhaps " 1 ", therefore will be defined as memory node with the direct-connected node 403 of stored charge end.The grid of writing MOS transistor 401 is connected in write word line 405; The drain terminal (or source end) of writing MOS transistor 401 is connected in write bit line 407; The source end (or drain terminal) of writing MOS transistor 401 is connected in the stored charge end of equivalent parasitic capacitances, also is memory node 403.If write MOS transistor 401 conductings, can 404 chargings of equivalent stray capacitance or discharge.The grid of reading MOS transistor 402 is connected in the stored charge end of equivalent parasitic capacitances 404, also is memory node 403, and the drain terminal (perhaps source end) of reading MOS transistor is connected in sense bit line 408, and the source end (perhaps drain terminal) of reading MOS transistor is connected in readout word line 406; Through the stored charge of memory node, can reflect the level of its memory node, thereby can control the conducting or the shutoff of reading metal-oxide-semiconductor 402.In this embodiment; Reading MOS transistor 402 is the PMOS transistor with writing MOS transistor 401; Turn-off when conducting when being its grid low level, high level; But its particular type is not limited by the present invention, reads MOS transistor 402 and writes MOS transistor 401 and can be nmos pass transistor yet, promptly turn-offs when conducting during its grid high level, low level.
Continue as shown in Figure 5; Provided to the property omitted the peripheral control circuit that is used for ride gain unit eDRAM 400; The write word line 405 of this gain cell eDRAM 400, write bit line 407, readout word line 406, sense bit line 408 are direct-connected with its Peripheral storage control circuit module 410; In concrete practical application, Peripheral storage control circuit module 410 comprises line decoder, column decoder, line decoder driving, column decoder driving, reading circuit module, write circuit module, address latch, logical sequence control module or the like.Write word line 405, write bit line 407, readout word line 406 and sense bit line 408 through 410 pairs of these gain cell eDRAMs 400 of storage control circuit module applies signal can carry out read operation, write operation, data to gain cell eDRAM 400 and keep operation or the like; In this embodiment, refresh operation also is the combination of two operating process of write-after-read.EDRAM operating process shown in Figure 3 was basic identical during its specific operation process and background technology were introduced.Need to prove especially; Read current between write word line 408 and the readout word line 406 is through reading 402 of metal-oxide-semiconductor; And through equivalent parasitic capacitances 404, equivalent parasitic capacitances 404 charge stored can remain unchanged basically, the mainly subthreshold value electric leakage through writing MOS gate tube 401 of its charge stored, read the grid leak electricity of MOS transistor 402 and the transistorized grid leak electricity of phase inverter discharges electric charge; Therefore, its gain cell eDRAM do not have destructiveness read or destructiveness read less.
Continue as shown in Figure 5; This gain cell eDRAM 400 is to be connected with the switching tube 409 of PLD, and the grid of switching tube 409 is directly connected in the output terminal of the phase inverter 413 of gain cell eDRAM 400, and the input end of phase inverter 413 directly is connected with memory node 403; Switching tube 409 is a nmos pass transistor in this embodiment; Therefore, if gain cell eDRAM 400 is stored " 1 ", memory node is a high level, then switching tube 409 turn-offs; If gain cell eDRAM 400 storages " 0 ", memory node are low level, then switching tube 409 conductings.The logic state of switching tube 409 is directly controlled by gain cell eDRAM 400.In other embodiments, switching tube 409 also can be the PMOS transistor.Phase inverter 413 can be the CMOS phase inverter.Through between memory node 403 and switching tube 409, phase inverter 413 being set; The fluctuation of the electromotive force of memory node 403 can not have influence on the variation of high electronegative potential of the grid of switching tube 413 to a certain extent; Guarantee the in stable condition of switching tube 120, so the destructiveness of the patient read operation process of the gain cell eDRAM of this embodiment is higher relatively.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific embodiment described in the instructions.
Claims (9)
1. eDRAM who is used for PLD, comprise read MOS transistor, write MOS transistor, write word line, readout word line, write bit line, sense bit line and equivalent parasitic capacitances; The grid of writing MOS transistor is connected in write word line; The drain terminal of writing MOS transistor is connected in write bit line; The source end of writing MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; The source end of perhaps writing MOS transistor is connected in write bit line, and the drain terminal of writing MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; The grid of reading MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; The drain terminal of reading MOS transistor is connected in sense bit line, and the source end of reading MOS transistor is connected in readout word line, and the source end of perhaps reading MOS transistor is connected in sense bit line, and the drain terminal of reading MOS transistor is connected in readout word line; It is characterized in that the stored charge end of said equivalent parasitic capacitances is controlled the switching tube of said PLD;
Wherein, Said equivalent parasitic capacitances is one of gate capacitance of writing the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, switching tube, perhaps is the combination of writing the gate capacitance of the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, switching tube.
2. eDRAM according to claim 1; It is characterized in that; Write word line, readout word line, write bit line and sense bit line all are connected with the Peripheral storage control circuit module, and read operation, write operation, data that said Peripheral storage control circuit module is used for ride gain unit eDRAM keep operation and refresh operation.
3. eDRAM according to claim 1 is characterized in that, also comprises phase inverter, and the input end of said phase inverter is connected with the stored charge end of said equivalent parasitic capacitances, and the output terminal of phase inverter is connected with the grid of the switching tube of said PLD.
4. eDRAM according to claim 3; It is characterized in that; Said equivalent parasitic capacitances is to write the active area stray capacitance of MOS transistor, read one of the gate capacitance of MOS transistor, gate capacitance of the MOS transistor in the phase inverter, perhaps is the combination of the gate capacitance of writing the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, the MOS transistor in the phase inverter.
5. eDRAM according to claim 3 is characterized in that, said phase inverter is the CMOS phase inverter.
6. eDRAM according to claim 1 is characterized in that, saidly reads MOS transistor and writes MOS transistor and be nmos pass transistor.
7. eDRAM according to claim 1 is characterized in that, saidly reads MOS transistor and writes MOS transistor and be the PMOS transistor.
8. eDRAM according to claim 1 is characterized in that, said PLD is a field programmable gate array.
9. eDRAM according to claim 1 is characterized in that, said switching tube is nmos pass transistor or PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910052484A CN101908371B (en) | 2009-06-04 | 2009-06-04 | Gain cell eDRAM for programmable logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910052484A CN101908371B (en) | 2009-06-04 | 2009-06-04 | Gain cell eDRAM for programmable logic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101908371A CN101908371A (en) | 2010-12-08 |
| CN101908371B true CN101908371B (en) | 2012-10-17 |
Family
ID=43263805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910052484A Expired - Fee Related CN101908371B (en) | 2009-06-04 | 2009-06-04 | Gain cell eDRAM for programmable logic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101908371B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8605489B2 (en) * | 2011-11-30 | 2013-12-10 | International Business Machines Corporation | Enhanced data retention mode for dynamic memories |
| EP3506265A1 (en) * | 2017-12-29 | 2019-07-03 | IMEC vzw | A memory device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5122986A (en) * | 1990-11-21 | 1992-06-16 | Micron Technology, Inc. | Two transistor dram cell |
| US6137714A (en) * | 1998-01-30 | 2000-10-24 | Xilinx, Inc. | Dynamic memory cell for a programmable logic device |
| US7120072B2 (en) * | 2004-06-30 | 2006-10-10 | Intel Corporation | Two transistor gain cell, method, and system |
| CN1845330A (en) * | 2005-04-08 | 2006-10-11 | 株式会社瑞萨科技 | Semiconductor memory device |
| CN1956197A (en) * | 2005-10-26 | 2007-05-02 | 国际商业机器公司 | Gain cells and methods of making and using the same |
-
2009
- 2009-06-04 CN CN200910052484A patent/CN101908371B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5122986A (en) * | 1990-11-21 | 1992-06-16 | Micron Technology, Inc. | Two transistor dram cell |
| US6137714A (en) * | 1998-01-30 | 2000-10-24 | Xilinx, Inc. | Dynamic memory cell for a programmable logic device |
| US7120072B2 (en) * | 2004-06-30 | 2006-10-10 | Intel Corporation | Two transistor gain cell, method, and system |
| CN1845330A (en) * | 2005-04-08 | 2006-10-11 | 株式会社瑞萨科技 | Semiconductor memory device |
| CN1956197A (en) * | 2005-10-26 | 2007-05-02 | 国际商业机器公司 | Gain cells and methods of making and using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101908371A (en) | 2010-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5162276B2 (en) | Ferroelectric memory device | |
| US7693004B2 (en) | Semiconductor memory device | |
| JPH01307095A (en) | Nonvolatile cam | |
| CN102760473A (en) | Differential sense amplifier without dedicated precharge transistors | |
| CN102081962B (en) | EDRAM (Enhanced Dynamic Random Access Memory) unit of gain unit, memory and operating method | |
| CN101908371B (en) | Gain cell eDRAM for programmable logic device | |
| CN105097017A (en) | SRAM (static random access memory) storage unit, SRAM memory and control method therefor | |
| CN101924550A (en) | Lookup table using gain unit eDRAMs | |
| CN101887748A (en) | CAM/TCAM provided with shadow non-volatile memory | |
| CN104637532A (en) | SRAM storage unit array, SRAM memory and control method thereof | |
| CN115662483B (en) | SRAM memory cell array, read-write method, controller and system | |
| KR930000898B1 (en) | Semiconductor memory capable of high-speed data erasing | |
| CN101908370B (en) | Memory and gain unit eDRAM (embedded Dynamic Random Access Memory) unit combined by bit lines | |
| TWI423258B (en) | Dual port sram having a higher voltage write-word-line in writing operation | |
| CN101923890B (en) | Gain unit eDRAM for programmable logic device | |
| Gupta et al. | Tunnel FET negative-differential-resistance based 1T1C refresh-free-DRAM, 2T1C SRAM and 3T1C CAM | |
| US7212431B2 (en) | Nonvolatile ferroelectric memory device and control method thereof | |
| Oh et al. | Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications | |
| US9025403B1 (en) | Dynamic cascode-managed high-voltage word-line driver circuit | |
| CN115602208A (en) | Memory and writing method thereof | |
| CN111951848A (en) | Embedded dynamic random access memory gain unit and operation method thereof | |
| CN103824861A (en) | Fin-like back gate storage structure and automatic refreshing method of floating body cells | |
| US6788591B1 (en) | System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch | |
| CN116206649B (en) | Dynamic memory, read-write method thereof and memory device | |
| CN102081963B (en) | Embedded dynamic random access memory (eDRAM) cell -gain cell eDRAM cell with metal oxide semiconductor (MOS) capacitors and preparation method of gain cell eDRAM cells |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121017 Termination date: 20150604 |
|
| EXPY | Termination of patent right or utility model |