CN101908371A

CN101908371A - Gain cell eDRAM for programmable logic device

Info

Publication number: CN101908371A
Application number: CN2009100524843A
Authority: CN
Inventors: 林殷茵; 薛晓勇
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2009-06-04
Filing date: 2009-06-04
Publication date: 2010-12-08
Anticipated expiration: 2029-06-04
Also published as: CN101908371B

Abstract

The invention belongs to the technical field of embedded dynamic random access memories (eDRAM), and in particular relates to a gain cell eDRAM for a programmable logic device. The gain cell eDRAM in the invention comprises a read MOS transistor, a write MOS transistor, a write word line, a read word line, a write bit line, a read bit line and an equivalent parasitic capacitor, wherein a charge storage end of the equivalent parasitic capacitor controls a switch tube of the programmable logic device; and by using the characteristic of non-destructive read or small destructive read of the gain cell eDRAM, the potential of a storage node does not change or the potential change is small when read operation is performed during updating operation, so the change of the logic state of the switch tube is not influenced. The chip area of the programmable logic device using the gain cell eDRAM can be greatly reduced.

Description

The gain cell eDRAM that is used for programmable logic device (PLD)

Technical field

The invention belongs to embedded DRAM (eDRM) technical field, be specifically related to a kind of gain unit (Gain Cell) eDRAM that is used for programmable logic device (PLD).

Background technology

PLD is the abbreviation of programmable logic device (PLD) (Programable Logic Device), FPGA is the abbreviation of field programmable gate array (FieldProgramable GateArray), both functions are basic identical, realize that just principle is slightly different, so in the prior art, sometimes can ignore the two difference, PLD and FPGA are referred to as programmable logic device (PLD).Programmable logic device (PLD) can be finished the function of any digital device, goes up to high-performance CPU, down to simple 74 circuit, can realize with PLD.Programmable logic device (PLD) is as a blank sheet of paper or a pile building blocks, and the slip-stick artist can be by traditional schematic diagram input method, or hardware description language designs a digital display circuit freely.By software emulation, can verify the correctness of design in advance.After PCB finishes, can also utilize the online modification ability of programmable logic device (PLD), modification at any time designs and needn't change hardware circuit.Use programmable logic device (PLD) to develop digital circuit, can shorten design time greatly, reduce the PCB area, improve the reliability of system.These advantages of programmable logic device (PLD) make the PLD technology obtain development at full speed after the nineties, have also promoted the progress of eda software and hardware description language (HDL) simultaneously greatly.

PLD or FPGA programmable logic device (PLD) include a plurality of MOS switching tubes and are used to control the storer of MOS switching tube, in the prior art, at first, propose to adopt SRAM as config memory, SRAM is used to control the MOS switching tube of programmable logic device (PLD), and it has low in energy consumption, fireballing characteristics.Further,, require its area more and more littler, therefore proposed to adopt DRAM to replace the storer of SRAM, conduct control MOS switching tube along with the development of programmable logic device (PLD).

The U.S. Patent number that Xilinx company proposes is to point out in the United States Patent (USP) of US6137714, be used to control the traditional capacitor element of DRAM memory employing stray capacitance replacement of MOS switching tube, avoid the shortcoming of manufacturing process complexity of the relative programmable logic device (PLD) of manufacturing process of capacitor element, and further reduced the shared area of memory portion.Figure 1 shows that the DRAM cellular construction synoptic diagram that is used for programmable logic device (PLD) of prior art.As shown in Figure 1, DRAM unit 10 comprises that MOS gate tube 110, stray capacitance 111,112 are memory node; MOS gate tube 110 is by word line 140 its conducting of control or the shutoffs of storage unit outside, the source end of MOS gate tube 110 connects the bit line 130 of storage unit outside, word line 140, bit line 130 are connected with Peripheral storage control circuit module 150, by word line 140, bit line 130 and Peripheral storage control circuit module 150 control DRAM unit 10 read-write operations and refresh operations; The charge storage situation of memory node 112 reflection stray capacitances 111, memory node 112 directly is connected with the grid of the switching tube 120 of programmable logic device (PLD), therefore can be by the conducting and the shutoff of DRAM unit 10 gauge tap pipes 120, for example, 10 storages " 1 " of DRAM unit, switching tube 120 conductings, 10 storages " 0 " of DRAM unit, switching tube 120 turn-offs; Stray capacitance 111 comprises the electric capacity of the active area of the gate capacitance of switching tube 120 and the end that MOS gate tube 110 is connected with memory node 112.For this DRAM unit 10, read or write or the process that keeps in, stray capacitance 111 can be by the subthreshold value electric leakage of MOS gate tube 110 and the grid leak tele-release electric charge of switching tube 120, especially in the read operation process, can discharge electric charge by the MOS gate tube 110 of conducting, therefore its read operation process is destructive, need constantly carry out refresh operation to the DRAM unit by Peripheral storage control circuit module 150.

Figure 2 shows that the another DRAM cellular construction synoptic diagram that is used for programmable logic device (PLD) of prior art.As shown in Figure 2, DRAM unit 20 comprises MOS gate tube 210, stray capacitance 211 and phase inverter 213; 212 is memory node, the stored charge of reflection stray capacitance 211, and memory node 212 directly is connected with the input end of phase inverter 213, and the output terminal of phase inverter 213 directly connects the grid of switching tube 120.Equally, MOS gate tube 210 is by word line 140 its conducting of control or the shutoffs of storage unit outside, the source end of MOS gate tube 110 connects the bit line 130 of storage unit outside, word line 140, bit line 130 are connected with Peripheral storage control circuit module 150, by word line 140, bit line 130 and Peripheral storage control circuit module 150 control DRAM unit 20 read-write operations and refresh operations; Read or write or the process that keeps in, stray capacitance 211 can be by the subthreshold value electric leakage of MOS gate tube 210 and the grid leak tele-release electric charge of switching tube 120, especially in the read operation process, can discharge electric charge by the MOS gate tube 210 of conducting, therefore its read operation process is destructive, need constantly carry out refresh operation to the DRAM unit by Peripheral storage control circuit module 150.Be different from DRAM unit part shown in Figure 1 and be to increase the phase inverter that is used to isolate, the fluctuation of the electromotive force of memory node 212 can not have influence on the variation of electromotive force of the grid of switching tube 120 to a certain extent like this, guarantees the in stable condition of switching tube 120.

But, more than the DRAM storage unit of embodiment illustrated in figures 1 and 2 when being applied to programmable logic device (PLD), its major defect is: read operation is destructive, it during refresh operation write-after-read, stray capacitance discharges and recharges (read operation in the refresh operation process also is destructive) by the MOS gate tube to stray capacitance in its read operation process, this moment is because the potential change of stray capacitance can cause state variation (the conducting change shutoff of switching tube, perhaps turn-off and become conducting, perhaps conducting shutoff degree dies down), the variation of this switching tube state can cause the logic state mistake of programmable logic device (PLD).In the prior art, overcome this shortcoming if desired, the content that generally can adopt another shadow memory corresponding to store this DRAM unit with this DRAM unit, when refreshing the content of DRAM unit is write shadow memory, shadow memory makes the switching tube state keep stable, this solution needs extra shadow memory, can increase chip area, and complicated operating process.

Simultaneously, see also Fig. 3, Figure 3 shows that the gain cell eDRAM cellular construction synoptic diagram with two metal-oxide-semiconductors of prior art.This eDRAM is proposed in U.S. Pat 7120072 by Intel Company, and it mainly is in order to replace SRAM to realize storing on the high density sheet.As shown in Figure 3, this Gain Cell eDRAM 100 comprise write MOS transistor 101, read MOS transistor 102, write word line (Write Word Line, WWL) 105, readout word line (Read Word Line, RWL) 106, write bit line (Write Bit Line, WBL) 107, sense bit line (Read Bit Line, RBL) 108 and equivalent parasitic capacitances 104.Wherein, the source region of writing MOS transistor 101 is connected in the grid of reading MOS transistor 102, and MN point 103 is a memory node, equivalent parasitic capacitances 104 1 ends are connected with 103, other end ground connection, therefore, conducting and shutoff that MOS transistor 102 is read in the high low energy control of the current potential that MN is ordered; For example, during electric capacity 104 stored charges, representative storage " 1 ", MN point 103 is a noble potential, can control and read MOS transistor 102 shutoffs.Read a termination RBL of MOS transistor 102, another termination RWL; Write a termination WBL of MOS transistor 101, another termination is read the grid of MOS transistor 102.In this embodiment, equivalent parasitic capacitances 104 is for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102, also or both combinations.Specify its operating process below in conjunction with the operating list among Fig. 3:

(1) write operation (Write): when writing " 0 ", RWL, RBL put 0 current potential and read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 0V, thus equivalent parasitic capacitances 104 discharges, and memory node 103 current potentials are 0.During one writing, RWL, RBL put 0 current potential and read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 1V, thus equivalent parasitic capacitances 104 chargings, and memory node 103 current potentials are noble potential.

(Hold): RWL, RBL put 0 current potential and read MOS transistor 102 and do not work when (2) data kept, and WWL puts 1V, writes MOS transistor 101 and turn-offs, and the current potential of memory node 103 is not subjected to ectocine.

(3) read operation (Read): when reading " 0 ", WWL puts 1V, and WBL puts 0V, writes MOS transistor 101 and turn-offs; The RWL biasing is less than 1V, and RBL puts 0V, and read MOS transistor 102 conductings this moment, and RWL charges to RBL by reading MOS transistor, because sensing circuit has clamping action, the electrical potential energy of RBL reaches 200mV, thereby can sense data " 0 ".When reading " 1 ", WWL puts 1V, and WBL puts 0V, writes MOS transistor 101 and turn-offs; The RWL biasing is read MOS transistor 102 this moment and is turn-offed less than 1V, and RWL can not charge to RBL by reading MOS transistor, and RBL keeps the 0V current potential, thereby can sense data " 1 ".

Operating list

From top read operation process as can be seen, equivalent parasitic capacitances does not discharge electric charge by writing MOS transistor, therefore to read degree low for its destructiveness, and its main destructiveness is read and is that on the one hand equivalent parasitic capacitances can discharge electric charge by the subthreshold value electric leakage of writing the MOS gate tube and the grid leak electricity of reading MOS transistor 120; The variation meeting that is the voltage of readout word line and sense bit line in the readout on the other hand influences the stable of equivalent parasitic electromotive force by the active area and the stray capacitance coupling between the grid of reading MOS transistor, but this influence is reversible, be that read operation finishes, influence also disappears.

Summary of the invention

The objective of the invention is to propose a kind of gain cell eDRAM, when this gain cell eDRAM can avoid the DRAM of prior art to be applied to programmable logic device (PLD), its refresh operation brought the problem of the state variation of switching tube.

Gain cell eDRAM provided by the invention, be used for configuration of programmable logic devices, it comprises reads MOS transistor, write MOS transistor, write word line, readout word line, write bit line, sense bit line and equivalent parasitic capacitances, the grid of writing MOS transistor is connected in write word line, drain terminal/source end of writing MOS transistor is connected in write bit line, source end/drain terminal of writing MOS transistor is connected in the stored charge end of described equivalent parasitic capacitances, the grid of reading MOS transistor is connected in the stored charge end of described equivalent parasitic capacitances, drain terminal/source end of reading MOS transistor is connected in sense bit line, source end/drain terminal of reading MOS transistor is connected in readout word line, and the stored charge end of described equivalent parasitic capacitances is controlled the switching tube of described programmable logic device (PLD).

Gain cell eDRAM provided by the invention, wherein, write word line, readout word line, write bit line and sense bit line all are connected with the Peripheral storage control circuit module, and read operation, write operation, data that described Peripheral storage control circuit module is used for ride gain unit eDRAM keep operation and refresh operation.Described equivalent parasitic capacitances comprises one of gate capacitance of the active area stray capacitance of writing MOS transistor, the gate capacitance of reading MOS transistor and switch mos transistor, perhaps is the combination of writing the gate capacitance of the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, switch mos transistor.Describedly read MOS transistor and write MOS transistor and can be nmos pass transistor, also can be the PMOS transistor.Described programmable logic device (PLD) is a field programmable gate array.Described switching tube can be nmos pass transistor or PMOS transistor.

As the preferred technique scheme, gain cell eDRAM also comprises phase inverter, and the input end of described phase inverter is connected with the stored charge end of described equivalent parasitic capacitances, and the output terminal of phase inverter is connected with the grid of the switching tube of described programmable logic device (PLD).Described equivalent parasitic capacitances is to write the active area stray capacitance of MOS transistor, read one of the gate capacitance of MOS transistor, gate capacitance of the MOS transistor in the phase inverter, perhaps is the combination of the gate capacitance of writing the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, the MOS transistor in the phase inverter.

Technique effect of the present invention is, the memory node of the gain cell eDRAM of this invention is controlled the switching tube of described programmable logic device (PLD), utilize this gain cell eDRAM not have that destructiveness is read or destructiveness is read features of smaller, in carrying out the refresh operation process, when carrying out read operation, the current potential of memory node do not change or potential change smaller, thereby can not influence the variation of the logic state of switching tube.Therefore the read operation process of this gain cell eDRAM can not cause the logic state mistake of programmable logic device (PLD), the contrast prior art, and the shadow memory of Zeng Jiaing can not dwindle the chip area of programmable logic device (PLD) greatly.

Description of drawings

Fig. 1 is the DRAM cellular construction synoptic diagram that is used for programmable logic device (PLD) of prior art.

Fig. 2 is the another DRAM cellular construction synoptic diagram that is used for programmable logic device (PLD) of prior art.

Fig. 3 is the gain cell eDRAM cellular construction synoptic diagram with two metal-oxide-semiconductors of prior art.

Fig. 4 is the structural representation of the first embodiment gain cell eDRAM provided by the invention.

Fig. 5 is the structural representation of the second embodiment gain cell eDRAM provided by the invention.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.

Figure 4 shows that the structural representation of an embodiment gain cell eDRAM provided by the invention.This embodiment gain cell eDRAM 300 is used for the config memory of programmable logic device (PLD), be used to control the conducting and the shutoff of its switching tube, switching tube is one of elementary cell of programmable logic device (PLD), and its logic state has reflected the programming state of programmable logic device (PLD).In this invention, programmable logic device (PLD) not only refers to PLD, also comprises the essentially identical programmable logic device (PLD) of principle such as FPGA.As shown in Figure 4, gain cell eDRAM 300 comprise write MOS transistor 301, read MOS transistor 302, write word line (Write Word Line, WWL) 305, readout word line (Read Word Line, RWL) 306, write bit line (WriteBit Line, WBL) 307, sense bit line (Read Bit Line, RBL) 308 and dotted line shown in equivalent parasitic capacitances 304.Because this electric capacity 304 that is used for stored charge is parasitic electric capacity, in its actual device architecture the capacitor element that independent physics exists, equivalent parasitic capacitances 304 is for to write the active area stray capacitance of MOS transistor 301 or to read the gate capacitance of MOS transistor 302 or the gate capacitance of switching tube 309, also or above three's combination; The concrete equivalent capacitance value size of equivalent parasitic capacitances 304 is not limited by the present invention, and it is relevant with the technology generations of making device MOS transistor device; Any electric capacity one end is the stored charge end, the other end is relative earth terminal, equivalent parasitic capacitances 304 is no exception, the one termination is low, other end stored charge, its stored charge end has reflected has stored logical message " 0 " or " 1 ", therefore will be defined as memory node with the direct-connected node 303 of stored charge end.The grid of writing MOS transistor 301 is connected in write word line 305, the drain terminal (or source end) of writing MOS transistor 301 is connected in write bit line 307, the source end (or drain terminal) of writing MOS transistor 301 is connected in the stored charge end of equivalent parasitic capacitances, also is memory node 303.If write MOS transistor 301 conductings, can be to equivalent parasitic capacitances 304 chargings or discharge.The grid of reading MOS transistor 302 is connected in the stored charge end of equivalent parasitic capacitances 304, also is memory node 303, and the drain terminal (perhaps source end) of reading MOS transistor is connected in sense bit line 308, and the source end (perhaps drain terminal) of reading MOS transistor is connected in readout word line 306; By the stored charge of memory node, can reflect the level of its memory node, thereby can control the conducting or the shutoff of reading metal-oxide-semiconductor 302.In this embodiment, read MOS transistor 302 and write MOS transistor 301 to be the PMOS transistor, turn-off when conducting when being its grid low level, high level, but its particular type is not limited by the present invention, read MOS transistor 302 and write MOS transistor 301 also can be nmos pass transistor, promptly turn-off when conducting during its grid high level, low level.

Continue as shown in Figure 4, provided to the property omitted the peripheral control circuit that is used for ride gain unit eDRAM 300, the write word line 305 of this gain cell eDRAM 300, write bit line 307, readout word line 306, sense bit line 308 are direct-connected with its Peripheral storage control circuit module 310, in concrete practical application, Peripheral storage control circuit module 310 comprises line decoder, column decoder, line decoder driving, column decoder driving, reading circuit module, write circuit module, address latch, logical sequence control module or the like.Write word line 305, write bit line 307, readout word line 306 and sense bit line 308 by 310 pairs of these gain cell eDRAMs 300 of storage control circuit module applies signal can carry out read operation, write operation, data to gain cell eDRAM 300 and keep operation and refresh operation or the like, in this embodiment, refresh operation also is the combination of two operating process of write-after-read.EDRAM operating process shown in Figure 3 was basic identical during its specific operation process and background technology were introduced.Need to prove especially, read current between write word line 308 and the readout word line 306 is by reading 302 of metal-oxide-semiconductor, and not by equivalent parasitic capacitances 304, equivalent parasitic capacitances 304 charge stored can remain unchanged substantially, the mainly subthreshold value electric leakage by writing MOS gate tube 301 of its charge stored, read the grid leak electricity of MOS transistor 302 and the grid leak electricity of switching tube discharges electric charge, therefore, its gain cell eDRAM does not have that destructiveness is read or destructiveness is read less.

Continue as shown in Figure 4, this gain cell eDRAM 300 is directly to be connected with the switching tube 309 of programmable logic device (PLD), the grid of switching tube 309 is directly connected in the memory node 303 of gain cell eDRAM 300, switching tube 309 is a nmos pass transistor in this embodiment, therefore, if gain cell eDRAM 300 is stored " 1 ", memory node is a high level, then switching tube 309 conductings, if gain cell eDRAM 300 storages " 0 ", memory node are low level, then switching tube 309 turn-offs.The logic state of switching tube 309 is directly controlled by gain cell eDRAM 300.In other embodiments, switching tube 309 also can be the PMOS transistor.

Comprehensive above Fig. 4 is described, as can be seen, this invention utilizes this gain cell eDRAM not have that destructiveness is read or destructiveness is read features of smaller, in carrying out the refresh operation process, when carrying out read operation, the current potential of memory node 303 do not change or potential change smaller, thereby can not influence the variation of the state of switching tube 309.Therefore the read operation process of this gain cell eDRAM can not cause the logic state mistake of programmable logic device (PLD).Do not need the shadow memory mentioned as in the prior art, can reduce the chip area of programmable logic device (PLD) greatly.

Figure 5 shows that the structural representation of another embodiment gain cell eDRAM provided by the invention.Comparison diagram 4 and Fig. 5 embodiment, its difference is that the gain cell eDRAM 400 of Fig. 5 embodiment comprises that also places the phase inverter between memory node and the switching tube.As shown in Figure 5, gain cell eDRAM 400 comprise write MOS transistor 401, read MOS transistor 402, write word line (Write Word Line, WWL) 405, readout word line (Read Word Line, RWL) 406, write bit line (Write Bit Line, WBL) 407, sense bit line (Read Bit Line, RBL) 408 and dotted line shown in equivalent parasitic capacitances 404.Because this electric capacity 404 that is used for stored charge is parasitic electric capacity, in its actual device architecture the capacitor element that independent physics exists, equivalent parasitic capacitances 404 is for writing the gate capacitance of metal-oxide-semiconductor in the active area stray capacitance of MOS transistor 301, the gate capacitance of reading MOS transistor 402 or the phase inverter 413, also or above three's combination; The concrete equivalent capacitance value size of equivalent parasitic capacitances 404 is not limited by the present invention, and it is relevant with the technology generations of making device MOS transistor device; Any electric capacity one end is the stored charge end, the other end is relative earth terminal, equivalent parasitic capacitances 404 is no exception, the one termination is low, other end stored charge, its stored charge end has reflected has stored logical message " 0 " or " 1 ", therefore will be defined as memory node with the direct-connected node 403 of stored charge end.The grid of writing MOS transistor 401 is connected in write word line 405, the drain terminal (or source end) of writing MOS transistor 401 is connected in write bit line 407, the source end (or drain terminal) of writing MOS transistor 401 is connected in the stored charge end of equivalent parasitic capacitances, also is memory node 403.If write MOS transistor 401 conductings, can be to equivalent parasitic capacitances 404 chargings or discharge.The grid of reading MOS transistor 402 is connected in the stored charge end of equivalent parasitic capacitances 404, also is memory node 403, and the drain terminal (perhaps source end) of reading MOS transistor is connected in sense bit line 408, and the source end (perhaps drain terminal) of reading MOS transistor is connected in readout word line 406; By the stored charge of memory node, can reflect the level of its memory node, thereby can control the conducting or the shutoff of reading metal-oxide-semiconductor 402.In this embodiment, read MOS transistor 402 and write MOS transistor 401 to be the PMOS transistor, turn-off when conducting when being its grid low level, high level, but its particular type is not limited by the present invention, read MOS transistor 402 and write MOS transistor 401 also can be nmos pass transistor, promptly turn-off when conducting during its grid high level, low level.

Continue as shown in Figure 5, provided to the property omitted the peripheral control circuit that is used for ride gain unit eDRAM 400, the write word line 405 of this gain cell eDRAM 400, write bit line 407, readout word line 406, sense bit line 408 are direct-connected with its Peripheral storage control circuit module 410, in concrete practical application, Peripheral storage control circuit module 410 comprises line decoder, column decoder, line decoder driving, column decoder driving, reading circuit module, write circuit module, address latch, logical sequence control module or the like.Write word line 405, write bit line 407, readout word line 406 and sense bit line 408 by 410 pairs of these gain cell eDRAMs 400 of storage control circuit module applies signal can carry out read operation, write operation, data to gain cell eDRAM 400 and keep operation or the like, in this embodiment, refresh operation also is the combination of two operating process of write-after-read.EDRAM operating process shown in Figure 3 was basic identical during its specific operation process and background technology were introduced.Need to prove especially, read current between write word line 408 and the readout word line 406 is by reading 402 of metal-oxide-semiconductor, and not by equivalent parasitic capacitances 404, equivalent parasitic capacitances 404 charge stored can remain unchanged substantially, the mainly subthreshold value electric leakage by writing MOS gate tube 401 of its charge stored, read the grid leak electricity of MOS transistor 402 and the transistorized grid leak electricity of phase inverter discharges electric charge, therefore, its gain cell eDRAM does not have that destructiveness is read or destructiveness is read less.

Continue as shown in Figure 5, this gain cell eDRAM 400 is to be connected with the switching tube 409 of programmable logic device (PLD), the grid of switching tube 409 is directly connected in the output terminal of the phase inverter 413 of gain cell eDRAM 400, the input end of phase inverter 413 directly is connected with memory node 403, switching tube 409 is a nmos pass transistor in this embodiment, therefore, if gain cell eDRAM 400 storages " 1 ", memory node are high level, then switching tube 409 turn-offs, if gain cell eDRAM 400 storages " 0 ", memory node are low level, then switching tube 409 conductings.The logic state of switching tube 409 is directly controlled by gain cell eDRAM 400.In other embodiments, switching tube 409 also can be the PMOS transistor.Phase inverter 413 can be the CMOS phase inverter.By between memory node 403 and switching tube 409, phase inverter 413 being set, the fluctuation of the electromotive force of memory node 403 can not have influence on the variation of high electronegative potential of the grid of switching tube 413 to a certain extent, guarantee the in stable condition of switching tube 120, so the destructiveness of the patient read operation process of the gain cell eDRAM of this embodiment is higher relatively.

Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.

Claims

1. gain cell eDRAM that is used for programmable logic device (PLD), comprise and read MOS transistor, write MOS transistor, write word line, readout word line, write bit line, sense bit line and equivalent parasitic capacitances, the grid of writing MOS transistor is connected in write word line, drain terminal/source end of writing MOS transistor is connected in write bit line, source end/drain terminal of writing MOS transistor is connected in the stored charge end of described equivalent parasitic capacitances, the grid of reading MOS transistor is connected in the stored charge end of described equivalent parasitic capacitances, drain terminal/source end of reading MOS transistor is connected in sense bit line, source end/drain terminal of reading MOS transistor is connected in readout word line, it is characterized in that the stored charge end of described equivalent parasitic capacitances is controlled the switching tube of described programmable logic device (PLD).

2. gain cell eDRAM according to claim 1, it is characterized in that, write word line, readout word line, write bit line and sense bit line all are connected with the Peripheral storage control circuit module, and read operation, write operation, data that described Peripheral storage control circuit module is used for ride gain unit eDRAM keep operation and refresh operation.

3. gain cell eDRAM according to claim 1, it is characterized in that, described equivalent parasitic capacitances is one of gate capacitance of writing the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, switching tube, perhaps is the combination of writing the gate capacitance of the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, switching tube.

4. gain cell eDRAM according to claim 1, it is characterized in that, also comprise phase inverter, the input end of described phase inverter is connected with the stored charge end of described equivalent parasitic capacitances, and the output terminal of phase inverter is connected with the grid of the switching tube of described programmable logic device (PLD).

5. gain cell eDRAM according to claim 4, it is characterized in that, described equivalent parasitic capacitances is to write the active area stray capacitance of MOS transistor, read one of the gate capacitance of MOS transistor, gate capacitance of the MOS transistor in the phase inverter, perhaps is the combination of the gate capacitance of writing the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, the MOS transistor in the phase inverter.

6. gain cell eDRAM according to claim 4 is characterized in that, described phase inverter is the CMOS phase inverter.

7. gain cell eDRAM according to claim 1 is characterized in that, describedly reads MOS transistor and writes MOS transistor and be nmos pass transistor.

8. gain cell eDRAM according to claim 1 is characterized in that, describedly reads MOS transistor and writes MOS transistor and be the PMOS transistor.

9. gain cell eDRAM according to claim 1 is characterized in that, described programmable logic device (PLD) is a field programmable gate array.

10. gain cell eDRAM according to claim 1 is characterized in that, described switching tube is nmos pass transistor or PMOS transistor.