CN101887748A - CAM/TCAM provided with shadow non-volatile memory - Google Patents
CAM/TCAM provided with shadow non-volatile memory Download PDFInfo
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Abstract
The invention discloses a CAM/TCAM provided with a shadow non-volatile memory, which belongs to the field of content addressable memories (Content Addressable Memory, CAM). The CAM/TCAM comprises a shadow non-volatile memory array which corresponds to data in a memory content addressable memory array according to an address relation so that the CAM/TCAM has the characteristic of non-volatile storage.
Description
Technical field
The invention belongs to content adressable memory (Content Addressable Memory, CAM) field, be specifically related to the content adressable memory of a kind of band shadow non-volatile storage array (Shadow Nonvolatile Memroy Array) or three-state content addressing memory (Ternary Content Addressable Memory, TCAM).
Background technology
Content adressable memory (CAM) is a kind of data according to outside input, outer input data is compared with the storage inside data then according to the storer of comparative result OPADD, and it is widely used in data retrieval, look-up table, data compression etc.
Content-addressed memory unit generally comprise memory function unit, comparing unit, word line (WordLine, WL), bit line (Bit Line), source line (Source Line, SL) and matched line (Match Line, ML).In the content-addressed memory unit of prior art, mainly with static RAM (SRAM) and dynamic RAM (DRAM) as the memory function unit.Generally speaking, two content-addressed memory units can be formed and form a three-state content addressing memory (TCAM), and it can support three kinds of logic states: 0,1 or X, and X promptly is not related to phychology (Don ' t care).
Figure 1 shows that the CAM cellular construction synoptic diagram based on SRAM of prior art, among this SRAM-TCAM, when the data of the data of importing among the BL (also being search data) and SRAM storage unit 21 storages are identical, two metal-oxide-semiconductors in the comparison module 22 all have a meeting to turn-off, the ML current potential is a high level, and matching result is instructed to; Otherwise, when the data of data of importing among the BL and 21 storages of DRAM storage unit are inequality, two equal conductings of metal-oxide-semiconductor in the comparison module 22, the ML current potential is a low level, Search Results does not match and is instructed to.
Figure 2 shows that the TCAM cellular construction synoptic diagram based on SRAM of prior art, this TCAM unit is to be combined by two CAM unit 11,12 shown in Figure 1, when wherein data " 0 " are stored in the CAM unit 12 on the CAM unit 11 storage data " 0 " on the left side, the right, represent this TCAM unit storage data " X "; During the CAM unit 12 storage data " 1 " on the CAM unit 11 storage data " 0 " on the left side, the right, represent this TCAM unit storage data " 1 "; During the CAM unit 12 storage data " 0 " on the CAM unit 11 storage data " 1 " on the left side, the right, represent this TCAM unit storage data " 0 "; During the CAM unit 12 storage data " 1 " on the CAM unit 11 storage data " 1 " on the left side, the right, representing this TCAM unit is failure mode.
Figure 3 shows that the CAM cellular construction synoptic diagram based on DRAM of prior art.When the data of the data of importing among the BL (also being search data) and DRAM storage unit 31 storages were identical, two metal-oxide-semiconductors in the comparison module 32 all had a meeting to turn-off, and the ML current potential is a high level, and matching result is instructed to; Otherwise, when the data of data of importing among the BL and 31 storages of DRAM storage unit are inequality, two equal conductings of metal-oxide-semiconductor in the comparison module 32, the ML current potential is a low level, the result that do not match is instructed to.
Figure 4 shows that the TCAM cellular construction synoptic diagram based on DRAM of prior art.This TCAM unit is to be combined by two CAM unit 13,14 shown in Figure 3, when wherein data " 0 " are stored in the CAM unit 14 on the CAM unit 13 storage data " 0 " on the left side, the right, represents this TCAM unit storage data " X "; During the CAM unit 14 storage data " 1 " on the CAM unit 13 storage data " 0 " on the left side, the right, represent this TCAM unit storage data " 1 "; During the CAM unit 14 storage data " 0 " on the CAM unit 13 storage data " 1 " on the left side, the right, represent this TCAM unit storage data " 0 "; During the CAM unit 14 storage data " 1 " on the CAM unit 13 storage data " 1 " on the left side, the right, representing this TCAM unit is failure mode.
Compare Fig. 1, the CAM/TCAM unit based on SRAM shown in Figure 2, Fig. 3, the CAM/TCAM unit based on DRAM shown in Figure 4 have the advantage that speed is faster, energy consumption is littler, cellar area is little.But we also notice that the electric capacity in the DRAM storage unit in the CAM/TCAM unit needs dynamically to keep refresh operation to store data, and is used for the peripheral circuit relative complex of refresh operation, has taken area of chip simultaneously.
Further, we can notice, more than shown in CAM/TCAM all have the characteristics of volatility (Volatile, outage back data do not keep) storage.
Summary of the invention
The technical problem to be solved in the present invention is to solve the problem based on the volatile storage among the CAM of SRAM and DRAM of prior art.
For solving the problems of the technologies described above, content adressable memory provided by the invention comprises address generator, the Content Addressable Memory array based on DRAM or SRAM, shadow non-volatile memory array, the address signal that described address generator produces inputs to Content Addressable Memory array or shadow non-volatile memory array, and the shadow non-volatile memory array is according to the data in the address relationship corresponding stored Content Addressable Memory array.
According to content adressable memory provided by the invention, wherein, described address generator, be integrated on the same chip based on Content Addressable Memory array, the shadow non-volatile memory array of DRAM or SRAM.The memory cell of described shadow non-volatile memory array can be EEPROM, FLASH, phase transition storage, magnetoresistive RAM, ferroelectric memory or resistance random access memory.
According to content adressable memory provided by the invention, in embodiment based on the Content Addressable Memory array of SRAM, based on the content addressable memory (CAM) cell of the Content Addressable Memory array of SRAM comprise six pipe SRAM storage unit and place matched line and ground between two comparing units.Described SRAM storage unit comprises first phase inverter and second phase inverter and two the 3rd metal-oxide-semiconductors that four metal-oxide-semiconductor equivalences are formed, and the two ends of phase inverter respectively are connected in bit line by one the 3rd metal-oxide-semiconductor, control the conducting or the shutoff of the 3rd metal-oxide-semiconductor by word line; Described comparing unit comprises first metal-oxide-semiconductor and second metal-oxide-semiconductor of series connection, the conducting or the shutoff of control of Electric potentials first metal-oxide-semiconductor at the two ends of described phase inverter, the conducting or the shutoff of control of Electric potentials second metal-oxide-semiconductor of source line.The memory cell of described shadow non-volatile memory array is the phase transition storage that comprises phase change memory resistance and MOS gate tube, one end of described phase inverter by bit line BL be connected in a phase-changing memory unit, the other end is connected in another phase-changing memory unit by bit line BL, described phase-changing memory unit is used for the current potential at corresponding stored phase inverter two ends.When described phase change memory resistance is high-impedance state, represent phase-changing memory unit storage data " 1 ", the bit line that is connected with phase-changing memory unit is put noble potential; When described phase change memory resistance is low resistance state, represent phase-changing memory unit storage data " 0 ", the bit line that is connected with phase-changing memory unit is put electronegative potential.Described Content Addressable Memory array and described shadow non-volatile memory array based on SRAM realized write operation by the input signal of common line decoder and column decoder.
The present invention provides a kind of three-state content addressing memory simultaneously, it comprises address generator, the three-state content addressing memory array based on DRAM or SRAM, shadow non-volatile memory array, the address signal that described address generator produces inputs to three-state content addressing memory array or shadow non-volatile memory array, and the shadow non-volatile memory array is according to the data in the address relationship corresponding stored Content Addressable Memory array.
According to three-state content addressing memory provided by the invention, wherein, described address generator, be integrated on the same chip based on three-state content addressing memory array, the shadow non-volatile memory array of DRAM or SRAM.The memory cell of described shadow non-volatile memory array is one of EEPROM, FLASH, phase transition storage, magnetoresistive RAM, ferroelectric memory, resistance random access memory.
According to three-state content addressing memory provided by the invention, in embodiment based on the three-state content addressing memory array of DRAM, based on the content addressable memory (CAM) cell of the Content Addressable Memory array of DRAM comprise two DRAM storage unit and place matched line and ground between two comparing units.Described DRAM storage unit comprises one the 4th MOS gate tube and an electric capacity, controls the conducting or the shutoff of the 4th metal-oxide-semiconductor by word line; Described comparing unit comprises first metal-oxide-semiconductor and second metal-oxide-semiconductor of series connection, the conducting or the shutoff of control of Electric potentials first metal-oxide-semiconductor of the non-earth terminal of described electric capacity, the conducting or the shutoff of control of Electric potentials second metal-oxide-semiconductor of source line.The memory cell of described shadow non-volatile memory array is the phase transition storage that comprises phase change memory resistance and MOS gate tube, the non-earth terminal of the electric capacity of described DRAM unit is connected in phase-changing memory unit by bit line, and described phase-changing memory unit is used for the current potential of the non-earth terminal of corresponding stored electric capacity.When described phase change memory resistance is high-impedance state, represent phase-changing memory unit storage data " 1 ", the bit line that is connected with phase-changing memory unit is put noble potential; When described phase change memory resistance is low resistance state, represent phase-changing memory unit storage data " 0 ", the bit line that is connected with phase-changing memory unit is put electronegative potential.Described three-state content addressing memory array and described shadow non-volatile memory array based on DRAM realized data write operation by the input signal of common line decoder and column decoder.Wherein, the electric capacity among the described DRAM is parasitic equivalent capacity; Gate capacitance or diffusion capacitance that described parasitic equivalent capacity is the 4th MOS gate tube.With respect to embodiment, have little, low in energy consumption, the fireballing characteristics of chip area based on the embodiment of the three-state content addressing memory array of DRAM based on the three-state content addressing memory array of SRAM.
Technique effect of the present invention is that CAM provided by the invention or TCAM by increasing the shadow non-volatile storage array, make the CAM of this invention or TCAM have non-volatile storage characteristics.
Description of drawings
Fig. 1 is the CAM cellular construction synoptic diagram based on SRAM of prior art;
Fig. 2 is the TCAM cellular construction synoptic diagram based on SRAM of prior art;
Fig. 3 is the CAM cellular construction synoptic diagram based on DRAM of prior art;
Fig. 4 is the TCAM cellular construction synoptic diagram based on DRAM of prior art;
Fig. 5 is the embodiment schematic block diagram of three-state content addressing memory provided by the invention;
Fig. 6 is the annexation synoptic diagram of DRAM-TCAM unit and phase-changing memory unit;
Fig. 7 is the tabulation of the write operation of TCAM embodiment illustrated in fig. 6
Fig. 8 is the tabulation of the read operation of TCAM embodiment illustrated in fig. 6
Fig. 9 is the tabulation of the addressing operation of TCAM embodiment illustrated in fig. 6
Figure 10 is the another embodiment synoptic diagram of the annexation of DRAM-TCAM unit and phase-changing memory unit;
Figure 11 is the embodiment schematic block diagram of content adressable memory provided by the invention;
Figure 12 is the annexation synoptic diagram of SRAM-CAM unit and phase-changing memory unit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Figure 5 shows that the embodiment schematic block diagram of three-state content addressing memory provided by the invention.Block diagram as shown in Figure 5, this three-state content addressing memory 100 mainly comprise address generator 110, based on TCAM array 120 and the shadow non-volatile memory array (Shadow Nonvolatile Memory Array) 130 of DRAM or SRAM.Based on the TCAM array of DRAM is to be arranged with the form of row and column by the storage unit shown in Fig. 4 (TCAM unit) of background technology to form, is to be formed by the form arrangement of the storage unit shown in Fig. 2 (TCAM unit) of background technology with row and column based on the TCAM array of SRAM.Shadow non-volatile memory array 130 can be that various non-volatile memory units such as EEPROM, FLASH, phase transition storage (Phase Change Memory), magnetoresistive RAM (Magnetic Random Access Memory), ferroelectric memory (Ferroelectronics Memory), resistance random access memory (Resistive Random Access Memory) are arranged the array that forms.Shadow non-volatile memory array 130 is according to the data in the address relationship corresponding stored TCAM array 120, be the data that write the TCAM array stores in the shadow non-volatile memory array 130 by the address, for example, two data of storage among the DRAM of certain the TCAM unit in the TCAM array, these two data are stored in equally respectively in two memory cells of corresponding address in the shadow non-volatile memory array.Address generator 110, be integrated on the same chip by SOC (System On Chip) technology based on TCAM array 120, the shadow non-volatile memory array 130 of DRAM or SRAM.
In this embodiment, with the nonvolatile memory in the shadow non-volatile memory array 130 is that phase transition storage is an example, Figure 6 shows that the annexation synoptic diagram of DRAM-TCAM unit and phase-changing memory unit, wherein the DRAM-TCAM unit is the unit in the TCAM array 130 of TCAM shown in Figure 5, and phase-changing memory unit is the unit in the shadow non-volatile memory array 120 shown in Figure 5.As shown in Figure 6, the DRAM-TCAM unit comprises two DRAM storage unit 41a, 41b and two comparing unit 42a, 42b, the grid of the MOS gate tube 413 among the MOS gate tube 411 among the DRAM storage unit 41a and the DRAM storage unit 41b all is connected with same word line simultaneously, comparing unit comprises first metal-oxide-semiconductor (being arranged in more top among the figure) and second metal-oxide-semiconductor (figure is positioned at more following), first metal-oxide-semiconductor and second metal-oxide-semiconductor are connected in series, the grid of first metal-oxide-semiconductor is connected with the non-earth terminal of the electric capacity of DRAM storage unit, the grid of second metal-oxide-semiconductor is connected with the source line, wherein second metal-oxide-semiconductor of 42a is connected in BL, and second metal-oxide-semiconductor of 42b is connected in
43a, 43b are two phase-changing memory units in the shadow non-volatile memory array; Each phase-changing memory unit comprises a phase change memory resistance (among the figure 431 or 433) and MOS gate tube (among the figure 432 or 434), and wherein the grid of MOS gate tube 432,434 all is connected in the same word line shown in the figure simultaneously; The phase change memory resistance that is connected in series with the MOS gate tube be connected in the bit line shown in the figure (BL or
).The data of phase-changing memory unit 43a storage are corresponding identical with the data of the 41a storage of DRAM-TCAM unit, and the data of phase-changing memory unit 43b storage are corresponding identical with the data of the 41b storage of DRAM-TCAM unit.
In conjunction with Fig. 5 and shown in Figure 6, the function of the content adressable memory of this embodiment is described.When this content adressable memory receives external command, the address command that address generator 110 produces can input to shadow non-volatile memory array 120 and Content Addressable Memory array 130 simultaneously, thereby on the storage unit correspondence of the storage unit of certain address in can Content Addressable Memory array 130 and certain address of shadow non-volatile memory array 120, on phase-changing memory unit for example shown in Figure 6 and the DRAM-TCAM unit correspondence.Content adressable memory shown in Figure 5 also comprises line decoder and column decoder (not illustrating among Fig. 5 to provide), be used for shadow non-volatile memory array 120 and Content Addressable Memory array 130 are write data, for example, the data of phase-changing memory unit 43a shown in Figure 4 and DRAM storage unit 41a storage write identical data, and phase-changing memory unit 43b and DRAM unit 41b write identical data.Need the data of search input to input to cam array, from the ML of cam array, export matching result from SL or SL.
Figure 7 shows that the tabulation of the write operation of this embodiment TCAM, wherein data 1 are the stored data states of DRAM unit 41a, data 2 are the stored data states of DRAM unit 41b, when data 1, data 2 all write data " 0 ", when " 0 ", be " being not related to phychology (Don ' t care) ", when data 1, data 2 write data " 0 " respectively, when " 1 ", this TCAM unit is stored as " 0 ", when data 1, data 2 write data " 1 " respectively, when " 0 ", this TCAM unit is stored as " 1 ", when data 1, data 2 write data " 1 " respectively, when " 1 ", this TCAM unit is stored as " failure mode (Invalid Mode) ", and this attitude is not used.
Figure 8 shows that the tabulation of the read operation of this embodiment TCAM, to DRAM unit 41a, 41b applies the read operation signal, work as 41a, the data that 41b reads respectively are " 0 ", when " 0 ", be " being not related to phychology (Don ' t care) ", work as 41a, the data that 41b reads respectively are " 0 ", when " 1 ", this TCAM unit is stored as " 0 ", work as 41a, the data that 41b reads respectively are " 1 ", when " 0 ", this TCAM unit is stored as " 1 ", work as 41a, the data that 41b reads respectively are " 1 ", when " 1 ", this TCAM unit is stored as " failure mode (Invalid Mode) ".
Figure 9 shows that the tabulation of the addressing operation of this embodiment TCAM, when being " H " with the level of ML shown in Figure 6, expression " coupling " when the level of ML is " L ", is represented " not matching ".For example, when if the data that DRAM unit 41a, 41b store respectively are " 0 ", " 1 ", these TCAM unit actual storage data are " 0 ", when from SL input target data " 0 ", the data of SL input are " 1 ", and data 1, data 2 are respectively " 0 ", " 1 ", comparing unit 42a and 42b all have a not conducting of metal-oxide-semiconductor, thereby ML puts high level, and the data of input are identical with the data of this TCAM unit storage, thereby can finish addressing operation; On the contrary, when from SL input target data " 1 ", ML puts low level,, the data of the data of input and the storage of this TCAM unit are inequality.Therefore, in comprehensive above-mentioned reading and writing, the addressing operation process, phase-changing memory unit 43a, 43b in itself and the shadow non-volatile storage array are uncorrelated, so the existence of shadow non-volatile storage array does not influence the storage operation process of TCAM storage array.
Outside above reading and writing, addressing operation process, need ceaselessly electric capacity 413 or 414 in the DRAM unit ceaselessly to be refreshed to make it keep current potential, for example, when DRAM unit 41a storage data are " 1 ", need refresh electric capacity 413 and make it remain on noble potential.Because the data with DRAM unit 41a, DRAM unit 41b storage are identical respectively to data that two cell stores 43a, 43b storages should be arranged in the shadow memory array, when WL puts high level, make 411,412,431,433 conductings of MOS gate tube, when DRAM unit 41a storage data are " 1 ", phase change memory resistance 431 is also stored data " 1 ", the point that BL connects phase change memory resistance 431 places noble potential, the non-earth terminal of electric capacity 413 is also put noble potential, therefore, can refresh electric capacity 413 makes it keep noble potential.Therefore, the current potential of the non-earth terminal of the electric capacity of phase-changing memory unit corresponding stored DRAM can carry out refresh operation to electric capacity again after the DRAM power down.In like manner, also can refresh electric capacity 414 by phase-changing memory unit 43b makes it keep noble potential.The reading and writing that the refresh process of DRAM does not influence among this embodiment, addressing operation process, and the peripheral circuit refresh operation process of passing through that its refresh operation process is traditional relatively realizes simple, and the face that can reduce this content adressable memory chip connects and reduces its power consumption.Simultaneously, with respect to traditional DRAM-TCAM shown in Figure 4, it is after power down, though the data among DRAM unit 41a, the 41b do not keep, but because the data among 43a, the 43b continue to keep in the phase-changing memory unit, can be by recovering the refresh operation after the energising, the storage data among DRAM unit 41a, the 41b are brushed back data mode before the power down, therefore, the TCAM of this inventive embodiments has non-volatile storage characteristics.
Figure 10 shows that the another embodiment synoptic diagram of the annexation of DRAM-TCAM unit and phase-changing memory unit, wherein the DRAM-TCAM unit is the unit in the TCAM array 130 of TCAM shown in Figure 5, and phase-changing memory unit is the unit in the shadow non-volatile memory array 120 shown in Figure 5.This embodiment and the key distinction embodiment illustrated in fig. 6 are, in the cam array among DRAM-TCAM unit 41a, the 41b, all include only a MOS gate tube, the electric capacity of the DRAM unit among Fig. 6 replaces with the stray capacitance of MOS gate tube, stray capacitance can be the gate capacitance of metal-oxide-semiconductor or diffusion capacitance etc., can be the combination of gate capacitance, diffusion capacitance parasitism, the particular type of electric capacity not be limited by the present invention yet.The specific operation process of content adressable memory that comprises structure embodiment illustrated in fig. 10 is identical with the content adressable memory that comprises structure embodiment illustrated in fig. 6, in the prior art, usually the capacitance size of the stray capacitance in Figure 10 structure may be less than the capacitance of the capacitor element shown in Fig. 6, but we can be by improving WL selected frequencies (putting the frequency of high level), raising makes the DRAM-TCAM unit keep the storage data stabilization to the refresh operation frequency of stray capacitance.Structure shown in Figure 10 has structure characteristic of simple more with respect to structure shown in Figure 6.
Figure 11 shows that the embodiment schematic block diagram of content adressable memory provided by the invention.Three-state content addressing memory (TCAM) structure is more simple relatively for content adressable memory (CAM), generally forms a TCAM unit by two CAM unit.Block diagram as shown in figure 11, this content adressable memory 200 mainly comprise address generator 210, based on cam array 220 and the shadow non-volatile memory array (Shadow Nonvolatile Memory Array) 230 of DRAM or SRAM.Based on the cam array of DRAM is to be arranged with the form of row and column by the storage unit shown in Fig. 3 (CAM unit) of background technology to form, is to be formed by the form arrangement of the storage unit shown in Fig. 1 (CAM unit) of background technology with row and column based on the cam array of SRAM.Shadow non-volatile memory array 230 can be that various non-volatile memory units such as EEPROM, FLASH, phase transition storage (Phase Change Memory), magnetoresistive RAM (Magnetic Random Access Memory), ferroelectric memory (Ferroelectronics Memory), resistance random access memory (Resistive Random Access Memory) are arranged the array that forms.Shadow non-volatile memory array 230 is according to the data in the address relationship corresponding stored cam array 220, be the data that write the cam array storage in the shadow non-volatile memory array 230 by the address, for example, data of storage in certain CAM unit in the cam array, these data are not stored in the memory cell of corresponding address in the shadow non-volatile memory array equally.Address generator 210, be integrated on the same chip by SOC (System On Chip) technology based on cam array 220, the shadow non-volatile memory array 230 of DRAM or SRAM.
Figure 11 shows that the annexation synoptic diagram of SRAM-CAM unit and phase-changing memory unit, wherein the SRAM-CAM unit is the unit in the cam array 230 of CAM shown in Figure 10, and phase-changing memory unit is the unit in the shadow non-volatile memory array 220 shown in Figure 10.As shown in figure 10, the SRAM-CAM unit comprises SRAM storage unit 51 and two comparing unit 52a, 52b of one six pipe, two phase inverters 511 that comprise in the SRAM storage unit 51 that four metal-oxide-semiconductors form and 512, can corresponding stored " 0 " or " 1 ", the grid correspondence of the metal-oxide-semiconductor 513,514 in the SRAM storage unit 51 is connected in WL.The SRAM-CAM unit also comprises two comparing unit 52a, 52b, comparing unit 52a comprises first metal-oxide-semiconductor 521 and second metal-oxide-semiconductor 522, comparing unit 52b comprises first metal-oxide-semiconductor 523 and second metal-oxide-semiconductor 524, be connected in series between first metal-oxide-semiconductor and second metal-oxide-semiconductor, the grid of first metal-oxide-semiconductor 521 is connected in the output terminal of phase inverter 511, the input end of phase inverter 512, the grid of first metal-oxide-semiconductor 523 is connected in the input end of phase inverter 511, the output terminal of phase inverter 512, and the grid of second metal-oxide-semiconductor 522 is connected in
The grid of second metal-oxide-semiconductor 524 is connected in SL.53a, 53b are two phase-changing memory units in the shadow non-volatile memory array; Each phase-changing memory unit comprises a phase change memory resistance (among the figure 531 or 533) and MOS gate tube (among the figure 532 or 534), and wherein the grid of MOS gate tube 532,4534 all is connected in the same word line shown in the figure simultaneously; The phase change memory resistance that is connected in series with the MOS gate tube be connected in the bit line shown in the figure (BL or
).The left end of the phase inverter of SRAM storage unit 51 is that noble potential, right-hand member are " 1 " for electronegative potential interval scale storage data, and is same, and the left end of phase inverter is that electronegative potential, right-hand member are " 0 " for noble potential interval scale storage data.During phase-changing memory unit 53a storage data " 1 " (phase change resistor is a high-impedance state), representative is corresponding with the noble potential of the left end of phase inverter, during phase-changing memory unit 53a storage data " 0 " (phase change resistor is a high-impedance state), representative is corresponding with the electronegative potential of the left end of phase inverter; In like manner, during phase-changing memory unit 53b storage data " 1 " (phase change resistor is a high-impedance state), representative is corresponding with the noble potential of the right-hand member of phase inverter, and during phase-changing memory unit 53b storage data " 0 " (phase change resistor is a high-impedance state), representative is corresponding with the electronegative potential of the right-hand member of phase inverter.Realized the corresponding stored of phase-changing memory unit and SRAM-CAM unit like this.
Continue as shown in figure 12, during SRAM storage unit 51 storage data " 1 ", metal-oxide-semiconductor 523 is closed, 521 conductings, if the search data of importing from SL is " 1 ", metal-oxide-semiconductor 522 is closed, 524 conductings, thereby comparing unit 52a and 52b all close, ML puts high level, representative " coupling "; If the search data of importing from SL is " 0 ", metal-oxide-semiconductor 522 conductings, 524 are closed, thereby a conducting is arranged among comparing unit 52a and the 52b, and ML puts low level, representative " not matching ".According to the aforesaid operations principle, can finish the search addressing operation of SRAM-CAM unit.Concrete read and write operation is basic identical with traditional SRAM-CAM unit.But, it is to be noted, identical with traditional SRAM-CAM unit, can not preserve data equally after the SRAM-CAM unit power down in this cam array, but owing to store the current potential at the phase inverter two ends of SRAM by 53a, 53b in the shadow non-volatile storage array, after restoring electricity, can recover the current potential at phase inverter two ends, thereby recover the storage data among the SRAM by phase-changing memory unit 53a, 53b.Therefore, the CAM of this inventive embodiments has non-volatile storage characteristics.Based on the cam array of SRAM relatively based on the cam array of DRAM, because the relative DRAM complex structure of sram cell, area are bigger, ML in the storage array of same memory capacity relatively can be longer, the dead resistance, the stray capacitance that further cause ML and produced are bigger, thereby on the speed power consumption, be better than cam array relatively based on SRAM based on the cam array of DRAM; There is not the leakage problem among the SRAM in DRAM in addition, makes based on the cam array of DRAM relatively littler based on the cam array of SRAM on power consumption yet.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.
Claims (18)
1. content adressable memory, it is characterized in that, comprise address generator, Content Addressable Memory array, shadow non-volatile memory array based on DRAM or SRAM, the address signal that described address generator produces inputs to Content Addressable Memory array or shadow non-volatile memory array, and the shadow non-volatile memory array is according to the data in the address relationship corresponding stored Content Addressable Memory array.
2. content adressable memory according to claim 1 is characterized in that, described address generator, is integrated on the same chip based on Content Addressable Memory array, the shadow non-volatile memory array of DRAM or SRAM.
3. content adressable memory according to claim 1 is characterized in that, the content addressable memory (CAM) cell of described Content Addressable Memory array based on SRAM comprise six pipe SRAM storage unit and place matched line and ground between two comparing units.
4. content adressable memory according to claim 3, it is characterized in that, described SRAM storage unit comprises first phase inverter and second phase inverter and two the 3rd metal-oxide-semiconductors that four metal-oxide-semiconductor equivalences are formed, the two ends of phase inverter respectively are connected in bit line by one the 3rd metal-oxide-semiconductor, control the conducting or the shutoff of the 3rd metal-oxide-semiconductor by word line; Described comparing unit comprises first metal-oxide-semiconductor and second metal-oxide-semiconductor of series connection, the conducting or the shutoff of control of Electric potentials first metal-oxide-semiconductor at the two ends of described phase inverter, the conducting or the shutoff of control of Electric potentials second metal-oxide-semiconductor of source line.
5. content adressable memory according to claim 4, it is characterized in that, the memory cell of described shadow non-volatile memory array is the phase transition storage that comprises phase change memory resistance and MOS gate tube, and an end of described phase inverter is connected in phase-changing memory unit, an other end by bit line BL and passes through bit line
Be connected in another phase-changing memory unit, described phase-changing memory unit is used for the current potential at corresponding stored phase inverter two ends.
6. content adressable memory according to claim 5 is characterized in that, when described phase change memory resistance is high-impedance state, represents phase-changing memory unit storage data " 1 ", and the bit line that is connected with phase-changing memory unit is put noble potential; When described phase change memory resistance is low resistance state, represent phase-changing memory unit storage data " 0 ", the bit line that is connected with phase-changing memory unit is put electronegative potential.
7. content adressable memory according to claim 3 is characterized in that, described Content Addressable Memory array and described shadow non-volatile memory array based on SRAM realized write operation by the input signal of common line decoder and column decoder.
8. content adressable memory according to claim 1, it is characterized in that the memory cell of described shadow non-volatile memory array is one of EEPROM, FLASH, phase transition storage, magnetoresistive RAM, ferroelectric memory, resistance random access memory.
9. three-state content addressing memory, it is characterized in that, comprise address generator, three-state content addressing memory array, shadow non-volatile memory array based on DRAM or SRAM, the address signal that described address generator produces inputs to three-state content addressing memory array or shadow non-volatile memory array, and the shadow non-volatile memory array is according to the data in the address relationship corresponding stored Content Addressable Memory array.
10. three-state content addressing memory according to claim 9 is characterized in that, described address generator, is integrated on the same chip based on three-state content addressing memory array, the shadow non-volatile memory array of DRAM or SRAM.
11. three-state content addressing memory according to claim 9, it is characterized in that, based on the content addressable memory (CAM) cell of the Content Addressable Memory array of DRAM comprise two DRAM storage unit and place matched line and ground between two comparing units.
12. three-state content addressing memory according to claim 11 is characterized in that, described DRAM storage unit comprises one the 4th MOS gate tube and an electric capacity, controls the conducting or the shutoff of the 4th metal-oxide-semiconductor by word line; Described comparing unit comprises first metal-oxide-semiconductor and second metal-oxide-semiconductor of series connection, the conducting or the shutoff of control of Electric potentials first metal-oxide-semiconductor of the non-earth terminal of described electric capacity, the conducting or the shutoff of control of Electric potentials second metal-oxide-semiconductor of source line.
13. three-state content addressing memory according to claim 12, it is characterized in that, the memory cell of described shadow non-volatile memory array is the phase transition storage that comprises phase change memory resistance and MOS gate tube, the non-earth terminal of the electric capacity of described DRAM unit is connected in phase-changing memory unit by bit line, and described phase-changing memory unit is used for the current potential of the non-earth terminal of corresponding stored electric capacity.
14. three-state content addressing memory according to claim 13 is characterized in that, when described phase change memory resistance is high-impedance state, represents phase-changing memory unit storage data " 1 ", the bit line that is connected with phase-changing memory unit is put noble potential; When described phase change memory resistance is low resistance state, represent phase-changing memory unit storage data " 0 ", the bit line that is connected with phase-changing memory unit is put electronegative potential.
15. three-state content addressing memory according to claim 13, it is characterized in that described three-state content addressing memory array and described shadow non-volatile memory array based on DRAM realized data write operation by the input signal of common line decoder and column decoder.
16. three-state content addressing memory according to claim 12 is characterized in that, described electric capacity is parasitic equivalent capacity.
17. three-state content addressing memory according to claim 16, gate capacitance or diffusion capacitance that described parasitic equivalent capacity is the 4th MOS gate tube.
18. three-state content addressing memory according to claim 9, it is characterized in that the memory cell of described shadow non-volatile memory array is one of EEPROM, FLASH, phase transition storage, magnetoresistive RAM, ferroelectric memory, resistance random access memory.
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| CN2009100511326A CN101887748A (en) | 2009-05-13 | 2009-05-13 | CAM/TCAM provided with shadow non-volatile memory |
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| CN2009100511326A CN101887748A (en) | 2009-05-13 | 2009-05-13 | CAM/TCAM provided with shadow non-volatile memory |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102541462A (en) * | 2010-12-28 | 2012-07-04 | 上海芯豪微电子有限公司 | Broadband read-write memory device |
| CN108199969A (en) * | 2017-12-22 | 2018-06-22 | 大连理工大学 | Type of tabling look-up hardware search engine |
| CN108615812A (en) * | 2018-05-14 | 2018-10-02 | 浙江大学 | A kind of three-state content addressing memory based on memory diode |
| CN109887536A (en) * | 2019-02-13 | 2019-06-14 | 上海新储集成电路有限公司 | A kind of non-volatile memory cell structure |
| CN114758695A (en) * | 2022-04-06 | 2022-07-15 | 北京大学 | Method for realizing multi-value content addressable memory MCAM based on ferroelectric tunneling field effect transistor FeTFET |
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2009
- 2009-05-13 CN CN2009100511326A patent/CN101887748A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102541462A (en) * | 2010-12-28 | 2012-07-04 | 上海芯豪微电子有限公司 | Broadband read-write memory device |
| CN108199969A (en) * | 2017-12-22 | 2018-06-22 | 大连理工大学 | Type of tabling look-up hardware search engine |
| CN108199969B (en) * | 2017-12-22 | 2020-09-29 | 大连理工大学 | Look-up type hardware search engine |
| CN108615812A (en) * | 2018-05-14 | 2018-10-02 | 浙江大学 | A kind of three-state content addressing memory based on memory diode |
| CN109887536A (en) * | 2019-02-13 | 2019-06-14 | 上海新储集成电路有限公司 | A kind of non-volatile memory cell structure |
| CN114758695A (en) * | 2022-04-06 | 2022-07-15 | 北京大学 | Method for realizing multi-value content addressable memory MCAM based on ferroelectric tunneling field effect transistor FeTFET |
| CN114758695B (en) * | 2022-04-06 | 2024-05-17 | 北京大学 | Method for realizing multi-value content addressable memory MCAM based on ferroelectric tunneling field effect transistor FeTFET |
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