CN101923890B

CN101923890B - Gain unit eDRAM for programmable logic device

Info

Publication number: CN101923890B
Application number: CN200910052912A
Authority: CN
Inventors: 林殷茵; 薛晓勇
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2009-06-11
Filing date: 2009-06-11
Publication date: 2012-09-05
Anticipated expiration: 2029-06-11
Also published as: CN101923890A

Abstract

The invention belongs to the technical field of an embedded dynamic random memory (eDRM), in particular to a gain unit eDRAM for a programmable logic device. An isolated MOS (Metal Oxide Semiconductor) tube is additionally arranged between a storage node and the grid electrode of a switching tube of the gain unit eDRAM provided by the invention. After the isolated MOS tube is additionally arranged, the electric potential of the storage node fluctuates and can not be directly transmitted to the grid electrode of the switching tube. Therefore, the switching tube of the programmable logic device controlled by the gain unit eDRAM has stable state and is not influenced by the refreshing operation of the gain unit eDRAM.

Description

A kind of gain cell eDRAM that is used for PLD

Technical field

The invention belongs to embedded DRAM (eDRAM) technical field, be specifically related to a kind of gain unit (Gain Cell) eDRAM that is used for PLD.

Background technology

PLD is the abbreviation of PLD (Programable Logic Device); FPGA is the abbreviation of field programmable gate array (Field Programable Gate Array); Both functions are basic identical, realize that just principle is slightly different, so in the prior art; Sometimes can ignore the two difference, PLD and FPGA are referred to as PLD.PLD can be accomplished the function of any digital device, goes up to high-performance CPU, down to simple 74 circuit, can realize with PLD.PLD is as a blank sheet of paper or a pile building blocks, and the slip-stick artist can be through traditional schematic diagram input method, or hardware description language designs a digital display circuit freely.Through software emulation, can verify the correctness of design in advance.After PCB accomplishes, can also utilize the online modification ability of PLD, modification at any time designs and needn't change hardware circuit.Use PLD to develop digital circuit, can shorten design time greatly, reduce the PCB area, improve the reliability of system.These advantages of PLD make the PLD technology after the nineties, obtain development at full speed, have also promoted the progress of eda software and hardware description language (HDL) simultaneously greatly.

PLD or FPGA PLD include a plurality of MOS switching tubes and the storer that is used to control the MOS switching tube; In the prior art, at first, propose to adopt SRAM as config memory; SRAM is used to control the MOS switching tube of PLD, and it has low in energy consumption, fireballing characteristics.Further,, require its area more and more littler, therefore proposed to adopt DRAM to replace the storer of SRAM, conduct control MOS switching tube along with the development of PLD.

The U.S. Patent number that Xilinx company proposes is to point out in the United States Patent (USP) of US6137714; Be used to control the traditional capacitor element of DRAM memory employing stray capacitance replacement of MOS switching tube; Avoid the complicated shortcoming of manufacturing process of the relative PLD of manufacturing process of capacitor element, and further reduced the shared area of memory portion.Shown in Figure 1 for the DRAM cellular construction synoptic diagram that is used for PLD of prior art.As shown in Figure 1, DRAM unit 10 comprises that MOS gate tube 110, stray capacitance 111,112 are memory node; MOS gate tube 110 is through storage unit outside word line 140 its conductings of control or shutoff; The source end of MOS gate tube 110 connects the outside bit line 130 of storage unit; Word line 140, bit line 130 are connected with Peripheral storage control circuit module 150, through word line 140, bit line 130 and Peripheral storage control circuit module 150 control DRAM unit 10 read-write operations and refresh operations; The charge storage situation of memory node 112 reflection stray capacitances 111; Memory node 112 directly is connected with the grid of the switching tube 120 of PLD, therefore can be through the conducting and the shutoff of DRAM unit 10 CS pipes 120, for example; 10 storages " 1 " of DRAM unit; Switching tube 120 conductings, 10 storages " 0 " of DRAM unit, switching tube 120 turn-offs; Stray capacitance 111 comprises the electric capacity of the active area of the gate capacitance of switching tube 120 and the end that MOS gate tube 110 is connected with memory node 112.For this DRAM unit 10; Read or write or the process that keeps in; Stray capacitance 111 can especially in the read operation process, can discharge electric charge through the MOS gate tube 110 of conducting through the subthreshold value electric leakage of MOS gate tube 110 and the grid leak tele-release electric charge of switching tube 120; Therefore its read operation process is destructive, need constantly carry out refresh operation to the DRAM unit through Peripheral storage control circuit module 150.

Shown in Figure 2 for the another DRAM cellular construction synoptic diagram that is used for PLD of prior art.As shown in Figure 2, DRAM unit 20 comprises MOS gate tube 210, stray capacitance 211 and phase inverter 213; 212 is memory node, the stored charge of reflection stray capacitance 211, and memory node 212 directly is connected with the input end of phase inverter 213, and the output terminal of phase inverter 213 directly connects the grid of switching tube 120.Equally; MOS gate tube 210 is through storage unit outside word line 140 its conductings of control or shutoff; The source end of MOS gate tube 110 connects the outside bit line 130 of storage unit; Word line 140, bit line 130 are connected with Peripheral storage control circuit module 150, through word line 140, bit line 130 and Peripheral storage control circuit module 150 control DRAM unit 20 read-write operations and refresh operations; Read or write or the process that keeps in; Stray capacitance 211 can be through the subthreshold value electric leakage of MOS gate tube 210 and the grid leak tele-release electric charge of switching tube 120; Especially in the read operation process; Can discharge electric charges by the MOS gate tube 210 through conducting, so its read operation process is destructive, need constantly carries out refresh operation through Peripheral storage control circuit module 150 to the DRAM unit.Be different from DRAM unit part shown in Figure 1 and be to increase the phase inverter that is used to isolate, the fluctuation of the electromotive force of memory node 212 can not have influence on the variation of electromotive force of the grid of switching tube 120 to a certain extent like this, guarantees the in stable condition of switching tube 120.

But; More than the DRAM storage unit of embodiment illustrated in figures 1 and 2 when being applied to PLD; Its major defect is: read operation is destructive, is write-after-read during refresh operation, and stray capacitance discharges and recharges (read operation in the refresh operation process also is destructive) through the MOS gate tube to stray capacitance in its read operation process; This moment is because the potential change of stray capacitance can cause state variation (the conducting change shutoff of switching tube; Perhaps turn-off the change conducting, perhaps conducting shutoff degree dies down), the variation of this switching tube state can cause the logic state mistake of PLD.In the prior art; Overcome this shortcoming if desired, generally can adopt the content of another this DRAM unit of shadow memory corresponding storage, write shadow memory to the content of DRAM unit when refreshing with this DRAM unit; Shadow memory makes the switching tube state keep stable; This solution needs extra shadow memory, can increase chip area, and complicated operating process.

When being applied to PLD for solving DRAM among above Fig. 1 and Fig. 2, its refresh operation technical matters of bringing the logic state of switching tube to change, one Chinese patent application number has proposed to be applied to the thought of PLD with gain unit (Gain Cell) eDRAM in the patent of CN 2009100524843.See also Fig. 3, shown in Figure 3 is the structural representation of the gain cell eDRAM that is used for PLD of prior art.This gain cell eDRAM 300 is used for the config memory of PLD, is used to control the conducting and the shutoff of its switching tube.Gain cell eDRAM 300 comprise write MOS transistor 301, read MOS transistor 302, write word line (Write Word Line; WWL) 305, readout word line (Read Word Line; RWL) 306, write bit line (Write Bit Line; WBL) 307, sense bit line (Read BitLine, RBL) 308 and dotted line shown in equivalent parasitic capacitances 304.Any electric capacity one end is the stored charge end; The other end is relative earth terminal; Equivalent parasitic capacitances 304 is no exception, one of which end ground connection, other end stored charge; Its stored charge end has reflected has stored logical message " 0 " perhaps " 1 ", therefore will be defined as memory node with the direct-connected node 303 of stored charge end.The grid of writing MOS transistor 301 is connected in write word line 305; The drain terminal (or source end) of writing MOS transistor 301 is connected in write bit line 307; The source end (or drain terminal) of writing MOS transistor 301 is connected in the stored charge end of equivalent parasitic capacitances, also is memory node 303.If write MOS transistor 301 conductings, can 304 chargings of equivalent stray capacitance or discharge.The grid of reading MOS transistor 302 is connected in the stored charge end of equivalent parasitic capacitances 304, also is memory node 303, and the drain terminal (perhaps source end) of reading MOS transistor is connected in sense bit line 308, and the source end (perhaps drain terminal) of reading MOS transistor is connected in readout word line 306; Through the stored charge of memory node, can reflect the level of its memory node, thereby can control the conducting or the shutoff of reading metal-oxide-semiconductor 302.Utilize in this Chinese patent gain cell eDRAM 300 no destructivenesses read or destructiveness read features of smaller; In carrying out the refresh operation process; When carrying out read operation; The current potential of memory node 303 does not change, and perhaps potential change is smaller, thereby can not influence the variation of the state of switching tube 309.Therefore the refresh operation process (read procedure) of this gain cell eDRAM can not cause the logic state of PLD to change.

But; Please continue to consult Fig. 3, in the read operation process, RBL and RWL can apply certain voltage of reading; The current potential that active area and stray capacitance coupling grid between of the variation meeting of the voltage of readout word line and sense bit line through reading MOS transistor 302 influences equivalent parasitic capacitances 304 in the readout stable; Thereby make the potential fluctuation of memory node,, further still might cause the state variation of switching tube 309 if this stray capacitance coupling makes potential fluctuation excessive.Therefore, embodiment illustrated in fig. 3 in, this gain cell eDRAM still might cause the logic state of PLD to change in the refresh operation process.

Summary of the invention

The technical matters that the present invention will solve is, avoids in the refresh operation process of gain cell eDRAM, reads that the active area of MOS transistor and the stray capacitance coupling between the grid cause the potential fluctuation of memory node and the phenomenon that further causes the logic state of PLD to change.

For solving above technical matters, the gain cell eDRAM that is used for PLD provided by the invention, comprise read MOS transistor, write MOS transistor, write word line, readout word line, write bit line, sense bit line and equivalent parasitic capacitances; The grid of writing MOS transistor is connected in write word line; Drain terminal/source end of writing MOS transistor is connected in write bit line; Source end/drain terminal of writing MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; The grid of reading MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances, and drain terminal/source end of reading MOS transistor is connected in sense bit line, and source end/drain terminal of reading MOS transistor is connected in readout word line; Also comprise the isolation metal-oxide-semiconductor between the grid that places said equivalent parasitic capacitances and switching tube, the stored charge end of said equivalent parasitic capacitances is controlled the switching tube state of said PLD through isolating the metal-oxide-semiconductor transmission level.

According to gain cell eDRAM provided by the invention; Wherein, Said equivalent parasitic capacitances be write the active area stray capacitance of MOS transistor, read MOS transistor gate capacitance, isolate one of active area electric capacity of metal-oxide-semiconductor, perhaps for active area stray capacitance, the gate capacitance of reading MOS transistor of writing MOS transistor, isolate the combination of the active area electric capacity of metal-oxide-semiconductor.Said isolation metal-oxide-semiconductor is nmos pass transistor or PMOS transistor.Said PLD is a field programmable gate array.The gate electrode of said isolation metal-oxide-semiconductor is controlled by select lines; Said write word line, write bit line, readout word line, sense bit line and select lines receive the control of Peripheral storage control circuit module.

Therein among the embodiment, saidly write MOS transistor and read MOS transistor and be the PMOS transistor.

In another embodiment, saidly write MOS transistor and read MOS transistor and be nmos pass transistor.

Technique effect of the present invention is to compare with the prior art gain cell eDRAM, through between the grid of memory node and switching tube, increasing an isolation metal-oxide-semiconductor; In the refresh operation process, because the current potential that active area and stray capacitance coupling grid between of the variation meeting of the voltage of readout word line and sense bit line through reading MOS transistor influence memory node in the readout, the current potential of memory node is produced fluctuate; After isolating metal-oxide-semiconductor, the current potential of memory node produces the grid that fluctuation can't directly transfer to switching tube; Therefore, the switching tube of the PLD that this gain cell eDRAM is controlled in stable condition do not influenced by the refresh operation of gain cell eDRAM.

Description of drawings

Fig. 1 is the DRAM cellular construction synoptic diagram that is used for PLD of prior art;

Fig. 2 is the another DRAM cellular construction synoptic diagram that is used for PLD of prior art;

Fig. 3 is the structural representation of the gain cell eDRAM that is used for PLD of prior art;

Fig. 4 is the structural representation that is used for the gain cell eDRAM of PLD provided by the invention;

Shown in Figure 5 is the potential change synoptic diagram of the gain cell eDRAM of refresh operation process.

Embodiment

For making the object of the invention, technical scheme and advantage clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.

Shown in Figure 4 is the structural representation that is used for the gain cell eDRAM of PLD provided by the invention.This embodiment gain cell eDRAM 400 is used for the config memory of PLD, through the conducting and the shutoff of gain cell eDRAM 400 its switching tubes of control.Switching tube is one of elementary cell of PLD, and its state (conducting or shutoff) has reflected the programming state of PLD.In this invention, PLD not only refers to PLD, also comprises the essentially identical PLDs of principle such as FPGA.As shown in Figure 4; Gain cell eDRAM 400 comprise write MOS transistor 401, read MOS transistor 402, write word line (Write Word Line; WWL) 405, readout word line (ReadWord Line; RWL) 406, write bit line (Write Bit Line, WBL) 407, sense bit line (Read Bit Line, RBL) 408, isolate the equivalent parasitic capacitances 404 shown in metal-oxide-semiconductor and the dotted line.Because this electric capacity 404 that is used for stored charge is parasitic electric capacity; In its actual device architecture the capacitor element that independent physics exists; Equivalent parasitic capacitances 404 is for writing the active area stray capacitance of MOS transistor 401 or reading the gate capacitance of MOS transistor 402 or isolate the active area electric capacity of metal-oxide-semiconductor 413, also or above three's combination; The concrete equivalent capacitance value size of equivalent parasitic capacitances 404 is not limited by the present invention; It is relevant with the technology generations of making device MOS transistor device. and any electric capacity one end is the stored charge end, and the other end is relative earth terminal, and equivalent parasitic capacitances 404 is no exception; One of which end ground connection; Other end stored charge, logical message " 0 " perhaps " 1 " has been stored in its stored charge end reaction, therefore will be defined as memory node with the direct-connected node 403 of stored charge end.The grid of writing MOS transistor 401 is connected in write word line 405; The drain terminal (or source end) of writing MOS transistor 401 is connected in write bit line 407; The source end (or drain terminal) of writing MOS transistor 401 is connected in the stored charge end of equivalent parasitic capacitances, also is memory node 403.If write MOS transistor 401 conductings, can 404 chargings of equivalent stray capacitance or discharge.The grid of reading MOS transistor 402 is connected in the stored charge end of equivalent parasitic capacitances 404, also is memory node 403, and the drain terminal (perhaps source end) of reading MOS transistor is connected in sense bit line 408, and the source end (perhaps drain terminal) of reading MOS transistor is connected in readout word line 406; Through the stored charge of memory node, can reflect the level of its memory node, thereby can control the conducting or the shutoff of reading metal-oxide-semiconductor 402.In this embodiment; Reading MOS transistor 402 is the PMOS transistor with writing MOS transistor 401; Turn-off when conducting when being its grid low level, high level; But its particular type is not limited by the present invention, reads MOS transistor 402 and writes MOS transistor 401 and can be nmos pass transistor yet, the conducting when grid of nmos pass transistor connects high level, turn-offs when connecing low level.The source end (or drain terminal) of isolating metal-oxide-semiconductor 413 is connected in memory node 413, and its other drain terminal (or source end) is connected in the grid of the switching tube 409 of PLD, and the grid of isolating metal-oxide-semiconductor 413 receives select lines (Strobe Line) 414 controls; In this embodiment; Isolating metal-oxide-semiconductor 413 is the PMOS transistor, when select lines is high level, isolates metal-oxide-semiconductor and turn-offs; When select lines is low level, isolate the metal-oxide-semiconductor conducting.In other embodiments, isolate metal-oxide-semiconductor 413 and also can be nmos pass transistor, when select lines is high level, isolate the metal-oxide-semiconductor conducting, when select lines is low level, isolates metal-oxide-semiconductor and turn-off.The height of level can transfer to the gate electrode of switching tube through isolation metal-oxide-semiconductor 413 on the memory node 413, thus the conducting of CS pipe 409 and shutoff.

Continue as shown in Figure 4; Provided to the property omitted the peripheral control circuit that is used for ride gain unit eDRAM 400; The write word line 405 of this gain cell eDRAM 400, write bit line 407, readout word line 406, sense bit line 408 are direct-connected with its Peripheral storage control circuit module 410, and Peripheral storage control circuit module 410 also outputs control signals to select lines 414.In concrete practical application, Peripheral storage control circuit module 410 comprises line decoder, column decoder, line decoder driving, column decoder driving, reading circuit module, write circuit module, address latch, logical sequence control module or the like.Write word line 405, write bit line 407, readout word line 406 and sense bit line 408 through 410 pairs of these gain cell eDRAMs 400 of storage control circuit module applies signal can carry out read operation, write operation, data to gain cell eDRAM 400 and keep operation and refresh operation or the like; In this embodiment; Refresh operation comprises two operating process of read and write, is specially the operating process of write-after-read.EDRAM operating process shown in Figure 3 was basic identical during its specific operation process and background technology were introduced.

Need to prove especially; Read current between sense bit line 408 and the readout word line 406 is through reading 402 of metal-oxide-semiconductor; And through equivalent parasitic capacitances 404, equivalent parasitic capacitances 404 charge stored can remain unchanged basically, the mainly subthreshold value electric leakage through writing MOS gate tube 401 of its charge stored, read the grid leak electricity of MOS transistor 402 and the grid leak electricity of switching tube discharges electric charge; Therefore, its gain cell eDRAM do not have destructiveness read or destructiveness read less.

For the technique effect to gain cell eDRAM embodiment illustrated in fig. 4 is made specific explanations, the refresh operation process of this embodiment gain cell eDRAM is elaborated in conjunction with Fig. 5.Shown in Figure 5 is the potential change synoptic diagram of the gain cell eDRAM of refresh operation process.As shown in Figure 5,506 is the potential waveform of RWL, and 508 is the potential waveform of RBL; 507 is the potential waveform of WBL, and 505 is the potential waveform of WWL, and 514 is the potential waveform of select lines; 504 is the potential waveform of memory node, and 509 is the potential waveform of the grid of switching tube; T0 is the refresh operation process to T4 constantly constantly, and concrete refresh operation process is following:

T0-T1: read operation step.In this stage, RWL is effective, and according to the electromotive force of memory node, RBL is last can to show different potential, through relatively amplifying through sense amplifier with reference voltage Ref, obtains the signal of the full amplitude of oscillation.508a corresponds to the current potential situation of reading " 0 " among the figure, and 508b corresponds to the current potential situation of reading " 1 "; In the refresh operation process, can the anti-phase current potential of RBL be added on the WBL.Can find out that from 508a and 508b in the initial T0 stage, when reading " 0 ", the RBL current potential is not to rise to noble potential suddenly, when reading " 1 ", the RBL current potential is increased by a small margin earlier and is fallen after rise.Active area and stray capacitance coupling influence grid between of the variation meeting of readout word line and read bitline voltage through reading MOS transistor is to the electromotive force of memory node in the read operation process, and therefore, at the T0-T1 node, the current potential of memory node produces fluctuation.If this potential fluctuation exceeds the threshold voltage of switching tube, the logic state of switching tube is changed.

T1-T2: memory node is carried out refresh operation.In this stage, WWL is effective, and WBL writes the value that T0-T1 reads constantly through writing MOS transistor to memory node, and after WWL was effective, memory node recovered 0 current potential; 507a corresponds to the current potential of writing " 0 ", and 507b corresponds to the current potential of one writing.

T2-T3: the node to the switch tube grid carries out refresh operation.After the electromotive force of memory node was stable, select lines began effectively at T2 constantly, and memory node refreshes through the node of 413 pairs of switch tube grids of isolated tube, and at this moment, WBL can continue memory node write and prevents that its current potential from changing.

T3-T4: after refreshing end, select lines, WWL, RWL lost efficacy successively.

Can find out from 504 and 509 contrasts; In read operation process (T0-T1 stage); The current potential of memory node can change because of the active area of reading MOS transistor and the stray capacitance coupling between the grid, and the node of switching tube grid is because the effect electromotive force of isolation metal-oxide-semiconductor is constant basically.Therefore, in the read procedure of whole refresh operation, it is stable that the state of switching tube keeps.

Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific embodiment described in the instructions.

Claims

1. gain eDRAM who is used for PLD, comprise read MOS transistor, write MOS transistor, write word line, readout word line, write bit line, sense bit line and equivalent parasitic capacitances; The grid of writing MOS transistor is connected in write word line; Drain terminal/source end of writing MOS transistor is connected in write bit line; Source end/drain terminal of writing MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances; The grid of reading MOS transistor is connected in the stored charge end of said equivalent parasitic capacitances, and drain terminal/source end of reading MOS transistor is connected in sense bit line, and source end/drain terminal of reading MOS transistor is connected in readout word line; It is characterized in that, also comprise the isolation metal-oxide-semiconductor between the grid that places said equivalent parasitic capacitances and switching tube, the stored charge end of said equivalent parasitic capacitances is controlled the state of the switching tube of said PLD through isolating the metal-oxide-semiconductor transmission level;

Said equivalent parasitic capacitances be write the active area stray capacitance of MOS transistor, read MOS transistor gate capacitance, isolate a kind of in the active area electric capacity of metal-oxide-semiconductor, perhaps for active area stray capacitance, the gate capacitance of reading MOS transistor of writing MOS transistor, isolate the combination of the active area electric capacity of metal-oxide-semiconductor.

2. gain eDRAM according to claim 1 is characterized in that, said isolation metal-oxide-semiconductor is nmos pass transistor or PMOS transistor.

3. gain eDRAM according to claim 1 is characterized in that, saidly writes MOS transistor and reads MOS transistor and be the PMOS transistor.

4. gain eDRAM according to claim 1 is characterized in that, saidly writes MOS transistor and reads MOS transistor and be nmos pass transistor.

5. gain eDRAM according to claim 1 is characterized in that said PLD is a field programmable gate array.

6. gain eDRAM according to claim 1 is characterized in that the grid of said isolation metal-oxide-semiconductor is controlled by select lines.

7. gain eDRAM according to claim 6 is characterized in that said write word line, write bit line, readout word line, sense bit line and select lines receive the control of Peripheral storage control circuit module.