CN103123805A - 2T dynamic memory unit and array structure based on resistance variation gate dielectric and method for operating same - Google Patents
2T dynamic memory unit and array structure based on resistance variation gate dielectric and method for operating same Download PDFInfo
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Abstract
The invention belongs to the technical field of memories and relates to a 2T dynamic memory unit and array structure based on a resistance-change gate dielectric and a method for operating the same. The 2T dynamic memory unit and array structure comprises a write-in tube, a read tube, a memory part, a write word line, a write bit line, a read word line and a read bit line, wherein the source terminal of the write-in tube is connected with the gate electrode of the read tube; the write-in tube has a programming function; the gate dielectric of the read tube is the memory part; the gate dielectric has an insulation state, a high-resistance state and a low-resistance state, and the conversion between high resistance and low resistance is reversible; a certain voltage is applied to the gate electrode of the read tube and the read word line in a reading process; and '0'and '1' can be judged according to the voltage change or the current value of the read bit line. The 2T dynamic memory unit and array structure is simple and convenient in process, low in cost, superior in effect, low in power consumption and high in performance, and is compatible with the front end of a 32-nm High k CMOS logic process.
Description
Technical field
The invention belongs to the memory technology field, relate to a kind of 2T device and array structure for embedded dynamic storage, be specifically related to a kind of 2T dynamic storage cell based on the resistive gate medium and array structure and method of operating thereof.
Background technology
The storage unit of traditional dynamic RAM typically comprises two elements: holding capacitor and access transistor, the structure of formation 1T1C.Traditional dynamic RAM array structure as shown in Figure 1, wherein 100 to 108 is access transistors, and 109 to 111 is bit lines, and 112 to 114 is word lines, and 115 to 117 is the stray capacitances on bit line, 118 to 126 is holding capacitors.Usually the course of work of traditional dynamic RAM comprises, the storage unit that the below consists of take operation access transistor 100 and holding capacitor 118 is as example: in the write operation stage, data value is placed on bit line 109, and 112, word line is raised, difference according to data value, holding capacitor 118 or charging, perhaps discharge, particularly, data writing is 1 o'clock, holding capacitor 118 chargings, data writing is 0 o'clock, holding capacitor 118 discharges.In the read operation stage, bit line 109 when making word line 112 effectively, has been freeed redistributing of electric charge at first by precharge between bit line capacitance 115 and holding capacitor 118, at this moment the voltage on bit line changes, and this change direction has determined to be stored the value of data.1T1C structure dynamic RAM is destructive, and the amount of charge that leaves in other words in the unit is modified during read operation, therefore completes a read operation and must return to its original value afterwards again.So completing read operation and then is exactly refresh operation afterwards.Carry out just carrying out next step read-write operation after refresh operation.This kind 1T1C structure dynamic RAM relies on holding capacitor storage data, so memory capacitance must be enough greatly to guarantee the reliability of storage, but the existence of large electric capacity is area occupied not only, and under the development trend that characteristic dimension is more and more less in semiconductor technology, make large electric capacity very difficult, the obstacle that has caused physics or technique to realize.
Summary of the invention
In order to achieve the above object, the present invention proposes a kind of 2T device and array structure for embedded dynamic storage, relates to more specifically a kind of 2T dynamic storage cell based on the resistive gate medium and array structure and method of operating thereof.
2T dynamic storage cell and array structure based on the resistive gate medium of the present invention comprise writing pipe 201, read pipe 202, memory unit 203, write word line (WWL) 204, write bit line (WBL) 205, readout word line (RWL) 206, sense bit line (RBL) 207; The source that writes pipe 201 connects the grid that reads pipe 202,
In the present invention, write the effect that pipe 201 has programming;
In the present invention, the gate dielectric 203 that reads pipe 202 is memory unit;
Described 203 uses have resistive characteristic material, as HfOx, insulation, high resistant, three kinds of different conditions of low-resistance are arranged, and wherein between high resistant, low-resistance, transformation is reversible, and respectively by SET and RESET voltage transition, and the process from the insulation attitude to high/low resistance is called FORMING;
In the present invention, during programming, write word line 204 is opened, and the voltage that write bit line 205 ends add reaches writes pipe 201 sources (read manage 202 grid), thereby changes the voltage at memory unit 203 two ends, changes 203 resistance value.
In the present invention, in programming process, the voltage that can regulate write word line 204 carries out current limliting.
Read tubular construction in the present invention as shown in Figure 3, in reading process, read in tube grid 301 and connect the source of writing pipe, 302,303 be respectively readout word line (RWL) and sense bit line (RBL), gate dielectric 304 is to have resistive characteristic material, and as HfOx, 305 is substrate, 306 is grid leakage current, and 307,308 are respectively drain terminal electric current and source electric current.When reading, apply certain voltage by writing pipe on 301, and apply suitable voltage (positive potential pulse) on 302, read the change in voltage or the current value that detect on 303; State " 1 " is different with the resistance of state " 0 " gate medium, and the voltage that therefore drops on gate medium is different, and the electromotive force on P-type semiconductor is just variant, causes drain terminal electric current 308 differences, and the change in voltage of 303 ends is also different; Particularly, when gate medium was high resistant, the voltage major part between 301 and 305 was fallen on gate medium, and the electromotive force on p type island region is lower, and drain terminal electric current 308 is also less, and the amplitude that 303 terminal voltages rise is less, as shown in Figure 3A; When gate medium was low-resistance, only some fell on gate medium the voltage between 301 and 305, and the electromotive force on p type island region is higher, and 308 is relatively large, and the amplitude that 303 terminal voltages rise is larger, as shown in Fig. 3 B.
In the present invention, Fig. 4 has shown the domain of 2T eDRAM storage element, wherein 405 representatives write the drain terminal of pipe 401, connect write bit line (WBL), 404 represent write word line (WWL), and 406 for reading the drain terminal of pipe 402, connect readout word line (RWL), 407 is 402 source, connects read bit (RBL), and 403 is the resistive gate medium.
In the present invention, in 2T eDRAM array structure, 501 is a unit, comprise writing and manage+read pipe, the position of programming can be regarded MIS RRAM as, and 502 is write word line (WWL), 503 is readout word line (RWL), 504 is write bit line (WBL), and 505 is sense bit line (RBL), and reading tube grid medium 506 has high and low resistance different conditions (as shown in Figure 5).
Advantage applies of the present invention exists:
(1) overcome the difficulty of traditional 1T1C DRAM unit scaling down, and with the compatible relatively poor problem of standard CMOS process;
(2) the present invention is 90nm and with a solution of lower node dynamic storage (particularly in-line memory), does not especially need to make specially large electric capacity, can with the CMOS HfOx high k metal gate technical compatibility of standard logic; In addition, data hold time can reduce refreshing frequency greater than general charge storage type eDRAM, is conducive to low-power consumption and uses.
The invention provides a kind of simple process, the embedded dynamic memory device structure of 2T that with low cost, effect is superior; Described storage component part is a kind of typical resistance-type memory, the reading current of 1 and 0 two condition can differ 20～500 times, good and the charge type dynamic storage (comprising 1T1C DRAM) of data retention characteristics, and compatible with 32nm High kCMOS logic process front end; Storage component part of the present invention is a kind of low-power consumption, high performance resistance-change memory device, and the embedded non-volatile storage that is specially adapted to 45nm and following technology node is used.
Description of drawings
Fig. 1 has shown traditional dynamic RAM array structure.
Fig. 2 is storage unit schematic diagram of the present invention.
Fig. 3 is the ultimate principle figure that described device reads, only to read tubular construction as example;
Wherein, A has shown high-impedance state, and B has shown low resistive state.
Fig. 4 is the domain of 2T eDRAM storage element of the present invention.
Fig. 5 is 2T eDRAM array structure schematic diagram of the present invention.
Fig. 6 is domain and the sectional view of unit.
Fig. 7 is array of figure of the present invention, and wherein, the framework of peripheral circuit and conventional memory is roughly the same, is comprised of sense amplifier, code translator etc.
Embodiment
According to 2T dynamic storage cell and the array structure of embodiments of the invention based on the resistive gate medium, comprise writing pipe 201, read pipe 202, memory unit 203, write word line (WWL) 204, write bit line (WBL) 205, readout word line (RWL) 206, sense bit line (RBL) 207; The source that writes pipe 201 connects the grid that reads pipe 202; Writing pipe 201 has the effect of programming; The gate dielectric 203 that reads pipe 202 is memory unit; Described 203 uses have resistive characteristic material, as HfOx, insulation, high resistant, three kinds of different conditions of low-resistance are arranged, and wherein between high resistant, low-resistance, transformation is reversible, and respectively by SET and RESET voltage transition, and the process from the insulation attitude to high/low resistance is called FORMING; During programming, write word line 204 is opened, and the voltage that write bit line 205 ends add reaches writes pipe 201 sources (read manage 202 grid), thereby changes the voltage at memory unit 203 two ends, changes 203 resistance value.
In programming process, the voltage that can regulate write word line 204 carries out current limliting.
Describedly read tubular construction as shown in Figure 3, in reading process, read tube grid 301 and connect the source that writes pipe, 302,303 be respectively readout word line (RWL) and sense bit line (RBL), gate dielectric 304 is to have resistive characteristic material, and as HfOx, 305 is substrate, 306 is grid leakage current, and 307,308 are respectively drain terminal electric current and source electric current; When reading, apply certain voltage by writing pipe on 301, and apply suitable voltage (positive potential pulse) on 302, read the change in voltage or the current value that detect on 303; State " 1 " is different with the resistance of state " 0 " gate medium, and the voltage that therefore drops on gate medium is different, and the electromotive force on P-type semiconductor is just variant, causes drain terminal electric current 308 differences, and the change in voltage of 303 ends is also different; Particularly, when gate medium was high resistant, the voltage major part between 301 and 305 was fallen on gate medium, and the electromotive force on p type island region is lower, and drain terminal electric current 308 is also less, and the amplitude that 303 terminal voltages rise is less, as shown in Figure 3A; When gate medium was low-resistance, only some fell on gate medium the voltage between 301 and 305, and the electromotive force on p type island region is higher, and 308 is relatively large, and the amplitude that 303 terminal voltages rise is larger, as shown in Fig. 3 B.
The domain of 2T eDRAM storage element as shown in Figure 4, wherein 405 representatives write the drain terminal of pipe 401, connect write bit line (WBL), 404 represent write word line (WWL), 406 for reading the drain terminal of pipe 402, connects readout word line (RWL), and 407 is 402 source, connect read bit (RBL), 403 is the resistive gate medium.
In 2T eDRAM array structure, 501 is a unit, comprise writing and manage+read pipe, the programming position can be regarded MIS RRAM as, 502 is write word line (WWL), and 503 is readout word line (RWL), and 504 is write bit line (WBL), 505 is sense bit line (RBL), and reading tube grid medium 506 has high and low resistance different conditions (as shown in Figure 5).
The below will introduce according to one embodiment of the invention based on the 2T dynamic storage cell of resistive gate medium and the method for operating of array structure.The operating voltage table is as shown in table 1:
Table 12T cell operating voltage table
Wherein,
Vrg: read the tube grid both end voltage, should be as far as possible little, to improve device reliability;
VR: resistive gate medium both end voltage;
Vset: the set voltage of resistive material, the resistive material changes low resistance into by high value;
Vreset: the reset voltage of resistive material, the resistive material changes high value into by low resistance;
Vpass1/Vpass1: write for 1/0 when operation and write tube grid (WWL) institute making alive;
VWB_r: WBL institute making alive during read operation
VWW_r: WWL institute making alive during read operation
VRW_r: RWL institute making alive during read operation
SRSC: the unit that selected row, column is intersected, selected row, selected column;
URSC: not selected row, the unit of choosing row to intersect, unselected rows, selected column;
SRUC: the unit that selected line, not selected row are intersected, i.e. selected cell, selected row, unselected columns;
URUC: the unit that not selected row, not selected row intersect, unselected rows, unselected columns;
Might need just may carry out the transformation of high resistance and low resistance after Forming for the insulation attitude under the HfO2 initial conditions, therefore, increase the Forming step, mode of operation is with writing 1 or write 0.
Fig. 6 is according to 2T dynamic storage cell and the array structure of one embodiment of the invention based on the resistive gate medium, take the 32nm process node as example.The 32nm logical device adopts High k Metal Gate technology, and most widely used gate medium is HfOx, has been proved to be to have the resistive characteristic; HfOx composition of the present invention is different, for the storage characteristics of optimised devices, the HfOx of described programming parts on thickness can with the difference to some extent of standard logic, increase a special mask plate 609;
Wherein,
605 for writing the drain terminal of pipe 601, connects write bit line (WBL), and 604 represent write word line (WWL);
606 for reading the drain terminal of pipe 602, connects readout word line (RWL), and 607 is 602 source, connects sense bit line (RBL);
603 is the resistive gate medium, 601 sources with are connected grid and connected by metal 608.
Need to prove, Fig. 7 shows according to 2T dynamic storage cell and the array structure of one embodiment of the invention based on the resistive gate medium, but the framework of peripheral circuit and conventional memory is roughly the same, is comprised of sense amplifier, column decoder etc.
In one embodiment, possible operating voltage table unipolar type resistive is special: (Vset=3.2V, Vreset=1.8V, VB1=2.0V, VB0=0.8V, Vpass1=Vpass0=0.8V Vpass＞Vt, VWB_r=0.8V, VWW_r=0.8V, VRW_r=1.0V), as shown in table 2:
Table 2
Possible operating voltage table bipolar:(Vset=3.2V, Vreset=-4.5V, VB1=2.0V, VB0=-2.0V, Vpass1=1V Vpass0=0.8V, VWB_r=0.8V, VWW_r=0.8V, VRW_r=1.0V), as shown in table 3:
Table 3
Although illustrate and described the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that at it and can make a lot of variations and modification without departing from the invention aspect wider.The present invention includes the SOI substrate, and all advanced structures such as FinFET, ring grid, many techniques and domain implementation are also arranged; Kinds of processes and domain implementation may be arranged; May have multiple for the integrated resistive material of grid; The present invention includes the improvement to method of operating based on the resistive material behavior, and for to improve storage characteristics to the optimization of operating voltage table.
Claims (8)
1. 2T dynamic storage cell and array structure based on a resistive gate medium, it is characterized in that, comprise write pipe (201), read pipe (202), memory unit (203), write word line (204), write bit line (205), readout word line (206) and sense bit line (207); The grid of pipe (202) is read in the described source connection that writes pipe (201).
2. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 1, it is characterized in that, describedly write the effect that pipe (201) has programming.
3. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 1, it is characterized in that, the described gate dielectric (203) that reads pipe (202) is memory unit; Described gate dielectric (203) uses resistive characteristic material HfOx.
4. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 1, it is characterized in that, described gate dielectric (203) has insulation, high resistant, three kinds of different conditions of low-resistance, wherein changes reversible between high resistant, low-resistance.
5. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 1, it is characterized in that, described write word line (204) is opened when programming, the voltage that write bit line (205) end adds reaches and writes pipe (201) source, change the voltage at memory unit (203) two ends, change the resistance value of (203); Described write word line (204) is regulated its voltage and is carried out current limliting in programming process.
6. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 1, it is characterized in that, when reading read in tube grid, readout word line applies certain voltage, can be according to the change in voltage of sense bit line or current value size judgement " 0 " and " 1 ".
7. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 6, it is characterized in that, the reading current of 1 and 0 two condition differs 20～500 times.
8. by 2T dynamic storage cell and array structure based on the resistive gate medium claimed in claim 1, it is characterized in that, increase mask plate (609) at the HfOx of described programming parts on thickness.
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| CN201110372169.6A CN103123805B (en) | 2011-11-21 | 2T dynamic storage cell based on variable-resistance gate medium and array structure and operational approach thereof |
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| CN201110372169.6A CN103123805B (en) | 2011-11-21 | 2T dynamic storage cell based on variable-resistance gate medium and array structure and operational approach thereof |
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| CN103123805A true CN103123805A (en) | 2013-05-29 |
| CN103123805B CN103123805B (en) | 2016-12-14 |
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| CN109461811A (en) * | 2018-09-12 | 2019-03-12 | 华中科技大学 | A kind of mixing of CRS resistance-variable storing device can reallocating method |
| CN115171751A (en) * | 2022-07-07 | 2022-10-11 | 北京超弦存储器研究院 | Memory, access method thereof and electronic equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109461811A (en) * | 2018-09-12 | 2019-03-12 | 华中科技大学 | A kind of mixing of CRS resistance-variable storing device can reallocating method |
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| CN115171751A (en) * | 2022-07-07 | 2022-10-11 | 北京超弦存储器研究院 | Memory, access method thereof and electronic equipment |
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