CN102789812A - NOR memory cell based on resistance-changeable gate dielectric, its array and its operation method - Google Patents
NOR memory cell based on resistance-changeable gate dielectric, its array and its operation method Download PDFInfo
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- CN102789812A CN102789812A CN2011101274039A CN201110127403A CN102789812A CN 102789812 A CN102789812 A CN 102789812A CN 2011101274039 A CN2011101274039 A CN 2011101274039A CN 201110127403 A CN201110127403 A CN 201110127403A CN 102789812 A CN102789812 A CN 102789812A
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Abstract
An NOR memory based on a resistance-changeable gate dielectric comprises: a transistor comprising a source electrode, a drain electrode and a control gate electrode; a memory node which is a gate dielectric of the control gate electrode of the transistor, is positioned between the control gate electrode of the transistor and a silicon substrate and stores the resistance change; a word line connected to the control gate electrode of the transistor; a bit line connected to the drain electrode of the transistor; and a source line connected to the source electrode of the transistor. The gate electrode uses a resistance-changeable characteristic material having three different states of insulation, high resistance and low resistance, there is reversible switching between the high resistance and the low resistance, a constant voltage is applied among the word line, the source line and the bit line during reading, and "0" and "1" can be determined according to different currents. The invention also provides an array and an operation method of the NOR memory cell based on the resistance-changeable gate dielectric.
Description
Technical field
The present invention relates to the memory technology field, relate in particular to a kind of device and NOR type array structure that is used for non-volatile storage, with and method of operating.
Background technology
Storer occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of non-volatility memorizer in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But because the requirement of stored charge, the floating boom of FLASH can not develop unrestricted attenuate with technology generation, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior non-volatility memorizer of future generation of performance.Recently electric resistance transition memory spare (resistive switching memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has the SrZrO3, ferroelectric material PbZrTiO3, ferromagnetic material Pr1-xCaxMnO3, binary metal oxide material, organic material of phase-change material, doping etc.Resistor-type memory is through action of electric signals, and (High Resistance State is HRS) with low resistance (Low Resistance State, but LRS) inverse conversion between the state, thereby realization memory function at high resistance state to make storage medium.
Referring to accompanying drawing 1, be traditional NOR type flash memory Flash.Wherein 101 is control gate (control gate); 102 is floating boom (floating gate); Be used for stored charge; 103 is dielectric layer between grid (Inter Poly Dielectric ONO), and 104 is tunnel oxide (Tunnel Oxide), and 105,106 are respectively drain electrode (drain) and source electrode (source).On 101 and 105, apply voltage during programming, the electric charge tunnelling is stored into floating boom, and changes the threshold voltage of device; Write at 0 o'clock and then electronics is evicted out of floating boom.NOR type flash memory Flash array is as shown in Figure 2, and wherein 200 is a storage unit, and 201 to 206 is control gate, and 207 to 212 is floating boom, and 213 to 215 is bit line (Bitline), and 216 to 217 is word line (Wordline).
NOR type flash memory Flash has following deficiency:
1. operation with high pressure needs just boosting, passing/the negative high voltage circuit of special;
2. needing increases the multiple tracks step on the basis of standard logic process, make dielectric and high-voltage tube between floating boom, grid;
3. NOR type flash memory Flash is a charge storage type device, and along with dwindling of characteristic dimension in the semiconductor technology, the floating boom of stored charge is unrestricted attenuate but, has the limit physically.
Summary of the invention
In view of this; The present invention provides a kind of 45nm to reach a solution with lower node non-volatility memorizer (particularly in-line memory); Especially can with the CMOS HfOx high k metal gate technical compatibility of standard logic, propose a kind of NOR type storage unit, array that becomes gate medium based on resistance with and mode of operation.
In order to achieve the above object, the present invention provides a kind of NOR type storer based on resistance change gate medium to comprise: transistor comprises source electrode, drain electrode and control grid; Memory node, the gate medium of promptly said transistor controls grid, between transistor controls grid and silicon substrate, memory resistor changes; Word line is connected to said transistorized control grid; Bit line is connected to said transistor drain; The source line is connected to said transistorized source electrode.
Grid uses has resistance change characteristic material; Have insulation, high resistant, three kinds of different conditions of low-resistance; Wherein transformation is reversible between high resistant, the low-resistance, between word line, source line, bit line, applies certain voltage when reading, and can judge " 0 " and " 1 " according to the electric currents of different sizes.
On word line and bit line, apply suitable voltage, state " 1 " is different with the resistance of state " 0 " gate medium, thereby the voltage that drops on the gate medium is different.When gate medium was high resistant, the voltage major part between word line and the substrate was fallen on gate medium, and the electromotive force on the p type island region is lower.When gate medium was low-resistance, only some fell on gate medium the voltage between word line and the substrate, and the electromotive force on the p type island region is higher.Resistance becomes the characteristic material and is HfOx
In order to achieve the above object, the present invention also provides a kind of NOR type storage unit based on resistance change gate medium to comprise: transistor comprises source electrode, drain electrode and control grid; Memory node, the gate medium of promptly said transistor controls grid, between transistor controls grid and silicon substrate, memory resistor changes; Word line is connected to said transistorized control grid; Bit line is connected to said transistor drain; The source line is connected to said transistorized source electrode.Grid uses has resistance change characteristic material; Have insulation, high resistant, three kinds of different conditions of low-resistance; Wherein transformation is reversible between high resistant, the low-resistance, between word line, source line, bit line, applies certain voltage when reading, and can judge " 0 " and " 1 " according to the electric currents of different sizes.
In order to achieve the above object, the present invention also provides a kind of NOR type memory cell operation method based on resistance change gate medium, comprising:
Write 1: the bit line to storage unit applies the 1st voltage; Word line applies the 2nd voltage, produces conductive channel in the voltage difference initiation gate medium of the 1st voltage and the 2nd voltage, and the resistance of gate medium is reduced; The voltage that lands on the grid reduces, and p type island region semiconductor surface electromotive force raises.
Write 0: the bit line to storage unit applies the 3rd voltage; Word line applies the 4th voltage, and the voltage difference of the 3rd voltage and the 4th voltage blocks the original conductive channel of gate medium, and the resistance of gate medium is raise; The voltage that lands on the grid increases, and p type island region semiconductor surface electromotive force reduces.
Read: the bit line to storage unit applies the 5th voltage, and word line applies the 6th voltage, and the 5th voltage and the 6th voltage are less; Be not enough to change the original resistance value of grid, through the bit line port reads bitline electric current of storage unit, 1 state p type island region semiconductor surface electromotive force is higher; Electric current on the bit line is bigger, and the electromotive force of 0 state p type island region semiconductor surface is lower, and the electric current on the bit line is less; Therefore electric current that 1 and 0 state is corresponding big respectively and little electric current, thus tell different store statuss.
It is easy to the invention provides a kind of technology; NOR type nonvolatile memory device architecture with low cost, that effect is superior, the reading electric current and possibly differ 20 ~ 1000 times of 1 and 0 two condition; Data retention characteristics is good, and compatible with 32nm High k CMOS logic process front end.The invention provides a kind of low-power consumption, high performance resistance-change memory device, the embedded non-volatile storage that is specially adapted to 45nm and following technology node is used.
Description of drawings
Accompanying drawing 1 is traditional NOR type flash memory Flash;
Accompanying drawing 2 is traditional NOR type flash memory Flash storage array;
Accompanying drawing 3 is the NOR type storage unit that becomes gate medium according to one embodiment of the invention based on resistance;
Accompanying drawing 4 is the schematic diagram that becomes the NOR type storage unit of gate medium according to one embodiment of the invention based on resistance;
Accompanying drawing 5 is the NOR type memory cell array that becomes gate medium according to one embodiment of the invention based on resistance;
Accompanying drawing 6 is the NOR type storage unit that becomes gate medium according to one embodiment of the invention with 32nm technology based on resistance.
Embodiment
Comprise based on the NOR type storer that resistance becomes gate medium according to embodiments of the invention: transistor comprises source electrode, drain electrode and control grid; Memory node, the gate medium of promptly said transistor controls grid, between transistor controls grid and silicon substrate, memory resistor changes; Word line is connected to said transistorized control grid; Bit line is connected to said transistor drain; The source line is connected to said transistorized source electrode.With reference to accompanying drawing 3, for become the NOR type storage unit of gate medium based on resistance according to one embodiment of the invention.Wherein, 301 is word line (Wordline), and 302,303 are respectively source line (Sourceline) and bit line (Bitline), and grid 304 uses has resistance change characteristic material, like HfOx.Wherein grid 304 has insulation, high resistant, three kinds of different conditions of low-resistance, and wherein transformation is reversible between high resistant, the low-resistance, and respectively by SET and RESET voltage transition, and the process from the insulation attitude to height/low-resistance is called FORMING.305 is substrate.Between word line 301, source line 302 and bit line 303, apply certain voltage when reading, can judge " 0 " and " 1 " according to the electric current of different sizes.
Accompanying drawing 4 is according to the schematic diagram of one embodiment of the invention based on the NOR type storage unit of resistance change gate medium, can carry out the transformation between the high low-resistance of grid material through voltage between change grid and the drain electrode (or substrate).Wherein 401 is word line, and 402,403 are respectively source line and bit line, and gate dielectric 404 is to have resistance to become the characteristic material, and like HfOx, 405 is substrate, and 406 is grid leakage current, and 407,408 are respectively drain terminal electric current and source end electric current.When reading, on 401 and 403, apply suitable voltage, state " 1 " is different with the resistance of state " 0 " gate medium, and the voltage that therefore drops on the gate medium is different, and the electromotive force on the P-type semiconductor is just variant, causes drain terminal electric current 408 differences.Specifically, when gate medium was high resistant, the voltage major part between 401 and 405 was fallen on gate medium, and the electromotive force on the p type island region is lower, and drain terminal electric current 408 is also less, shown in Fig. 4 (a); When gate medium was low-resistance, only some fell on gate medium the voltage between 401 and 405, and the electromotive force on the p type island region is higher, and 408 is relatively large, shown in Fig. 4 (b).
Accompanying drawing 5 is that each cell size is 1T according to the NOR type memory cell array of one embodiment of the invention based on resistance change gate medium.Wherein: 505 is a unit, and 501 is word line, and 502 is source line (Sourceline), and 503 is bit line (Bitline), and 504 are resistance change grid.The NOR type storage unit 505 that becomes gate medium based on resistance comprises: transistor comprises source electrode, drain electrode and control grid; Memory node 504, the gate medium of promptly said transistor controls grid, between transistor controls grid and silicon substrate, memory resistor changes; Word line 501 is connected to said transistorized control grid; Bit line 503 is connected to said transistor drain; Source line 502 is connected to said transistorized source electrode.
To introduce the NOR type memory cell operation method that becomes gate medium according to one embodiment of the invention based on resistance below.The operating voltage table is as shown in table 1:
Table 1:
| Mode of operation | V BL | V WL | V SL |
| Write " 1 ", high resistant is to low-resistance | Vpro | Vpro+ |
0 |
| Write " 0 ", low-resistance changes high resistant into | Vera | Vera+ |
0 |
| Read | V BR | V WR | 0 |
Wherein:
Vpro: bit-line voltage during one writing;
Vera: bit-line voltage when writing " 0 ";
Vset: resistance becomes the set voltage of material, and resistance becomes material and changes low resistance into by high value;
Vreset: resistance becomes the reset voltage of material, and resistance becomes material and changes high value into by low resistance;
V
BR: bit-line voltage when reading;
V
WR: word line voltage when reading.Concrete numerical value is confirmed by process condition and array disturbed condition.
Specifically describe operating process below:
One writing: the bit line to storage unit applies voltage Vpro; Word line applies voltage Vpro+Vset, produces conductive channel in bit line and the word line voltage difference Vset initiation gate medium, and the resistance of gate medium is reduced; The voltage that lands on the grid reduces, and p type island region semiconductor surface electromotive force raises.
Write " 0 ": the bit line to storage unit applies voltage Vera; Word line applies voltage Vera+Vreset; The voltage difference Vreset of the 3rd voltage and the 4th voltage blocks the original conductive channel of gate medium; The resistance of gate medium is raise, and the voltage that lands on the grid increases, and p type island region semiconductor surface electromotive force reduces.
Read operation: the bit line to storage unit applies voltage VBR, and word line applies voltage VWR, and VBR and VWR are less; Be not enough to change the original resistance value of grid, through the bit line port reads bitline electric current of storage unit, 1 state p type island region semiconductor surface electromotive force is higher; Electric current on the bit line is bigger, and the electromotive force of 0 state p type island region semiconductor surface is lower, and the electric current on the bit line is less; Therefore electric current that 1 and 0 state is corresponding big respectively and little electric current, thus tell different store statuss.
In one embodiment, possible operating voltage can be for shown in the table 2:
Table 2:
Vset=1.0V,?Vreset=-0.6V,?V
BR=0.2V,?V
WR=0.6V
| Mode of operation | V BL | V WL | V SL |
| Write " 1 ", high resistant is to low-resistance | -0.2 | 0.8 | 0 |
| Write " 0 ", low-resistance changes high resistant into | 0.2 | -0.4 | 0 |
| Read | 0.2 | 0.6 | 0 |
In addition; Under some process conditions; Might be insulation attitude (high resistance) under the HfO2 initial conditions, need carry out Forming and operate in generation initial conduction passage in the dielectric layer that Forming voltage generally is higher than 1 operation of writing on the common meaning; Just possibly carry out the transformation between normal state " 1 " and the state " 0 " then, afterwards write 0 with write 1 and only the conductive channel in the medium blocked somewhere again and connect.The Forming step is that the bit line to storage unit applies voltage VBL_For, and word line applies voltage VWL_For, and bit line and word line voltage difference make and form conductive channel in the gate medium, thereby reduces gate medium resistance and drop to the voltage on the gate medium, and is as shown in table 3:
Table 3:
| Mode of operation | V BL | V WL | V SL |
| Forming | V BL_For | |
0 |
Accompanying drawing 6 is the NOR type storage unit that becomes gate medium according to one embodiment of the invention with 32nm technology based on resistance.The 32nm logical device adopts High k Metal Gate technology, and most widely used gate medium is HfOx, and it has been proved to be has resistance change characteristic.Except the said HfOx composition in front is not all, for the storage characteristics of optimised devices, the HfOx of the programming parts here on thickness maybe with the difference to some extent of standard logic, so increase a special mask plate 605 on the domain.Wherein: 601 is word line (Wordline), and 602 is source line (Sourceline), and 603 is bit line (Bitline), and 604 are resistance change gate dielectric.
Need to prove that accompanying drawing 5 shows according to the NOR type memory cell array of one embodiment of the invention based on resistance change gate medium, but the framework of peripheral circuit and conventional memory is roughly the same, is made up of sense amplifier, code translator etc.
Although illustrate and described the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that at it and can make a lot of variations and modification without departing from the invention aspect wideer.The present invention includes the SOI substrate, and all advanced structures such as FinFET, ring grid, also can use P type MOSFET to replace N type MOSEFT; Have many technologies and domain implementation; Has the multiple integrated resistance change material of grid that is used for; The present invention includes the improvement that becomes material behavior based on resistance to method of operating, and for improving the optimization of storage characteristics to the operating voltage table.
Claims (14)
1. one kind becomes the NOR type storer of gate medium based on resistance, comprising:
Transistor comprises source electrode, drain electrode and control grid;
Memory node, the gate medium of promptly said transistor controls grid, between transistor controls grid and silicon substrate, memory resistor changes;
Word line is connected to said transistorized control grid;
Bit line is connected to said transistor drain;
The source line is connected to said transistorized source electrode.
2. the NOR type storer based on resistance change gate medium according to claim 1, wherein: grid uses has resistance change characteristic material, has insulation, high resistant, three kinds of different conditions of low-resistance, wherein changes reversible between high resistant, the low-resistance.
3. the NOR type storer based on resistance change gate medium according to claim 1, wherein: on word line and bit line, apply suitable voltage, state " 1 " is different with the resistance of state " 0 " gate medium, thus the voltage that drops on the gate medium is different.
4. the NOR type storer based on resistance change gate medium according to claim 2, wherein: when gate medium was high resistant, the voltage major part between word line and the substrate was fallen on gate medium, and the electromotive force on the p type island region is lower.
5. the NOR type storer based on resistance change gate medium according to claim 2, wherein: when gate medium was low-resistance, only some fell on gate medium the voltage between word line and the substrate, and the electromotive force on the p type island region is higher.
6. the NOR type storer based on resistance change gate medium according to claim 1, wherein: said resistance becomes the characteristic material and is HfOx.
7. one kind becomes the NOR type memory cell of gate medium based on resistance, comprising:
Transistor comprises source electrode, drain electrode and control grid;
Memory node, the gate medium of promptly said transistor controls grid, between transistor controls grid and silicon substrate, memory resistor changes;
Word line is connected to said transistorized control grid;
Bit line is connected to said transistor drain;
The source line is connected to said transistorized source electrode.
8. the NOR type memory cell based on resistance change gate medium according to claim 7, wherein: grid uses has resistance change characteristic material, has insulation, high resistant, three kinds of different conditions of low-resistance, wherein changes reversible between high resistant, the low-resistance.
9. the NOR type memory cell based on resistance change gate medium according to claim 7, wherein: on word line and bit line, apply suitable voltage, state " 1 " is different with the resistance of state " 0 " gate medium, thus the voltage that drops on the gate medium is different.
10. the NOR type memory cell based on resistance change gate medium according to claim 8, wherein: when gate medium was high resistant, the voltage major part between word line and the substrate was fallen on gate medium, and the electromotive force on the p type island region is lower.
11. the NOR type memory cell based on resistance change gate medium according to claim 8, wherein: when gate medium was low-resistance, only some fell on gate medium the voltage between word line and the substrate, and the electromotive force on the p type island region is higher.
12. the NOR type memory cell based on resistance change gate medium according to claim 7, wherein: said resistance becomes the characteristic material and is HfOx.
13. the NOR type memory cell operation method based on resistance change gate medium is characterised in that may further comprise the steps:
One writing: the bit line to storage unit applies the 1st voltage; Word line applies the 2nd voltage, produces conductive channel in the voltage difference initiation gate medium of the 1st voltage and the 2nd voltage, and the resistance of gate medium is reduced; The voltage that lands on the grid reduces, and p type island region semiconductor surface electromotive force raises;
Write " 0 ": the bit line to storage unit applies the 3rd voltage; Word line applies the 4th voltage, and the voltage difference of the 3rd voltage and the 4th voltage blocks the original conductive channel of gate medium, and the resistance of gate medium is raise; The voltage that lands on the grid increases, and p type island region semiconductor surface electromotive force reduces.
14. the NOR type memory cell operation method based on resistance change gate medium according to claim 13 is characterised in that may further comprise the steps:
Read operation: the bit line to storage unit applies the 5th voltage, and word line applies the 6th voltage, and the 5th voltage and the 6th voltage are less; Be not enough to change the original resistance value of grid, through the bit line port reads bitline electric current of storage unit, 1 state p type island region semiconductor surface electromotive force is higher; Electric current on the bit line is bigger, and the electromotive force of 0 state p type island region semiconductor surface is lower, and the electric current on the bit line is less; Therefore electric current that 1 and 0 state is corresponding big respectively and little electric current, thus tell different store statuss.
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| CN110837355A (en) * | 2019-10-21 | 2020-02-25 | 华中科技大学 | Logic circuit based on NOR flash array and operation method |
| CN111581675A (en) * | 2020-04-10 | 2020-08-25 | 安徽大学 | Physical unclonable function circuit structure based on resistive random access memory |
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| CN110837355A (en) * | 2019-10-21 | 2020-02-25 | 华中科技大学 | Logic circuit based on NOR flash array and operation method |
| CN111581675A (en) * | 2020-04-10 | 2020-08-25 | 安徽大学 | Physical unclonable function circuit structure based on resistive random access memory |
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Application publication date: 20121121 |