CN102651233B - Composite memory - Google Patents
Composite memory Download PDFInfo
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- CN102651233B CN102651233B CN201110046327.9A CN201110046327A CN102651233B CN 102651233 B CN102651233 B CN 102651233B CN 201110046327 A CN201110046327 A CN 201110046327A CN 102651233 B CN102651233 B CN 102651233B
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Abstract
The invention discloses a kind of composite memory.This composite memory comprises several compound memory unit.This compound memory unit comprises: floating boom subelement; And the resistance random access memory RRAM subelement on the drain electrode being formed at this floating boom subelement; Wherein, when RRAM subelement is as memory module, floating boom subelement is as gating module; And RRAM subelement is when being in low resistance state, floating boom subelement is as memory module.The present invention has fully utilized that the high density of floating boom storage mode, high reliability, crosstalk are little, the low-power consumption of tolerance advantages of higher and RRAM storage mode, high speed, advantages of simple structure and simple.
Description
Technical field
The present invention relates to microelectronic industry memory technology field, particularly relate to a kind of composite memory.
Background technology
Current semiconductor memory market, with volatile dynamic RAM (Dynamic Random Access Memory, be called for short DRAM) and static RAM (Static Random Access Memory, abbreviation SRAM) and nonvolatile " flash memory " storer (Flash) be representative.Along with the development of the various portable digital products such as movable storage device, mobile telecommunication device and digital camera is with universal, the demand of market to non-volatile data storage increases further, in order to improve storage density and data storing reliability, the flash storage based on conventional floating gate structure is faced with severe challenge.For this reason, industry has carried out large quantifier elimination to non-volatile semiconductor memory technology of future generation, and various new memory technology obtains develop rapidly.As follow-on electric charge capture flash memory (Charge Trap Flash, being called for short CTF) resistance random access memory (Resistive Random Access Memory is called for short RRAM) of storer and revolution type is representational two research directions of current most.
Fig. 1 is the structural representation of prior art CTF storer of the present invention.As shown in Figure 1, the gate dielectric layer of typical CTF storer comprises restraining barrier, accumulation layer and tunnel layer three-decker.Fig. 2 is the principle schematic of prior art CTF storer of the present invention.As shown in Figure 2, the storage principle of CTF storer is the same with traditional floating-gate memory principle, utilizes the change of threshold voltage before and after programming to realize " 0 " and " 1 " of stored logic.CTF storer adopts the discrete memory technology of electric charge, effectively alleviates the contradiction between tunnel oxide and data holding ability.Discrete charge storage mainly utilizes the memory node insulated each other to carry out stored charge.Such as SONOS (Si/SiO
2/ Si
3n
4/ SiO
2/ Si) structure utilizes the deep energy level defect of nitride self as charge storage media, and nanocrystalline structure utilizes the nanocrystalline as charge storage media of separation.Therefore the local leak channel in tunnel oxide only can cause the leakage of minority stored charge, greatly can improve the charge maintenance capability of memory device.
Fig. 3 is the structural representation of prior art RRAM storer of the present invention.As shown in Figure 3, RRAM storage unit mainly comprises change resistance layer and upper/lower electrode.Fig. 4 is storage principle first schematic diagram of prior art RRAM storer of the present invention.Fig. 5 is storage principle second schematic diagram of prior art RRAM storer of the present invention.As shown in Figure 4 and Figure 5, in RRAM storage unit, the transition phenomenon utilizing some membraneous material to there will be different resistance states (high and low resistance state) under the effect of electric excitation realizes logical zero and " 1 " of storage.It is low that research finds that RRAM has write voltage, and the write erasing time is short, and non-destructive reads, and structure is simple, the advantages such as required area is little, and due to its high speed writein erasing characteristic, be also considered to the memory device being hopeful most to replace traditional DRAM.
Table 1 prior art CTF storer of the present invention and the RRAM memory performance table of comparisons
| Storer | CTF | RRAM |
| Non-volatile | Have | Have |
| Write power | High | Low |
| Write voltage | High | Low |
| Data holding ability | Better | There is fluctuation |
| Write time | 1μs | 10ns |
| Erasing time | 10ms | 30ns |
| The reading time | 50ns | 20ns |
| Write energy | High | Low |
| Density | High | High |
Table 1 is prior art CTF storer of the present invention and the RRAM memory performance table of comparisons.As shown in Table 1, two kinds of storer mutual relative merits.Realizing in process of the present invention, inventor recognizes that prior art exists following technological deficiency: can not select storage mode flexibly according to user's request, thus obtains a kind of storer having two kinds of storage mode advantages concurrently.
Summary of the invention
(1) technical matters that will solve
For addressing the aforementioned drawbacks, the invention provides a kind of composite memory, with the advantage in conjunction with floating boom storage mode and RRAM storage mode, selecting storage mode flexibly according to user's request.
(2) technical scheme
According to an aspect of the present invention, provide a kind of compound memory unit, this compound memory unit comprises: floating boom subelement; And the resistance random access memory RRAM subelement on the drain electrode being formed at this floating boom subelement; Wherein, when RRAM subelement is as memory module, floating boom subelement is as gating module; And RRAM subelement is when being in low resistance state, floating boom subelement is as memory module.
Preferably, in compound memory unit of the present invention, floating boom subelement is electric charge capture flash memory CTF subelement.
Preferably, in compound memory unit of the present invention, an electrode of RRAM subelement is connected with the drain electrode of CTF subelement; RRAM subelement another electrode corresponding with electrode is as the bit line of compound memory unit; And the grid of CTF subelement is as the wordline of compound memory unit.
Preferably, in compound memory unit of the present invention, RRAM subelement is as memory module, when CTF subelement is as gating module, then: when programmed, source ground, wordline is connected with providing the circuit of positive bias, and bit line is connected with the circuit of the program voltage providing RRAM subelement; Maybe when wiping, bit line is connected with providing the circuit of erasing voltage; Or when reading, wordline is connected with providing the circuit of positive bias, bit line is connected with providing the circuit reading voltage.
Preferably, in compound memory unit of the present invention, RRAM subelement is in low resistance state, when CTF subelement is as memory module, then: when programmed, CTF subelement adopts Fowler-Nordheim (Fowler Nordheim is called for short FN) programming or channel hot electron to inject (Channel Hot Electron injection is called for short CHE) programming; Maybe when wiping, CTF subelement adopts FN erasing; Or when reading, the wordline of compound memory unit is connected with providing the circuit reading voltage, and bit line is connected with providing the circuit of positive bias, the source ground of CTF subelement.
According to another aspect of the present invention, a kind of composite memory is additionally provided.This composite memory comprises storage array, RRAM peripheral control circuits, floating boom peripheral control circuits and gating circuit, wherein: storage array comprises several above-mentioned compound memory unit, along two compound memory unit common-source of bit line direction; Gating circuit, is connected with the word/bit line of each storage unit with RRAM peripheral control circuits, floating boom peripheral control circuits, for realizing the selection to default compound memory unit memory module; RRAM peripheral control circuits, is connected with RRAM subelement with gating circuit, for realizing programming to RRAM subelement in default compound memory unit, erasing or reading; CTF peripheral control circuits, is connected with CTF subelement with gating circuit, for realizing programming to CTF subelement in default compound memory unit, erasing or reading.
(3) beneficial effect
The present invention has following beneficial effect:
The benefit such as 1, the present invention has fully utilized that the high density of floating boom storage mode, high reliability, crosstalk are little, the low-power consumption of tolerance advantages of higher and RRAM storage mode, high speed, structure are simple;
2, the present invention achieves the fusion of two kinds of different storage modes on monolithic chip, thus can meet the storage needs of different modes, improves performance, reduces cost;
3, the present invention is mutually compatible with traditional microelectronic technique in the preparation process of storer, is beneficial to extensive promotion and application.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art CTF storer of the present invention;
Fig. 2 is the principle schematic of prior art CTF storer of the present invention;
Fig. 3 is the structural representation of prior art RRAM storer of the present invention;
Fig. 4 is storage principle first schematic diagram of prior art RRAM storer of the present invention;
Fig. 5 is storage principle second schematic diagram of prior art RRAM storer of the present invention;
Fig. 6 is the structural representation of embodiment of the present invention compound memory unit;
Fig. 7 is the structural representation of embodiment of the present invention compound memory unit;
Fig. 8 is the realization flow figure of embodiment of the present invention compound memory unit;
Fig. 9 is the structural representation of embodiment of the present invention composite memory.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
In a basic embodiment of the present invention, propose a kind of compound memory unit.Fig. 6 is the structural representation of embodiment of the present invention compound memory unit.As shown in Figure 6, the present embodiment compound memory unit comprises: resistance random access memory RRAM subelement and floating boom subelement; RRAM subelement is formed on the drain electrode of floating boom subelement.Wherein, compound memory unit can switch between two kinds of memory modules: RRAM subelement is as memory module, and CTF subelement is as gating module; Or RRAM subelement is in low resistance state, CTF subelement is as memory module.In the present embodiment, floating boom subelement can be traditional floating gate structure, preferably electric charge capture flash memory CTF subelement.
Present embodiment discloses a kind of design proposal of compound memory unit of multifunctional universal formula, by merging the memory technology of floating boom and RRAM in a storage array, the high velocity, low pressure that both can realize RRAM subelement stores, also can realize the storage of the high density high reliability of floating boom subelement, the switching of different storage mode can control to realize by external software according to different storage environments.
In an exemplary embodiment of the present invention, a kind of compound memory unit is provided.Fig. 7 is the structural representation of embodiment of the present invention compound memory unit.As shown in Figure 7, in the present embodiment compound memory unit, an electrode of RRAM subelement is connected with the drain electrode of CTF subelement; RRAM subelement another electrode corresponding with electrode is as the bit line of compound memory unit; And the grid of CTF subelement is as the wordline of compound memory unit.
In the present embodiment, together with being done with the bottom electrode of RRAM by the drain terminal electrode of CTF unit, become a public electrode, thus the storage unit that formation one is new.By the judgement to external environment condition, if need the storage mode of low-voltage high speed, then select RRAM store data, now using CTF unit as gate tube, to avoid the reading cross-interference issue of RRAM, then realize the read-write erase operation of RRAM unit further; As needed, using the unit of CTF as storage data, to be operated by peripheral control circuits and first make it change low resistance state into all RRAM unit R eset, and then carry out program erase read operation to CTF unit.
In another exemplary embodiment of the present invention, provide a kind of composite memory.This composite memory comprises storage array, RRAM peripheral control circuits, floating boom peripheral control circuits and gating circuit.Wherein: storage array comprises above disclosed compound memory unit, along two compound memory unit common-source of bit line direction; Gating circuit, is connected with the word/bit line of each storage unit with RRAM peripheral control circuits, floating boom peripheral control circuits, for realizing the selection to default compound memory unit memory module; RRAM peripheral control circuits, is connected with RRAM subelement with gating circuit, for realizing programming to default RRAM subelement, erasing or reading; CTF peripheral control circuits, is connected with CTF subelement with gating circuit, for realizing programming to default CTF subelement, erasing or reading.
The architectural feature of above-mentioned two embodiments to compound memory unit is described, and the mode of operation providing this compound memory unit is described below.Fig. 8 is the realization flow figure of embodiment of the present invention compound memory unit.As shown in Figure 8, this flow process comprises:
Step S802, sensing external environment condition needs;
Step S804, judges whether to need high velocity, low pressure to store, and if so, performs step S806, otherwise, perform step S812;
Step S806, determines to adopt RRAM storage mode;
Step S808, using CTF subelement as gate tube;
Step S810, corresponding RRAM subelement performs read/write/erase operation, and flow process terminates;
Step S812, determines to adopt CTF storage mode;
Step S814, carries out RESET to all RRAM subelements, makes it enter low resistance state;
Step S816, corresponding CTF subelement performs read/write/erase operation, and flow process terminates.
In the present embodiment, above-mentioned steps S810 specifically comprises: when programmed, source ground, and wordline is connected with providing the circuit of positive bias, and bit line is connected with the circuit of the program voltage providing RRAM subelement; Maybe when wiping, bit line is connected with providing the circuit of erasing voltage; Or when reading, wordline is connected with providing the circuit of positive bias, bit line is connected with providing the circuit reading voltage.Step S816 specifically comprises: when programmed, and CTF subelement adopts FN programming or channel hot electron to inject CHE programming; Maybe when wiping, CTF subelement adopts FN erasing; Or when reading, the wordline of compound memory unit is connected with providing the circuit reading voltage, and bit line is connected with providing the circuit of positive bias, the source ground of CTF subelement.
Below by concrete discussion RRAM subelement and CTF subelement how to realize each generic operation further.Fig. 9 is the structural representation of embodiment of the present invention composite memory.
Wherein, CTF peripheral control circuits is connected with storage array by gating circuit with RRAM peripheral control circuits, the wordline (WL) of storage array is connected with the wordline gate tube of CTF peripheral control circuits and the wordline gate tube of RRAM peripheral control circuits respectively by a gating switch, the bit line (BL) of storage array is connected with the bit line strobe pipe of CTF peripheral control circuits and the bit line strobe pipe of RRAM peripheral control circuits respectively by a gating switch, and gating switch is controlled by gating signal sel.CTF peripheral control circuits and RRAM peripheral control circuits are respectively the peripheral control circuits of traditional NOR type floating-gate memory and the RRAM peripheral control circuits of 1T1R (one transistor one RRAM) structure.
For composite memory as shown in Figure 9, be described in two kinds of situation.
One, when needs high velocity, low pressure storage mode, gating signal sel (as shown in Figure 9) is controlled by external software, when sel is high level " 1 ", RRAM peripheral control circuits is strobed, now select RRAM as storage unit, CTF unit, now as gate tube, forms similar 1T1R structure.SL line ground connection, when programming, the WL of selected cell applies positive bias V
1(as 5V (guarantee be greater than CTF weave into after threshold voltage), raceway groove is opened), corresponding BL adds the program voltage V of RRAM
p(usual 1 ~ 2V), when erasing, corresponding BL adds V
erase, during reading, corresponding WL adds positive bias V
1raceway groove is opened, corresponding BL adds and reads voltage V
read(being generally 0.2V) reads.
Two, when needs CTF is as storage unit time, need first to carry out Reset operation to all RRAM unit and make it all become low resistance state, then gating signal reset, CTF peripheral control circuits is strobed.It is the same that whole device is just equivalent to common CTF device, its program erase read operation is consistent with common CTF device, such as: FN programming (as: WL upper applying voltage 15V can be adopted, SL, BL floating, Substrate ground), CHE programming (as: on the upper and BL of WL applying 10V and 8V, SL and Substrate ground).Erasing can select FN to wipe (as: WL applying voltage-15V, BL, SL floating, Substrate ground); During reading, WL applies V
read, BL adds about 1V voltage (different structure and material have certain difference), SL ground connection.
In the present embodiment, fully utilize the advantage of CTF memory device and RRAM memory device, monolithic chip achieves two kinds of different storage modes, thus the storage needs of different modes can be met, improve performance, reduce cost, and its preparation process is mutually compatible with traditional microelectronic technique, is beneficial to extensive promotion and application.
In the present invention, selected CTF unit can be chosen as traditional SONOS (Si/SiO
2/ Si
3n
4/ SiO
2/ Si) structure, or TANOS (TaN/AL
2o
3/ Si
3n
4/ SiO
2/ Si) structure, MANOS (Metal/AL
2o
3/ Si
3n
4/ SiO
2/ Si) structure, TAHOS (TaN/AL
2o
3/ HIGH-K/SiO
2/ Si) structure, MAHOS structure or the similar rhythmo structure such as BE-SONOS structure, MAOHOS structure are all within range of choices, and nanocrystalline structure, introduces the similar structures such as nanocrystalline SONOS, TANOS in addition.Wherein, required High-K material can choose AL
2o
3, HFO
2, TIO
2, different component the doping such as HfALO, HfSiO, HfSiON after novel high K dielectric.
In the present invention, selected RRAM subelement can be unipolar device, bipolar device and electrodeless device.The change resistance layer material of RRAM subelement can be perovskite oxide: R
1-xca
xmnO
3(R=Pr/La/Nd), La
0.67sr
0.33mnO
3, SrTiO
3, SrZrO3, LiNbO
3, BaTiO
3; Transition metal binary oxide: NiOTiO
2, CuO
x, ZrO
2, Nb
2o
5, Ta
2o
5, Al
2o
3, CoO, HfO
2, MgO, VO
2, ZnO; Solid electrolyte: SiO
2, WO
3, CuI
0.76s
0.1, Ag – Ge – Se, Ag-Ge-S, Ag
2s, Cu
2s, Sb
35te
65; Organism: AIDCN, PVK, PS, PCm, F12TPN, PI-DPC, CuTCNQ, AgTCNQ, o-PPV, P
3hT; Also have other as: a-Si:H, μ c-Si etc. has the material of similarity.
In the present invention, the material of selected public electrode can choose precious metal Pt, Ag, Pd; Metal W conventional in CMOS technology, Ti, Al, Cu; Metal oxide ITO, IZO, YBCO, LaAlO
3, SrRuO
3and polycrystalline Si material.
Current DRAM, Flash need different technological processes, and in system-on-a-chip (System on chip is called for short Soc) field, its cost is difficult to reduce.RRAM and Flash memory function merges in a unit by the present invention, both the high speed storing function of DRAM can have been realized, also Flash high-density city function can be realized, and by the control of external software, the exchange of these two kinds of functions can be realized, optimize the configuration of whole storage organization further.Meanwhile, because just complete preparation by a kind of technological process, cost is effectively reduced.And this technological process is mutually compatible with traditional microelectronic technique, be more conducive to extensive promotion and application.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a composite memory, is characterized in that, this composite memory comprises storage array, RRAM peripheral control circuits, CTF peripheral control circuits and gating circuit, wherein:
Described storage array comprises several compound memory unit, and this compound memory unit comprises: CTF subelement; And the resistance random access memory RRAM subelement on the drain electrode being formed at this CTF subelement; Wherein, when described RRAM subelement is as memory module, described CTF subelement is as gating module; And described RRAM subelement is when being in low resistance state, described CTF subelement is as memory module, and along two compound memory unit common-source of bit line direction, an electrode of described RRAM subelement is connected with the drain electrode of described CTF subelement; Described RRAM subelement another electrode corresponding with described electrode is as the bit line of described compound memory unit; And the grid of described CTF subelement is as the wordline of described compound memory unit;
Described gating circuit, is connected with the word/bit line of each storage unit with described RRAM peripheral control circuits, floating boom peripheral control circuits, for realizing the selection to presetting described compound memory unit memory module;
Described RRAM peripheral control circuits, is connected with RRAM subelement with described gating circuit, for realizing programming to RRAM subelement in default compound memory unit, erasing or reading;
Described CTF peripheral control circuits, is connected with CTF subelement with described gating circuit, for realizing programming to CTF subelement in default compound memory unit, erasing or reading;
Wherein, CTF peripheral control circuits is connected with storage array by gating circuit with RRAM peripheral control circuits, the wordline of storage array is connected with the wordline gate tube of CTF peripheral control circuits and the wordline gate tube of RRAM peripheral control circuits respectively by a gating switch, the bit line of storage array is connected with the bit line strobe pipe of CTF peripheral control circuits and the bit line strobe pipe of RRAM peripheral control circuits respectively by a gating switch, and gating switch is controlled by gating signal sel:
One, when needs high velocity, low pressure storage mode, control gating signal sel is high level " 1 ", and RRAM peripheral control circuits is strobed, and now select RRAM subelement as memory module, CTF subelement is now as gating module;
Two, when needs CTF subelement is as memory module, carry out Reset operation to all RRAM unit and make it all become low resistance state, control gating signal sel reset, CTF peripheral control circuits is strobed, and now selects CTF subelement as memory module.
2. composite memory according to claim 1, is characterized in that, described RRAM subelement as memory module, when described CTF subelement is as gating module, then:
When programmed, source ground, described wordline is connected with providing the circuit of positive bias, and described bit line is connected with the circuit of the program voltage providing RRAM subelement; Or
When wiping, described bit line is connected with providing the circuit of erasing voltage; Or
When reading, described wordline is connected with providing the circuit of positive bias, and described bit line is connected with providing the circuit reading voltage.
3. composite memory according to claim 1, is characterized in that, described RRAM subelement is in low resistance state, when described CTF subelement is as memory module, then:
When programmed, CTF subelement adopts Fowler-Nordheim FN programming or channel hot electron to inject CHE programming; Or
When wiping, CTF subelement adopts FN erasing; Or
When reading, the wordline of described compound memory unit is connected with providing the circuit reading voltage, and bit line is connected with providing the circuit of positive bias, the source ground of CTF subelement.
4. composite memory according to any one of claim 1 to 3, is characterized in that, described CTF subelement is the one of following structure: rhythmo structure, nanocrystalline structure or introduce nanocrystalline rhythmo structure.
5. composite memory according to claim 4, is characterized in that: described rhythmo structure is the one in following structure: Si/SiO
2/ Si
3n
4/ SiO
2/ Si structure, TaN/AL
2o
3/ Si
3n
4/ SiO
2/ Si structure, Metal/AL
2o
3/ Si
3n
4/ SiO
2/ Si or TaN/AL
2o
3/ HIGH-K material/SiO
2/ Si.
6. composite memory according to any one of claim 1 to 3, is characterized in that, described RRAM subelement is unipolar device, bipolar device or electrodeless device;
The change resistance layer material of described RRAM subelement is the one in following material: perovskite oxide, transition metal binary oxide, solid electrolyte, organism or a-Si:H, μ c-Si.
7. composite memory according to claim 6, is characterized in that:
Described perovskite oxide is the one in following material: R
1-xca
xmnO
3(R=Pr/La/Nd), La
0.67sr
0.33mnO
3, SrTiO
3, SrZrO3, LiNbO
3, BaTiO
3;
Described transition metal binary oxide is the one in following material: NiOTiO
2, CuO
x, ZrO
2, Nb
2o
5, Ta
2o
5, Al
2o
3, CoO, HfO
x, MgO
x, MoO
x, VO
2, ZnO;
Described solid electrolyte is the one in following material: SiO
2, WO
3, CuI
0.76s
0.1, Ag – Ge – Se, Ag-Ge-S, Ag
2s, Cu
2s, Sb
35te
65;
Described organism is the one in following material: AIDCN, PVK, PS, PCm, F12TPN, PI-DPC, CuTCNQ, AgTCNQ, o-PPV, P
3hT.
8. composite memory according to any one of claim 1 to 3, is characterized in that: described electrode is the one in following material: Pt, Ag, Pd, W, Ti, Al, Cu, ITO, IZO, YBCO, LaAlO
3, SrRuO
3or polycrystalline Si.
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| CN105789434B (en) * | 2014-12-25 | 2018-08-28 | 北京有色金属研究总院 | A kind of resistance-variable storing device and preparation method thereof based on hybrid perovskite material |
| CN110233980B (en) * | 2019-06-27 | 2021-11-02 | Oppo广东移动通信有限公司 | Active pixel image sensor, image processing method and storage medium |
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| US20060054950A1 (en) * | 2004-09-10 | 2006-03-16 | In-Gyu Baek | Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same |
| CN1815741A (en) * | 2005-01-06 | 2006-08-09 | 三星电子株式会社 | Nor-type hybrid multi-bit non-volatile memory device and method of operating the same |
| CN101110266A (en) * | 2006-07-20 | 2008-01-23 | 华邦电子股份有限公司 | Multi-level operation in nitride storage memory cell |
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| US20060054950A1 (en) * | 2004-09-10 | 2006-03-16 | In-Gyu Baek | Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same |
| CN1815741A (en) * | 2005-01-06 | 2006-08-09 | 三星电子株式会社 | Nor-type hybrid multi-bit non-volatile memory device and method of operating the same |
| CN101110266A (en) * | 2006-07-20 | 2008-01-23 | 华邦电子股份有限公司 | Multi-level operation in nitride storage memory cell |
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| C06 | Publication | ||
| PB01 | Publication | ||
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