CN104112476B - The super low-power consumption pseudo differential architectures nonvolatile memory of compatibility standard CMOS technology - Google Patents
The super low-power consumption pseudo differential architectures nonvolatile memory of compatibility standard CMOS technology Download PDFInfo
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Abstract
The invention discloses a kind of super low-power consumption pseudo differential architectures nonvolatile memory of compatibility standard CMOS technology, solve the problems, such as that power consumption is high, reduce the area of memory cell structure, including multiple memory cell, each memory cell reads five pipe, the second reading pipe, first choice pipe and the second selecting pipe transistors by control pipe, first and formed, all transistors are single polysilicon grating structure and the gate oxide of same thickness, and the memory cell is compatible with standard CMOS process；The programming and erasing operation of the present invention utilizes FN tunneling effects, solves the problems, such as that power consumption is high；Similar differential configuration is formed merely with five transistors, integrated level is high, and area is small, reliability enhancing, improves reading speed.
Description
Technical field
The invention belongs to microelectronics technology, is related to the memory technology of semiconductor integrated circuit, more specifically, being compatible
The super low-power consumption pseudo differential architectures nonvolatile memory of standard CMOS process.
Background technology
Many integrated-optic devices need a certain amount of nonvolatile memory.Usual non-volatile memory is used as
The separate storage body of chip exterior or as the memory bank in label chip, mainly in the chips in the power supply of no power supply
In the case of store relevant information of some control programs, process instruction or article etc. for a long time.
Current several usually used non-volatility memorizers mainly have Erasable Programmable Read Only Memory EPROM EPROM, electricity
Erasable Programmable Read Only Memory EPROM EEPROM and flash memory Flash Memory.Other also ferroelectric memory FeRAM,
The new nonvolatile memory that magnetic RAM MRAM and phase transition storage OUM etc. occur in recent years, it is studied all
Have been achieved for gratifying progress.But they all can not be compatible with standard CMOS process, commonly required special process can increase
Add more procedure of processings and mask quantity, cause being significantly increased for cost, the appearance of especially used nonvolatile memory
Amount is not when being not too big, than as used in passive radio-frequency identification labeled chip, a cost inherently very crucial limitation because
Element.Low-cost, small area, low-power consumption, the nonvolatile memory of high reliability are imperative.
In order to solve the Railway Project being discussed above, also have more scheme propose can be compatible with standard technology deposit
Storage unit structure, avoids the increase of additional step and the mask number of plies, and the chip with being realized under cmos process flow
It is integrated more convenient.But their programmings for using, the principle of erasing focus mostly on thermoelectron injection effect and FN (FN,
Fowler-Nordheim) tunneling effect.But at a relatively high electric current is needed using thermoelectron injection effect, energy consumption is too big, and
FN tunneling effects can then occupy sizable area, and these factors can all influence the popularization and application of nonvolatile memory.
The content of the invention
Deposit it is an object of the invention to provide a kind of super low-power consumption pseudo differential architectures of compatibility standard CMOS technology are non-volatile
Reservoir solves the deficiency of above-mentioned prior art, and its programming and erasing operation utilizes FN tunneling effects, and it is high to solve power consumption
Problem；Similar differential configuration is formed just with five transistors, due to not being full symmetric structure therefore turning into pseudo-differential
Structure, area is small, and integrated level is high, and output difference signal increases its reliability, and contributes to the spirit with the use of differential configuration
Quick amplifier, improve reading speed.
Specific technical scheme is as follows：
A kind of super low-power consumption pseudo differential architectures nonvolatile memory of compatibility standard CMOS technology, including multiple storages are single
Member, each memory cell read pipe M02, the second reading pipe M03, the choosings of first choice pipe M04 and second by control pipe M01, first
Five transistor compositions of pipe M05 are selected, wherein control pipe M01 is to be connected to form the device of capacitive form by source electrode, drain electrode, the end of trap three
Part, its source electrode P03, drain electrode P01, trap P02 three-terminal links, forms control port CG；First reads pipe M02 source electrode P04 and its
Trap P05 is connected, and forms the first read port RP1；Second reading pipe M03 drain electrode P10 is connected to the second read port
RP2；Control pipe M01, the first gate interconnection formation one for reading reading pipe tri- transistors of M03 of pipe M02 and second are closed
Floating boom FG；Two selecting pipes M04 and M05 gate interconnection form selection port SEL；Second reads pipe M03, first choice pipe
M04 and the second selecting pipe M05 shares the first p-well of substrate PW；First choice pipe M04 drain electrode P07 and first reads pipe M02
Drain electrode P06 be connected；Second selecting pipe M05 drain electrode P13 is connected with the second reading pipe M03 source electrode P12；First choice pipe
Output port DO1 and output port of M04 and the second selecting pipe M05 source electrode respectively as two differential signals of memory cell
DO0。
The gate area of control pipe M01 in the memory cell is more than the first grid face for reading pipe M02 and the 2nd M03
Product.
The control pipe M01, the first reading pipe M02 be PMOS transistor, the second reading pipe M03, first choice pipe M04 and
Second selecting pipe M05 is nmos pass transistor.
The control pipe M01 is resided in the first N traps NW1；First reading pipe M02 is resided in the 2nd N traps NW2；Second
Pipe M03 and first choice pipe M04 and the second selecting pipe M05 is read to reside in the first p-well PW.
By shallow trench region domain separation between described the first N traps, the 2nd N traps, described p-well is currently used double trap works
Optimize the p-well of the electrology characteristic of transistor in skill using doping techniques, generally require high-energy, heavy dose of injection, it is deep
Enter the general microns of epitaxial layer, specific data will determine according to the technique of correlation.The nmos pass transistor is resident
Among identical p-well.
Control pipe M01, the first reading pipe M02 and second in the memory cell read pipe M03, first choice pipe M04
With the second selecting pipe M05 gate oxide thickness all same.
Control pipe M01, the first reading pipe M02 and second in the memory cell read pipe M03, first choice pipe M04
It is single-layer polysilicon gate structure with the second selecting pipe M05.
Tri- control port CG, the first read port RP1, the second read port RP2 ports in the memory cell by
In the coupling of electric capacity, the potential after coupling is superimposed the potential to be formed on floating boom FG.
Floating boom FG in the memory cell adulterates for N-type impurity.
All transistors of the memory cell are resided on same silicon substrate SUB.
N trap capacitance structures of the control pipe M01 using N traps capacitance structure or with source and drain injection.
The control port CG of described memory cell extraction, the first read port RP1, the second read port RP2, selection end
Mouth SEL applies different combinations of voltages when carrying out different operations.
The technique effect obtained using the present invention：
(1) present invention is proposed based on existing standard CMOS process, therefore need not in the design application of chip
Extra addition mask and processing step, greatly reduce application cost, and reduce the technology development cycle, shorten the listing of chip
Time, it is extremely applicable to the stricter occasion of cost control.(2) present invention is a kind of pseudo differential architectures, just with three
Transistor forms floating boom, and the current signal of output difference, area occupied is much smaller compared to the structure of fully differential, so it collects
Programming and erasing operation into high (3) structure of the present invention of density uses FN tunneling effects, avoids to inject using thermoelectron and imitates
The shortcomings that power consumption caused by answering is too high.(4) floating boom is n-type doping in the present invention, greatly improves the effect of tunnelling.It can contract
Short erase-write cycles, can be with high voltage during a certain degree of reduction programmed and erased.(5) memory cell of the invention is difference
The output of signal, and the difference of the differential signal exported is very big, so the reading speed of unit, than very fast, reliability is high.
(6) present invention proposes a kind of new N traps capacitance structure with source and drain injection, and this structure capacitive is in the case of bias high voltage
It can rapidly reach stable, be advantageous to improve erasable speed.
Brief description of the drawings
Fig. 1 is the structure chart of single memory cell in the present invention；
Fig. 2 is the cross-sectional structure figure of memory cell in the present invention；
Fig. 3 is the device schematic cross-section and schematic top plan view that control pipe M01 is MOS capacitance structure in the present invention；
Fig. 4 is the device schematic cross-section and schematic top plan view that control pipe M01 is N trap capacitance structures in the present invention；
Fig. 5 is that control pipe M01 is the device schematic cross-section of the N trap capacitance structures with source and drain injection and bowed in the present invention
Depending on schematic diagram；
Fig. 6 is the first top view for reading that pipe M02 grids are n-type doping in the present invention；
Fig. 7 is the overall structure diagram of the present invention.
Embodiment
The super low-power consumption pseudo-differential of the compatibility standard CMOS technology of the embodiment of the present invention is described in detail below with reference to accompanying drawing
Structure nonvolatile memory.
Reference picture 7, the present invention are made up of identical memory cell, and the memory cell of this example is 16, that is, is stored
Device capacity is 16 bits, but be not restricted to that 16 bits, actual memory capacity can increase according to demand, and can utilize
Block storage array increases memory capacity.It can be seen from figure 7 that in per a line, the control port CG of all memory cell is mutual
It is connected together；All selection port SEL link together；In each row, the first all read port RP1 is connected to
Together；All second read port RP2 link together, and thus constitute the structure of whole memory.
Reference picture 1, each memory cell only include 5 transistors, all transistors be single polysilicon grating structure and
The gate oxide of same thickness, therefore the memory cell is compatible with standard CMOS process.
Each memory cell reads pipe M02 by control pipe M01, first, second reads pipe M03, first choice pipe M04 and the
Two transistors of selecting pipe M05 five form.Wherein control pipe M01 is to be connected to form capacitive form by source electrode, drain electrode, the end of trap three
Device, its source electrode P03, drain electrode P01, trap P02 three-terminal links, forms control port CG；First read pipe M02 source electrode P04 with
Its trap P05 is connected, and forms the first read port RP1；Second reading pipe M03 drain electrode P10 is connected to the second read port
RP2；Control pipe M01, the gate interconnection of two reading transistor tri- transistors of M02 and M03 form the floating boom FG of a closing；
Two selecting pipes M04 and M05 gate interconnection form selection port SEL；Second reads pipe M03, first choice pipe M04 and second
Selecting pipe M05 shares the first p-well of substrate PW；First choice pipe M04 drain electrode P07 and first reads pipe M02 drain electrode P06
It is connected；Second selecting pipe M05 drain electrode P13 is connected with the second reading pipe M03 source electrode P12；Two selecting pipes M04's and M05
Output port DO1 and output port DO0 of the source electrode respectively as two differential signals of memory cell.
All transistors of the memory cell are resided on identical silicon substrate SUB.
Two selecting pipes M04 and M05 are worked in the state of information in reading memory cell.
In reading state, read port can be connected to supply voltage, and to read pipe M02 be PMOS transistor, the due to first
Two to read pipe M03 be nmos pass transistor, and they share floating boom, on floating boom because containing electronics number there is low or high electricity
Position, the first reading pipe M02, the second reading pipe M03 is set always to only have a transistor to be opened, another, which is in, closes shape
State, therefore they can export the larger current signal of difference.First choice pipe M04 and the second selecting pipe M05 are in selection port SEL
The make decision data of two phase inverters output of control whether be transferred to bit line BL1, bit line BL0 up.
In write state, it is not necessary to transfer data to bit line, therefore low-voltage will be biased in selection port SEL to make
Two transistors of M04 and M05 are closed, and prevent that high voltage causes high current power consumption in write-in.
As shown in Fig. 2 each memory cell cross-sectional structure figure of the present invention, from fig. 2 it can be seen that storage unit structure
In control pipe M01 be placed in the first N traps NW1；First reading pipe M02 is placed in the 2nd N traps NW2；Second reads pipe M03
It is placed on first choice pipe M04 and the second selecting pipe M05 in the first p-well PW.Control pipe M01 and first reads pipe M02 and the
The proportionate relationship of two reading pipe M03 gate areas is adjusted according to specific circumstances.It can also be seen that control pipe from Fig. 2
Gate area read than first pipe, second read pipe gate area it is big many (being more than 5 times), can so increase control
The voltage coupling coefficient to floating gate potential is held, substantially reduces the high pressure required in programmed and erased.Each transistor is specific
Dimension scale according to the different designers Reasonable adjustment of the technique of application.
Floating boom FG in the memory cell adulterates for N-type impurity.
First in the memory cell structure, which reads pipe M02 and second, reads pipe M03 in the operation of programmed and erased
Also function as tunneling tube.The first read port RP1 is as tunnelling port when erasing；Second read port RP2 when programming
As tunnelling port.
Control pipe M01 in memory cell structure, which can be used, three types：
Type one：It is illustrated in figure 3 the MOS electricity that source electrode, drain electrode and the interconnection of the end of trap three of the PMOS transistor of standard are formed
Hold structure, in figure source electrode, drain electrode and the contact of N traps connect into port A, grid needs list as another port B, this structure
Only trap of making contacts and needs corresponding contact hole and metal connecting line；Type two：N trap capacitance structures are illustrated in figure 4, in figure
The contact of N traps is used as port C, and for grid as another port D, this structure can remove contact hole and metal in type one from
Line, the area of occupancy are smaller；Type three：The N trap capacitance structures with source and drain injection as shown in Figure 5, in figure the contact of N traps with
Source and drain injection is connected together as port F with metal, and grid is as another port E, and this structure is due in polysilicon
Source and drain is provided with around grid to inject, can be with so there is enough electronics and hole in a silicon substrate for the use of grid oxygen layer capacitance
Stable state is quickly formed in the case of bias voltage, so as to improve erasable speed.
First reads the top view of pipe M02 grid doping as shown in fig. 6, key parameter d therein size is according to work
The requirement of skill determines that parameter d effect is primarily to meet the self-registered technology requirement during source, leakage doping；N_well
Refer to N well region；Active refers to active area；SD_DOP refers to source and drain injection；Contact refers to contact hole；N+_DOP is referred to
Grid carries out the region of first kind doping type；Poly refers to polysilicon region.
Control pipe M01, the first reading pipe M02, the second reading pipe M03, first choice pipe in the memory cell structure
M04 and the second selecting pipe M05 answer its shape of rational deployment and relative position, to reduce the influence of parasitic capacitance.
Memory cell of the present invention each port biasing when writing " 0 ", one writing and read operation is listed in table 1
Voltage condition.Wherein, CG control gates port, RP1 are the first read port, and RP2 is the second read port, and SEL is selection port,
VDDFor the supply voltage of circuit work, by designer, the technology library used by design chips requires to select its size,
Supply voltage V in the present embodimentDD=1.5V, VGNDFor the ground voltage 0V, V of circuit workPEWipe and needed when programming
Higher than VDDHigh voltage, the V used in the present embodimentPE=10V.Provided in the present invention：Electron tunneling enters floating boom and represents write-in
Data " 1 ", electron tunneling leave floating boom and represent write-in data " 0 ".
The memory cell operating voltage of table 1
Operating condition of the invention given below：
1st, " 0 " operation is write
It is exactly to wipe out the electric charge on floating boom by tunneling effect to write " 0 " operation.Now to establish erasing floating gate charge
Condition just need the voltage according to table 1 to be biased each port.Control port CG, the second read port RP2 are equal
Bias ground voltage VGNDBy voltage coupling by the potential control on floating boom in very low level, in the first read port RP1
Bias high voltage VPE, so as to establish higher voltage drop between the first reading pipe M02 silicon substrate and floating boom FG, cause
Tunneling effect occurs on first reading pipe M02, electric charge is wiped free of from floating boom, during electronics is wiped free of from floating boom,
Current potential on floating boom FG finally makes floating boom and first read voltage subtractive between pipe M02 silicon substrate also in raising slowly
As low as it is insufficient for occurring the condition of tunneling effect, erase process terminates, and data " 0 " are successfully written to memory cell.Due to
First choice pipe M04, the second selecting pipe M05 are not involved in tunneling effect, but because the first read port RP1 is biased high electricity
Pressure, so first choice pipe M04 will prevent the high voltage from causing high current to reduce power consumption, therefore biased in selection port SEL
VGNDTurn it off.
2nd, one writing operates
One writing operation is exactly electronics is entered by tunneling effect in floating boom.Now to establish the bar of erasing floating gate charge
Part just needs the voltage according to table 1 to be biased each port.Control port CG, the first read port RP1 are biased
High voltage VPE, by voltage coupling by the potential control on floating boom in very high current potential, the second read port RP2 is ground
Voltage VGND, so as to establish higher voltage drop between floating boom and the second reading pipe M03 silicon substrate, in corresponding grid oxygen
Change and very strong electric field is formed on layer, trigger tunneling effect, electronics enters floating boom from substrate tunnelling, in electronics from the mistake into floating boom
Current potential on Cheng Zhong, floating boom FG finally makes the voltage difference between floating boom and the second reading pipe M03 substrate also in reduction slowly
It is decreased to be insufficient for the condition that tunneling effect occurs, programming process terminates, and data " 1 " are successfully written to memory cell.By
Tunneling effect is not involved in first choice pipe M04, the second selecting pipe M05, but because the first read port RP1 is biased height
Voltage, so first choice pipe M04 will suppress the high voltage and cause high current to reduce power consumption, therefore it is inclined in selection port SEL
Put VGNDTurn it off.
3rd, read operation
High voltage is not needed during read operation, control port CG is biased in ground voltage VGND.Now first read pipe M02
Pipe M03 is read as pipe is read with second, there can be high or low current potential on the floating boom of the memory cell after being written into, so as to
Some device in reading pipe M02 and M03 is set to turn into normal open device, another turns into normally closed device, and the data of reading are reflected in
Export differentiated current signal.After this memory cell is selected, selection port SEL is biased to supply voltage VDDAllow this
The current signal of memory cell output enters bit line, then quickly reads data by sense amplifier.
After row write " 0 " operation is entered, electric charge is wiped free of on floating boom FG, and the potential of its own is higher, so that first reads
Pipe M02 is in normally off, and the second reading pipe M03 is in normal open state, after the selected reading of the memory cell, selects end
Mouth SEL signals are high voltage, and output port DO1 output sub-threshold current leakages, output port DO0 exports saturation current, by position
Line BL1 and BL0 conduction, the signal of two-pass DINSAR enter sense amplifier, quickly read data " 0 ".
After one writing operation is carried out, electric charge increases by programming process on floating boom FG, and the potential of its own is relatively low, from
And the first reading pipe M02 is in normal open state, and the second reading pipe M03 is in normally off, the memory cell is selected to be read
After taking, selection port SEL signals are high voltage, and output port DO0 output sub-threshold current leakages, output port DO1 exports full
And electric current, by bit line BL1 and BL0 conduction, the signal of two-pass DINSAR enters sense amplifier, quickly reads data " 1 ".
Although the above is the complete description to specific embodiments of the present invention, can take it is various modification, variant and
Alternative.These equivalents and alternative are included within the scope of the disclosure.Therefore, the scope of the present invention should not
Described embodiment is limited to, but should be defined by the appended claims.
Claims (10)
1. a kind of super low-power consumption pseudo differential architectures nonvolatile memory of compatibility standard CMOS technology, including multiple storages are single
Member, it is characterised in that：Each memory cell reads pipe M02, the second reading pipe M03, first choice pipe by control pipe M01, first
Five transistor compositions of M04 and the second selecting pipe M05；Wherein control pipe M01 is to be connected to form electricity by source electrode, drain electrode, the end of trap three
The device of appearance form, its source electrode P03, drain electrode P01, trap P02 three-terminal links, forms control port CG；First reads pipe M02 source
Pole P04 connects with its trap P05, forms the first read port RP1；Second reading pipe M03 drain electrode P10 is connected to the second reading
Take port RP2；Control pipe M01, the first gate interconnection formation one for reading pipe M02, second reading pipe tri- transistors of M03 are sealed
The floating boom FG closed；First choice pipe M04, the second selecting pipe M05 gate interconnection form selection port SEL；Second reads pipe
M03, first choice pipe M04, the second selecting pipe M05 are shared with the first p-well PW；First choice pipe M04 drain electrode P07 and first is read
Pipe M02 drain electrode P06 is taken to be connected；Second selecting pipe M05 drain electrode P13 is connected with the second reading pipe M03 source electrode P12；First
Selecting pipe M04, the second selecting pipe M05 source electrode respectively as two differential signals of memory cell output port DO1, output
Port DO0.
2. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：Control in the memory cell
Tubulation M01 gate area is more than first and reads pipe M02, the second reading pipe M03 gate area.
3. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：The control pipe M01, first
It is PMOS transistor to read pipe M02, and the second reading pipe M03, first choice pipe M04, the second selecting pipe M05 are NMOS crystal
Pipe.
4. pseudo differential architectures nonvolatile memory as claimed in claim 3, it is characterised in that：The control pipe M01 is resident
In the first N traps NW1；First reading pipe M02 is resided in the 2nd N traps NW2；Second reading pipe M03 and first choice pipe M04,
Second selecting pipe M05 is resided in the first p-well PW.
5. pseudo differential architectures nonvolatile memory as claimed in claim 4, it is characterised in that：Described the first N traps, second
By trench isolations between N traps, the second reading pipe M03, first choice pipe M04, the second selecting pipe M05 make in identical the
Among one p-well PW.
6. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：Control in the memory cell
Tubulation M01, first read the gate oxidation thickness that pipe M02 and second reads pipe M03, first choice pipe M04 and the second selecting pipe M05
Spend all same.
7. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：Control in the memory cell
It is individual layer polycrystalline that tubulation M01, the first reading pipe M02 and second, which read pipe M03, first choice pipe M04 and the second selecting pipe M05,
Silicon gate structure.
8. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：The control pipe M01 is used
N trap capacitance structures with source and drain injection.
9. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：Control in the memory cell
Port CG processed, the first read port RP1, tri- ports of the second read port RP2 by electric capacity coupling, after coupling
Potential is superimposed the potential to be formed on floating boom FG.
10. pseudo differential architectures nonvolatile memory as claimed in claim 1, it is characterised in that：Described memory cell is drawn
The control port CG that goes out, the first read port RP1, the second read port RP2, selection port SEL are when carrying out different operations
Apply different combinations of voltages.
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| CN104299646B (en) * | 2014-10-24 | 2017-12-22 | 中国人民解放军国防科学技术大学 | Super low-power consumption nonvolatile memory based on standard technology |
| CN104392747B (en) * | 2014-10-24 | 2018-04-03 | 中国人民解放军国防科学技术大学 | The nonvolatile memory of the low erasable voltage of low-power consumption based on standard technology |
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| CN1825487A (en) * | 2006-02-23 | 2006-08-30 | 复旦大学 | Non-volatile memory unit |
| CN101329913A (en) * | 2007-06-18 | 2008-12-24 | 隆智半导体公司 | CMOS compatible single-layer polysilicon non-volatile memory |
| US7483310B1 (en) * | 2006-11-02 | 2009-01-27 | National Semiconductor Corporation | System and method for providing high endurance low cost CMOS compatible EEPROM devices |
| CN101373634A (en) * | 2007-08-20 | 2009-02-25 | 隆智半导体公司 | CMOS logic compatible non-volatile memory cell structure, operation, and array configuration |
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| US20040004861A1 (en) * | 2002-07-05 | 2004-01-08 | Impinj, Inc. A Delware Corporation | Differential EEPROM using pFET floating gate transistors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1825487A (en) * | 2006-02-23 | 2006-08-30 | 复旦大学 | Non-volatile memory unit |
| US7483310B1 (en) * | 2006-11-02 | 2009-01-27 | National Semiconductor Corporation | System and method for providing high endurance low cost CMOS compatible EEPROM devices |
| CN101329913A (en) * | 2007-06-18 | 2008-12-24 | 隆智半导体公司 | CMOS compatible single-layer polysilicon non-volatile memory |
| CN101373634A (en) * | 2007-08-20 | 2009-02-25 | 隆智半导体公司 | CMOS logic compatible non-volatile memory cell structure, operation, and array configuration |
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