JP2012221525A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an excessive current from flowing when a transition from high resistance to low resistance in a resistance change element is caused in a semiconductor storage device that uses a variable resistive element as a storage element.SOLUTION: When a bit line and a word line are selected and the resistance value of a corresponding resistance change element is written so as to change the value from high resistance to low resistance, the selected word line is caused to transition from a first voltage at a non-selection level to a third voltage that is between the first voltage and a second voltage at a selection level, so that the resistance value of the corresponding resistance variable element is changed to a resistance value at an intermediate stage between the high resistance and the low resistance. Then, the selected word line is caused to transition from the third voltage to the second voltage, so that the resistance value of the corresponding resistance change element is changed to the low resistance.

Description

  The present invention relates to a semiconductor device, a control method thereof, and a memory system. In particular, the present invention relates to a semiconductor device including a resistance change element as a memory element.

  As a current large-capacity semiconductor memory device, a DRAM is the most common and widely used in computer systems and the like. In addition, flash memories are widely used as nonvolatile semiconductor memory devices. However, it is said that DRAMs and flash memories, which are currently mainstream, reach the miniaturization limit in the next few years. Accordingly, various high-capacity semiconductor memory devices that can replace DRAMs and flash memories have been developed. Among these, resistance variable memories (RRAM or ReRAM) using a phenomenon in which a resistance change occurs when a voltage is applied to a transition metal oxide such as a perovskite oxide or NiO are attracting attention. In the resistance change memory, the resistance change state is retained even after the power is turned off, so that it becomes a nonvolatile memory. Such a resistance change memory is also described in Non-Patent Document 1 and Non-Patent Document 2.

  FIG. 4A shows an example of the structure of the memory cell of this resistance change memory. In the memory cell 40, a resistance change element 41 and a cell transistor 42 are connected in series between a bit line 31 and a source line 33. A resistance value is written (programmed) in the resistance change element 41 by passing a current through the resistance change element 41. Further, the resistance value is read by passing a current through the resistance change element 41.

  FIG. 4B shows an example of the internal structure of the resistance change element 41. The resistance change element 41 is sandwiched between a first electrode 45 connected to the bit line 31, a second electrode 46 connected to a cell transistor (not shown), and the first electrode 45 and the second electrode 46. And an insulating film 47. In the case where a transition metal oxide is used for the insulating film 47, it has been announced that the first electrode 45, the second electrode 46, and the material used for the insulating film 47 have various characteristics depending on the combination.

  For writing (programming) of the variable resistance element, writing that changes a high resistance state (hereinafter also referred to as RRST (Register to ReSeT)) to a low resistance state (hereinafter also referred to as RSET) and low resistance. Two types of writing are required: writing that changes a certain state (RSET (Register to SeT)) to a high-resistance state (RRST). In the following description, writing to change the high resistance state (PRST) to the low resistance state (RSET) is SET writing (hereinafter also referred to as “Set”), and the low resistance state is changed to the high resistance state. The writing to be performed is also referred to as RESET writing (hereinafter also referred to as Reset).

  In this set and reset write operation, the unipolar type that writes by applying a voltage to the variable resistance element in the same direction in the set and reset, and the write in the reverse direction is applied to the variable resistance element in the set and reset. And bipolar type. A bipolar write operation will be described with reference to FIG. In FIG. 4C, the voltage applied between the electrodes of the resistance change element is plotted on the horizontal axis, and the current value flowing between both ends is plotted on the vertical axis. First, assume that the variable resistance element is in a reset state. The resistance value is high. In this reset state, when a positive voltage VDSET is applied between the terminals of the variable resistance element (point A in FIG. 4C), the variable resistance element is set from a high resistance state to a low resistance state. (Transition from point A to point B in FIG. 4C). The maximum current flowing at this time is ICOMP.

  On the other hand, when writing from the set state to the reset state, a voltage is applied in the opposite direction to writing to the set state. That is, the voltage VDRST is applied to the variable resistance element in the set state in the opposite direction to the set (point C in FIG. 4C. The current flowing at this time is IRST. Then, the variable resistance element is reset from the set state. The resistance value returns to a large state (transition from point C to point D in Fig. 4 (c)) The reading operation of the resistance element is performed by applying a small voltage equal to or lower than VDSET to the resistance element, It is determined whether it is in a set state or a reset state.

  Non-Patent Documents 1 and 2 describe that in a memory using a resistance change element as a memory element, the resistance value after SET writing (RSET resistance value) depends on the maximum current value at the time of writing. . Non-Patent Documents 3 and 4 are not directly related to a semiconductor device using a resistance change element as a memory element, but the variation amount of Vth (threshold voltage) of the MOS transistor depends on the channel area. Is described. Non-Patent Documents 3 and 4 are cited as descriptions of comparative examples in the description of the embodiments.

U. Russo et al. “Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory” IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 56, NO. 5, P1040-1047 2009 H. Y. Lee et al., “Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM 8 INTERNIONAL ELECTRONDE EMETRON DEVELET Tomohisa Mizuno, “Physics of Fluctuation of Transistor Characteristics” Applied Physics Vol. 75, No. 9, P1103-1108 2009 Kenji Taniguchi “Introduction to CMOS Analog Circuits” P146 CQ Publishing

  In a semiconductor device using a resistance change element as a memory element, when the resistance change element is transitioned from a high resistance state to a low resistance state, the resistance value after the transition is described in Non-Patent Documents 1 and 2. Thus, it depends on the maximum applied current amount at the time of transition. However, according to the inventor's analysis, when the resistance value of the resistance change element rapidly changes from a high resistance to a low resistance, the terminal voltage of the resistance change element changes abruptly as the resistance value changes. Due to the rapid voltage change, the amount of parasitic charge stored in the parasitic capacitance element related to the terminal of the variable resistance element flows instantaneously in the variable resistance element, making it difficult to accurately control the maximum current value. For example, the parasitic capacitance element and the parasitic charge amount are associated with a data bus and a bit line between the resistance change element and a current control element (write amplifier) that controls current supply to the resistance change element, respectively. Even if the amount of current supplied by the current control element is controlled in response to a sudden change in the resistance value of the resistance change element, the amount of parasitic charge related to the parasitic capacitance element supplies current to the resistance change element. It is. This problem will be described in detail in the description of the embodiment.

  According to a first aspect of the present invention, a memory cell including a resistance change element that stores information as a resistance value, connected in series, and a transistor that accesses the resistance change element, and one end of the memory cell A bit line connected to the memory cell, a source line connected to the other end of the memory cell, a word line connected to the gate electrode of the transistor, and a word line driving circuit for supplying a voltage to the word line, When the resistance value of the variable resistance element is set from a high resistance to a low resistance, the word line driving circuit starts from the first voltage that makes the transistor non-conductive, the first voltage, and the A voltage between a second voltage that renders the transistor conductive with a first impedance, and the transistor is made conductive with a second impedance that is higher than the first impedance. After the transition to the third voltage, the resistance value of the variable resistance element is changed to the first resistance value in a stage between the high resistance and the low resistance, and the transition to the third voltage is made. There is provided a semiconductor device in which the word line is changed from the third voltage to the second voltage after a predetermined time to set the resistance value of the variable resistance element to the low resistance.

  According to a second aspect of the present invention, there are provided a plurality of memory cells provided in a matrix corresponding to the intersections of a plurality of bit lines and a plurality of word lines, each memory cell corresponding to one end. A resistance change element that is connected to the bit line and that can be written in a high resistance state and a low resistance state by an applied current, and the word line and source corresponding to the other end of the resistance change element A transistor connected to a line and controlled to be conductive / non-conductive between the other end of the variable resistance element and the source line by a voltage applied to the corresponding word line; When the bit line and the word line are selected and the resistance value of the corresponding variable resistance element is written from high resistance to low resistance, the selected bit line is connected to a current source and the selected word line is selected. The line is transitioned from the first voltage at the non-selection level to a third voltage that is an intermediate voltage between the first voltage and the second voltage at the selection level, and the resistance value of the corresponding variable resistance element is increased to the high voltage. A first control for changing the resistance value to an intermediate resistance value between the resistance and the low resistance; and a transition of the selected word line from the third voltage to the second voltage, and a resistance value of the corresponding resistance change element. The second control for setting the resistance to the low resistance, the selected word line is returned to the first voltage, the selected bit line is disconnected from the current source, and the writing to the corresponding variable resistance element is terminated. And a third method for controlling the semiconductor device.

  According to a third aspect of the present invention, in a memory system comprising: a memory unit; and a control unit that controls the operation of the memory unit and performs information processing using information stored in the memory unit. A memory cell including a resistance change element that stores information in a resistance value, connected in series with each other, and a transistor that accesses the resistance change element; a bit line connected to one end of the memory cell; A source line connected to the other end of the memory cell, a word line connected to the gate electrode of the transistor, and a word line driving circuit for supplying a voltage to the word line, the word line driving circuit comprising the resistor When the resistance value of the change element is set from a high resistance to a low resistance, the word line is changed from the first voltage that makes the transistor non-conductive to the first voltage and the transistor. Transition to a third voltage that is between a second voltage that causes the transistor to conduct at a first impedance and that causes the transistor to conduct at a second impedance that is higher than the first impedance; After a predetermined time after changing the resistance value of the variable resistance element to the first resistance value in the stage between the high resistance and the low resistance and making the transition to the third voltage, the word line is connected to the third resistance value. A memory system is provided in which the resistance value of the variable resistance element is set to the low resistance by making a transition from the first voltage to the second voltage.

  According to each aspect of the present invention, when the resistance change element is transitioned from a high resistance state to a low resistance state, a sudden terminal voltage fluctuation of the resistance change element is prevented, and the maximum current value is accurately controlled. be able to.

1 is a circuit block diagram around a memory cell array of a semiconductor device according to a first embodiment of the present invention; 1 is a block diagram of an entire semiconductor device according to a first embodiment. FIG. 6 is a waveform diagram of a write operation according to the first embodiment. 2A is a block diagram showing an internal configuration of a memory cell, FIG. 2B is a block diagram showing a further internal structure of the resistance change element, and FIG. 2C is an IV characteristic diagram of the resistance change element. . 6 is a circuit block diagram around a memory cell array in a resistance change memory according to a comparative example 1; FIG. 6 is a waveform diagram of a write operation by the resistance changeable memory of Comparative Example 1. FIG. 6 is a diagram illustrating a problem in Comparative Example 1. 6 is a circuit block diagram around a memory cell array in a resistance change memory according to a comparative example 2; FIG. FIG. 11 is a waveform diagram of a write operation by the resistance change memory of Comparative Example 2. 6 is a diagram illustrating a problem in Comparative Example 2. It is drawing explaining the effect by 1st Embodiment. It is an operation | movement waveform diagram of the semiconductor device by 2nd Embodiment. FIG. 6 is a circuit block diagram around a memory cell array of a semiconductor device according to a third embodiment. FIG. 10 is a circuit block diagram around a memory cell array of a semiconductor device according to a fourth embodiment. FIG. 10 is a circuit block diagram around a memory cell array of a semiconductor device according to a fifth embodiment. (A) Arrangement according to the sixth embodiment and (b) Arrangement according to the seventh embodiment for the entire memory array. FIG. 20 is a circuit block diagram of a word line decoder and driver according to an eighth embodiment. FIG. 20 is a circuit block diagram of a word line decoder and driver according to a ninth embodiment. It is an IV characteristic diagram of the semiconductor device according to the tenth embodiment. It is a circuit block diagram around the memory cell array of the semiconductor device according to the tenth embodiment. It is a write-in operation | movement waveform diagram by 10th Embodiment. It is drawing explaining the effect by 10th Embodiment. It is a circuit block diagram around a memory cell array of a semiconductor device according to an eleventh embodiment. FIG. 30 is a circuit block diagram around a memory cell array of a semiconductor device according to a twelfth embodiment. FIG. 29 is a circuit block diagram around a memory cell array of a semiconductor device according to a thirteenth embodiment. It is a block diagram of the memory system by 14th Embodiment.

  Before describing each embodiment of the present invention in detail, an outline of the embodiment will be described. It should be noted that the drawings and reference numerals attached to the description of the outline are merely examples for facilitating understanding, and are not intended to be limited to the illustrated embodiments.

  As shown in FIG. 1, an example of the semiconductor device according to an embodiment of the present invention is a resistance change in which a resistance value can be written in a high resistance state and a low resistance state by a current connected to the bit line and flowing. A memory cell (40) having an element (41) and a transistor (42) connected in series with the variable resistance element and controlled in conduction / non-conduction by a voltage applied to a corresponding word line is provided. As shown in an example of RCELL in FIG. 3, when the resistance value of the corresponding variable resistance element is written from the high resistance (RRST) to the low resistance (RSET), the word line (SWL) to be selected is not connected to the transistor (42). A transition is made from the first voltage (VSS) at the selected level to the third voltage (VWL), which is an intermediate voltage between the first voltage and the second voltage (VPP) at the transistor (42). The resistance value of the variable resistance element is changed to an intermediate resistance value between the high resistance and the low resistance (see the resistance value at t5 in FIG. 3). Thereafter, the selected word line is transited from the third voltage to the second voltage (VPP) (from t5 to t6 in FIG. 3), and the resistance value of the corresponding variable resistance element is set to low resistance (RSET). The second voltage causes transistor (42) to conduct with a first impedance. The third voltage causes the transistor (42) to conduct with a second impedance that is higher than the first impedance. It should be noted that the intermediate voltage (intermediate level) is a voltage level of the word line (SWL) as long as the transistor (42) is turned on, and does not indicate a voltage that is ½ of the power supply VPP and the power supply VSS. is necessary. It should be noted that the resistance value at the intermediate stage does not show a resistance value that is 1/2 of the high resistance (RRST) and the low resistance (RSET) as well.

  Since the voltage of the selected word line SWL is set to the third voltage at the intermediate level and the resistance value of the variable resistance element is temporarily shifted to the intermediate resistance value, the resistance value of the variable resistance element is suddenly decreased. The potential of the selected bit line is prevented from changing. Charges instantaneously flow from the parasitic capacitance associated with the selected bit line to the resistance change element, and the resistance value of the resistance change element transitions to a resistance value lower than the assumed resistance value. Can be prevented.

  The description of the outline is finished above, and each embodiment will be described in more detail with reference to the drawings.

[First Embodiment]
(Configuration of the first embodiment)
FIG. 2 is a block diagram of the entire semiconductor device according to the first embodiment. The semiconductor device 10 of FIG. 2 is a semiconductor device including a large-capacity read / write memory array 11 having an 8-bank configuration. In FIG. 2, an X decoder (row decoder) 14 decodes a row address and drives a selected word line (not shown). The sense amplifier 12 determines the current or potential of a bit line (not shown) of the memory array 11 during a read operation, and outputs it as data to the outside. The column decoder 13 decodes the column address, turns on the selected Y switch (not shown), selects a bit line, and connects it to the IO line (not shown). The command decoder 19 receives a predetermined address signal and a control signal as a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE, and decodes the command (note that The signal name / indicates that the signal becomes active when it becomes low level). The command control circuit 20 receives an output signal from the command decoder 19 and outputs a control signal necessary for executing each command to each part in the semiconductor device 10. In particular, during a write operation, control signals such as SLSET, FSTPB, and SSTPB are output to the X decoder 14. The column address buffer and burst counter 17 generates an address corresponding to the burst length from the input column address under the control of the command control circuit 20 and supplies it to the column decoder 13. The mode register 15 inputs an address signal and bank selection signals BA0, BA1, and BA2 (select one of eight banks), and outputs a control signal to the command control circuit 20. The row address buffer 16 receives the input row address and supplies it to the X decoder 14.

  The clock generator 22 receives complementary external clocks CK and / CK supplied to the semiconductor device 10 from the outside. When the clock enable signal CKE is at a high level, the clock generator 22 outputs an internal clock to each part in the semiconductor device. When CKE goes low, the supply of the clock is stopped thereafter.

  The data control circuit 18 inputs and outputs write data and read data. When outputting read data, the data input / output circuit 21 converts the data read in parallel from the data control circuit into serial data in synchronization with the clock signal supplied from the DLL circuit and outputs the data from the data input / output terminal DQ. At the time of writing, data input in series from the data input / output terminal DQ is converted into parallel data and sent to the data control circuit 18.

  FIG. 1 is a circuit block diagram showing a partial region of one bank of the memory array 11 out of the eight banks of the memory array 11. FIG. 1 shows one memory cell array 30 (MAT) and peripheral circuits related to the memory cell array 30 among a plurality of memory cell arrays 30 (MAT) arranged in a matrix in the memory array 11. In FIG. 1, the address decoder 58 is a circuit outside the memory array 11 and is shown in FIG. The memory cell array 30 includes a plurality of bit lines 31, a plurality of word lines (sub-word lines) 32 wired in a direction intersecting the plurality of bit lines 31, and intersections of the plurality of bit lines 31 and the plurality of word lines 32. Corresponding to the plurality of memory cells 40 provided in a matrix. Each memory cell 40 has one end connected to the bit line 31 corresponding to the corresponding bit line 31, one source / drain connected to the other end of the resistance changing element 41, and the gate connected to the corresponding word line 32. A transistor 42 is provided. The transistor 42 is a transistor that becomes a cell transistor, and the other of the source and drain is connected to the source line 33. In addition, the transistor 42 is an NMOS transistor to give a preferable example. The source line 33 is connected in common to the transistors of the memory cells in the memory cell array 30. Since the source line is common to the transistors of each memory cell, the source line is not necessarily in the form shown in the figure, and may be arranged in a planar shape or a mesh shape in the memory cell array 30. In particular, when a vertical transistor (a transistor in which a channel is generated in the vertical direction) is used as the transistor 42, the source line may be arranged in a planar shape by an n + diffusion layer or the like.

  The sub word driver 51 drives the word line selected based on the address signal supplied from the address decoder 58 to a high level (VPP; second voltage). The unselected word line maintains the low level (VSS; first voltage). A word line power supply circuit unit 52 for supplying a voltage when a word line is selected to the sub word driver 51 is provided. The word line power supply circuit unit 52 includes a first word line power supply circuit 53, a second word line power supply circuit 54, and a third word line power supply circuit 55. The first word line power supply circuit 53 is used at resetting and reading. The second word line power supply circuit 54 and the third word line power supply circuit 55 are used at the time of setting.

  The first word line power supply circuit 53 includes a PMOS transistor having a source connected to the power supply VPP, a gate connected to the control signal SLSEL, and a drain connected to the high-level power supply terminal of the sub word driver 51, and the control signal SLSEL is active (low level). The power supply VPP is supplied as the high-level power supply of the sub word driver 51.

  The second word line power supply circuit 54 includes a PMOS transistor having a source connected to the power supply VPP, a gate connected to the control signal SSTPB, and a drain connected to the high-level power supply terminal of the sub word driver 51, and the control signal SSTPB is active (low level). Then, the power supply VPP is supplied as the power supply for the sub word driver 51. Note that the PMOS transistor of the second word line power supply circuit 54 has a channel size W smaller than that of the first word line power supply circuit 53. Accordingly, the on-resistance when the second word line power supply circuit 54 becomes conductive is higher than the on-resistance when the first word line power supply circuit 53 becomes conductive.

  The third word line power supply circuit 55 includes a PMOS transistor having a source connected to the power supply VWL (third voltage), a gate connected to the control signal FSTPB, and a drain connected to the high-level power supply terminal of the sub word driver 51, and the control signal FSTPB. Becomes conductive (low level), and the power supply VWL is supplied as the high-level power supply of the sub word driver 51. The power supply VWL is a power supply having a voltage level lower than that of the power supply VPP and outputting an intermediate level between the high-level power supply VPP and the low-level power supply VSS of the word line.

  The source line driver 36 is connected to the VRST as a positive power supply, and receives the control signal SLSEL to drive the source line. When the control signal SLSEL is high level, the source line 33 is driven to the VSS level (fifth voltage), and when the control signal SLSEL is low level, the source line 33 is driven to the VRST level (seventh voltage). .

  The bit line selection circuit 70 is provided with bit line selection switches 72 and 74 that connect each bit line 31 to the common bit line 75 and bit line selection switches 71 and 73 that connect each bit line 31 to the source line 33. Yes. As a signal for controlling on / off of the bit line selection switches 71 and 72, BLST and its inverted signal BLSTB are connected to the bit line selection switches 71 and 72, and when the control signal BLST is at high level, the corresponding bit line 31 Are connected to the common bit line 75, and when the control signal BLST is at low level, the corresponding bit line 31 is connected to the source line 33. The control signal BLST is connected to a different signal for each bit line selection switch corresponding to each bit line, and among the plurality of bit lines 31, only one selected bit line 31 is the common bit line 75. The remaining bit lines 31 are connected to the source line 33.

  The bit line selection circuit 70 is provided with a source line common bit line connection switch 76 for connecting the output of the source line driver 36 to the common bit line 75. The source line common bit line connection switch 76 is controlled to be turned on / off by a control signal SBLC and its inverted signal SBLCB. When the control signal SBLC is at a high level (the inverted signal SBLCB is at a low level), the source line 33 and the common bit line 75 are connected. Are connected via a source line common bit line connection switch 76.

  The write amplifier circuit 60 includes a SET driver 61 and a RESET selector 67. The SET driver 61 includes a constant current source transistor 62 serving as a current source when the selected variable resistance element 41 is written from a high resistance to a low resistance, and a switch transistor 64 that controls on / off of a current flowing through the variable resistance element 41. Is provided. The constant current source transistor 62 and the switch transistor 64 are both PMOS transistors. The source of the constant current source transistor 62 is connected to the positive power supply VSET, and the current control signal VSETREF is connected to the gate. The source of the switch transistor 64 is connected to the drain of the constant current source transistor 62, the drain of the switch transistor 64 is connected to the common bit line 75, and the gate is connected to the selection signal SETSELB.

  The SET driver 61 is adjusted so that the maximum current at the time of SET writing becomes a constant current value ICOMP by the current flowing through the constant current source transistor 62, and the resistance change element in the RSET (low resistance) state after performing the SET writing The resistance value 41 is kept constant.

  The RESET selector 67 includes a switch transistor 68 that is an NMOS transistor having a source connected to the reference power supply VSS (sixth voltage), a drain connected to the common bit line 75, and a gate connected to the control signal RSTSEL.

  At the time of SET writing, writing is performed by passing a current from the write amplifier circuit 60 to the source line 33 via the bit line 31 and the memory cell 40. Conversely, at the time of RESET writing, the memory cell 40 and the bit line 31 from the source line 33 are reversed. Is written by passing a current through the reset selector 67 of the write amplifier circuit.

  The global bit line selection switch 83 is a switch for connecting the common bit line 75 and the global bit line (GBL). READSW and its inverted signal READSWB are connected as a signal for controlling conduction / non-conduction of the global bit line selection switch 83. The global bit line selection switch 83 connects the common bit line 75 and the global bit line (GBL) during a read operation, and is closed during a write operation. In FIG. 1, the global bit line selection switch 83 has a CMOS transmission gate configuration, but any other configuration can be used as long as it is a switch that controls conduction / non-conduction between the common bit line 75 and the global bit line. Good. A sense amplifier (not shown) is connected to the tip of the global bit line 81. The write amplifier circuit 60, the global bit line selection switch 83, and the bit line selection circuit 70 are included in the bit line control circuit. The source line driver 36 is included in the source line control circuit.

(Operation of the first embodiment)
FIG. 3 is a waveform diagram of a write operation according to the first embodiment. The operation at the time of writing will be described with reference to FIG. 3 in addition to FIG.

  In FIG. 3, SET writing is performed in the first half, and RESET writing is performed in the second half. In FIG. 3, it is assumed that the initial state is a standby state and no command is being executed. In this state, since the bit line selection signal BLST is at a low level, each bit line 31 is disconnected from the common bit line 75 and connected to the source line 33. Since the source line control signal SLSEL is at a high level, each source line 33 and each bit line 31 are set to a low level (VSS level). The control signals SLSEL, SSTPB, and FSTPB of the word line power supply circuit unit 52 are all at a high level, and each (sub) word line 32 is fixed at a low level (VSS level). The switch signal SETSELB of the write amplifier circuit is at a high level and the RSTSEL is at a low level. The SET driver 61 and the RESET selector 67 of the write amplifier circuit 60 are disconnected from the common bit line 75, and the write amplifier circuit 60 and the common bit line 75 are disconnected. It is set so that no current flows between them. Further, the control signal SBLC is at the low level, the common bit line 75 is connected to the source line 33, and the common bit line 75 is also fixed at the low level in the same manner as the source line 33.

  Accordingly, in the initial state, no current flows through any memory cell 40, so the voltage VDEV between the terminals of each resistance change element 41 is 0 V, and the memory cell current ICELL is 0. The resistance value of the resistance change element 41 of the memory cell to be written is assumed to be RRST, that is, the high resistance state in the initial state.

  In this state, a PSET command is input from the outside in synchronization with the system clock CLK at timing t0. The PSET command is a SET write command that sets the resistance of a selected memory cell to a low resistance state. At this time, a bank and a column address are also input at the same time. It is assumed that the row address has already been input. When the PSET command is input, the semiconductor device 10 cancels the standby state and moves to execution of SET writing.

  At timing t1, the bit line selection signal BLST of the selected bit line 31 is set to a high level, and the selected bit line 31 is disconnected from the source line 33 and connected to the common bit line 75.

  At timing t2, the control signal FSTPB for activating the third word power supply circuit 55 is set to the low level, and the sub-word driver 51 is supplied with VWL, which is an intermediate level voltage between the low level voltage VSS and the high level voltage VPP, as the power supply. To do. In response, the sub word driver 51 raises the selected word line from the low level VSS to the intermediate level voltage VWL.

  At timing t3, the control signal SBLC falls to the low level, and the common bit line 75 is disconnected from the source line 33. Further, the switch control signal SETSELB of the SET driver 61 of the write amplifier circuit 60 is lowered to a low level, and a current is supplied from the constant current source transistor 62 of the SET driver 61 to the common bit line 75. At this time, since the bit line 31 already selected by the bit line selection circuit 70 is connected to the common bit line 75, a current flows to the source line 33 through the selected memory cell 40. At this time, since the resistance change element 41 of the selected memory cell 40 is in the RRST (high resistance) state, the voltage VDEV between the terminals of the selected resistance change element becomes a large value, and the voltage of the selected bit line is also the first voltage. Rises to a voltage of 4. In this state, the constant current source transistor 62 of the SET driver 61 operates in the non-saturation region, and only a small current flows through the selected memory cell 40. The resistance value of the selected resistance change element 41 is RRST. The (high resistance) state is maintained.

  When the time for applying a large voltage VDEV between the terminals of the selected variable resistance element 41 at timing t4 continues for a certain time TSETW, the resistance value of the variable resistance element 41 starts to change to a low resistance. The time TSETW from when the voltage VDEV is applied between the terminals of the resistance change element 41 to when the resistance value starts changing to a low resistance is a time depending on the characteristics of the device. The length of TSETW may be instantaneous or may require a certain time as shown in FIG.

  When the resistance value of the resistance change element 41 starts to change to a low resistance at timing t4, the voltage of the selected bit line also decreases accordingly. The current ICELL flowing from the selected bit line to the selected cell also increases. However, at this stage, since the intermediate voltage VWL is applied to the gate electrode of the cell transistor 42, the on-resistance of the cell transistor 42 is in a relatively high state (second impedance). Therefore, when the current ICELL flowing through the selected cell increases, the potential difference between the source and drain of the cell transistor increases, so that the resistance value of the resistance change element changes to a low value (first resistance value), and the resistance change element terminal Even if the intermediate voltage VDEV is lowered, the voltage drop of the selected bit line is not so great. The maximum value of the write current at this time is limited to IWCOMP. IWCOMP adjusts the VWL potential so that the current value is sufficiently lower than the current limit value (ICOMP) by the SET driver 61. At this time, attention should be paid so that the maximum value of the variation of IWCOMP caused by the variation of the characteristics of the cell transistor is smaller than ICOMP.

  At timing t5, the control signal FSTPB of the word line power supply circuit unit 52 is set to a high level, the third word line power supply circuit 55 is controlled to be non-conductive, the control signal SSTPB is set to a low level, and the second word The line power supply circuit 54 is controlled to be in a conductive state. Then, the power supply voltage supplied from the word line power supply circuit unit 52 to the sub word driver 51 starts to rise from the intermediate voltage level VWL to the voltage VPP. Accordingly, the voltage of the selected (sub) word line SWL starts to rise from the intermediate voltage level VWL to the voltage VPP. This increase speed (slew rate) is set to a low speed (first slew rate = small) to suppress the transient current, and can be performed by adjusting the transistor size W of the second word line power supply circuit 54, for example. As the voltage of the selected (sub) word line SWL gradually increases from VWL to voltage VPP, the on-resistance of the cell transistor 42 gradually decreases. That is, the impedance of the cell transistor 42 shifts to the first impedance that is lower than the second impedance. As the on-resistance of the cell transistor 42 decreases, the selected cell current ICELL gradually increases. Furthermore, as the selected cell current ICELL increases, the resistance value RCELL of the resistance change element 41 gradually decreases. However, when reaching a constant current value ICOMP determined by the constant current source transistor 62 of the write amplifier circuit 60, the constant current source transistor 62 is saturated and the selected cell current ICELL does not increase any more. The resistance value of the variable resistance element 41 in the SET (low resistance) state is determined to be a constant value by the value of the maximum current value ICOMP.

  Note that the time from the timing t3 to the timing t5 is set to an optimal time in consideration of variations in the time TSETW depending on device characteristics.

  At timing t6, the switch control signal SETSELB of the SET driver 61 is raised to a high level, and the SET driver 61 is disconnected from the common bit line 75. Further, the control signal SBLC is raised to a high level, and the common bit line 75 is connected to the source line 33. Then, the selected cell current ICELL does not flow, the voltage VDEV between the terminals of the resistance change element 41 becomes zero, and the voltage of the selected bit line also decreases to the VSS level.

  At timing t7, the control signal SSTPB of the word line power supply circuit unit 52 is set to a high level, and the second word line power supply circuit 54 is controlled to be non-conductive. Further, the address decoder 58 lowers the voltage of the sub word line SWL to the VSS level.

  At timing t8, the bit line selection signal BLST of the selected bit line 31 falls to the low level, the selected bit line 31 is disconnected from the common bit line 75, connected to the source line 33, and the selected memory cell by the PSET command input A series of SET write processing for setting the resistance of the current to the low resistance state is completed.

  Next, at timing t10, a PRST command is input from the outside as a new command in synchronization with the system clock CLK. The PRST command is a RESET write command for setting the resistance of the selected memory cell from the low resistance state to the high resistance state. At this time, a bank and a column address are also input at the same time.

  At timing t11, the bit line selection signal BLST of the selected bit line 31 is set to a high level, and the selected bit line 31 is disconnected from the source line 33 and connected to the common bit line 75.

  At timing t12, the control signal SLSET is lowered to the low level, and the source line voltage is raised to the high level voltage VRST. This is because in RESET writing, it is necessary to pass a current from the source line 33 to the write amplifier circuit 60 contrary to SET writing. Since the non-selected bit line is also connected to the source line 33, it rises to the same potential as the source line 33. Since the control signal SBLC is maintained at a high level, the source line 33 and the common bit line 75 are connected by the source line common bit line connection switch 76 and are connected to the common bit line 75 and the common bit line 75. Similarly, the selected bit line rises to the same potential as the source line 33. Further, when the control signal SLSET falls to the low level, the first word power supply circuit 53 of the word line power supply circuit section 52 is activated, and the high-level voltage VPP is supplied to the sub word driver 51 as a power supply.

  At timing t13, the selected sub word line SWL rises from the low level voltage VSS to the VPP level by a signal from the address decoder 58. Since the first word line power supply circuit 53 uses a transistor having a large channel width W, the selected sub word line SWL rises quickly. That is, the slew rate (second slew rate) of the selected sub word line SWL at the time of reset is larger than the slew rate (first slew rate) of the selected sub word line SWL at the time of setting. The second slew rate suppresses the time increase of the reset program cycle that controls the source line and all the bit lines.

  At timing t14, the control signal SBLC falls to the low level, and the common bit line 75 is disconnected from the source line 33. Further, the control signal RSTSEL is raised to a high level, and the RESET selector 67 of the write amplifier circuit 60 causes the common bit line 75 to fall to a low level (VSS level). Then, a constant current flows from the source line 33 to the RESET selector 67 of the write amplifier circuit 60 via the resistance change element 41 of the selected memory cell 40 and the selected bit line. Further, a negative potential VDEV is generated between the terminals of the resistance change element 41 when the terminal on the side connected to the source or drain of the selection transistor 42 is used as a reference.

  By causing a constant current to flow through the selected variable resistance element 41, at a timing t15 after a certain time determined by the device characteristics from the timing t14, the selected resistance change element 41 changes from the RSET (low resistance) state to the RRST (low resistance) state. Start transition to high resistance state. As the resistance value of the selected variable resistance element increases, the absolute value of the current ICELL flowing in the reverse direction of the selected cell decreases. As ICELL decreases, the potential of the selected bit line gradually approaches VSS.

  At timing t16, the control signal RSTSEL falls to the low level. When the control signal RSTSEL falls to the low level, the RESET selector 67 of the write amplifier circuit 60 disconnects the common bit line 75 from the write amplifier circuit 60. Further, the control signal SBLC is raised to a high level, and the common bit line 75 is connected to the source line 33. Then, the current ICELL does not flow to the selected cell, and the voltage of the selected bit line becomes a high level substantially the same as that of the source line.

  At timing t17, the selected sub word line SWL falls to a low level by a signal from the address decoder 58.

  At timing t18, the control signal SLSET is raised to high level, and the voltage of the source line is returned to low level. When the voltage of the source line becomes low level, the voltage of the non-selected bit line also becomes low level.

  At timing t19, the bit line selection signal BLST of the selected bit line 31 is lowered to the low level, the selected bit line 31 is disconnected from the common bit line 75, connected to the source line 33, and the selected memory cell by the PRST command input A series of RESET write processing for setting the resistance to the high resistance state is completed.

  As described above, in the first embodiment, the voltage of the selected word line is gradually changed from the non-selected voltage level in the SET write in which the variable resistance element is changed from the high resistance state (RRST) to the low resistance state (RSET). By changing to the selected voltage level and writing while the voltage of the selected word line transitions from the non-selected level to the selected level, a sudden voltage fluctuation of the selected bit line is prevented. In order to explain this technical significance in more detail, a comparative example will be described here.

(Comparative Example 1)
FIG. 5 is a circuit block diagram around the memory cell array in the resistance change memory according to the first comparative example. In FIG. 5, parts that are substantially the same as those in FIG. 1 of the first embodiment are given the same reference numerals, and redundant descriptions are omitted. In the comparative example 1 shown in FIG. 5, the word line power supply circuit unit 52 shown in FIG. 1 is not provided, and when the sub word driver 151 is activated, power is always supplied from the power supply VPP. About another structure, it is as substantially the same as FIG. 1 of 1st Embodiment.

  FIG. 6 is a waveform diagram of a write operation by the resistance change memory of Comparative Example 1. Only a portion having a waveform different from that of the first embodiment of FIG. 3 will be described. Since the second half of RESET writing is the same as the operation waveform diagram of the first embodiment shown in FIG.

  The SET write operation in FIG. 6 will be described with respect to portions different from the operation waveforms of the first embodiment in FIG. Up to timing t1, it is the same as FIG. At the timing t2, the selected sub word line is raised to the voltage VPP based on the signal from the address decoder 58. Therefore, the on-resistance of the cell transistor 42 is set to a sufficiently low value.

  At timing t3, the switch control signal SETSELB is lowered to a low level, and a current ICELL is supplied from the constant current source transistor 62 of the SET driver 61 to the selected cell. At this stage, since the variable resistance element is in the RRST (high resistance) state, the selected cell current ICELL is limited.

  At the time of SET writing, the resistance change of the resistance change element is assumed to occur at timing t4 after the lapse of time TSETW from timing t3 when the voltage is applied to the memory cell. Since the voltage-dividing relationship between the impedance of the resistance change element and the write circuit system is greatly changed by the resistance change, the bit line potential is greatly reduced before and after that. The common bit line and the selected bit line have a large parasitic capacitance due to a diffusion layer capacitance of a transistor connected to each bit line, a gate capacitance of a transistor that is turned on, a wiring capacitance, and the like. Therefore, when the resistance change rate is fast, a sudden change in the voltage division relationship causes charge discharge from the parasitic capacitance, and the selected memory cell has a transient current larger than ICOMP indicated by the maximum value (IMAX) (instantaneously). Will flow). At this time, since the SET driver 61 is disposed on the higher potential side than the common bit line 75, this transient current cannot be suppressed.

  Therefore, in a circuit like the comparative example 1, a current larger than the maximum current (ICOMP) set by the SET driver is applied to the selected memory cell due to a transient current. Since RSET of the resistance change element strongly depends on the maximum current applied at the time of set writing, RSET is determined by the transient current and cannot be set to an arbitrary value. Further, when the wiring resistance value of the bit line is high, there is a difference in IMAX between the far end and the near end of the bit line, and a far end difference is caused in the cell characteristics.

  FIG. 7 shows the operating point of Comparative Example 1 as the IV characteristic of the variable resistance element (not actually sweeping the voltage, but shown as an image of the operating point). RSET (resistance value of low resistance) is determined by IMAX.

  Thus, there is a problem that the maximum current cannot be appropriately controlled by the ICOMP control by the write amplifier circuit alone.

(Comparative Example 2)
FIG. 8 is a circuit block diagram around the memory cell array in the resistance changeable memory according to the second comparative example. Portions that are substantially the same as those in the circuit block diagram of the first embodiment shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted.

  In Comparative Example 2, the maximum current ICOMP at the time of SET writing is adjusted by adjusting the gate voltage of the cell transistor. In Comparative Example 2, the write amplifier circuit 160 is not provided with the constant current source transistor 62 as shown in FIG. At the time of SET writing, the maximum current (ICOMP) at the time of writing is controlled by adjusting the capability of the cell transistor by the potential (VWL) of the selected sub word line SWL. Here, VWL is selected by the word line power supply circuit unit 152. The circuit of Comparative Example 2 shown in FIG. 8 is substantially the same as that of FIG. 1 except that the constant current source transistor 62 is not provided in the write amplifier circuit 160 and the circuit configuration of the word line power supply circuit unit 152 is different. The circuit configuration is the same as that of the first embodiment shown.

  FIG. 9 is a waveform diagram of a write operation by the resistance change memory according to the second comparative example. Since the cell transistor 42 always passes when the charges charged in the parasitic capacitances of the bit line 31 and the common bit line 75 are discharged, in Comparative Example 2, by limiting the capability of the cell transistor 42, an excessive current due to the discharge is generated. Can be suppressed.

  On the other hand, as described in Non-Patent Document 3 and Non-Patent Document 4, the amount of variation in VTH (gate threshold voltage) of a transistor depends on the channel area. For example, the standard deviation ΔVTH of the VTH fluctuation caused by the variation in the impurity concentration in the depletion layer is expressed by [Equation 1].

  In [Expression 1], A is a constant determined by a physical constant, L is a channel length, W is a channel width, and Tox is a gate insulating film thickness.

  In a memory cell array miniaturized to a processing size of several tens of nm, the channel area of a cell transistor is very small, and ΔVTH ranges from several tens of mV to several hundreds of mV. Further, Non-Patent Document 4 describes that not only the impurity concentration but also microfabrication, variation in gate insulating film thickness, and the influence of fluctuations in carrier mobility on transistor characteristics increase with miniaturization.

  Due to these factors, in the miniaturized memory cell, the on-current of the cell transistor varies greatly between the memory cells. Therefore, the maximum current value (ICOMP) of the memory cell is different for each memory cell as shown in ICELL in FIG. It varies greatly. This tendency appears more greatly because the sensitivity of the ID to VGS increases as the current is reduced.

  As a result, even when the method of Comparative Example 2 is used, the resistance value RSET in the low resistance state varies greatly due to variations in the characteristics of the cell transistors. FIG. 10 shows the operating point in Comparative Example 2 as the IV characteristic of the resistance change element (not actually sweeping the voltage, but shown as an image of the operating point). Due to the variation in ICOMP, the resistance value RSET in the low resistance state varies.

(Comparison between Comparative Example 1, Comparative Example 2 and the first embodiment)
FIG. 11 shows the operating point according to the first embodiment as the IV characteristic of the variable resistance element (not actually sweeping the voltage, but shown as an image of the operating point). By the two-stage word line potential control, the difference between ICOMP memory cells can be reduced, and the variation between RSET memory cells can be reduced.

  That is, in the period from the timing t3 to the timing t5 in FIG. 3, the first-stage SET writing is performed in which the maximum value of the SET current is limited to IWCOMP by the word line potential control (VWL). Thereafter, the potential of the word line is changed to VPP, and the second stage SET writing is performed by the maximum current ICOMP determined by the SET driver 61 of the write amplifier circuit 60.

  Since the two-step SET writing is performed, the maximum current exceeding ICOMP is prevented from flowing due to the transient current due to the rapid resistance change of the resistance change element as in Comparative Example 1 shown in FIG. In other words, the resistance value of the variable resistance element is changed to the intermediate resistance value between the high resistance and the low resistance by writing in the first stage. Therefore, it is possible to reduce the width of the change in resistance value due to the second writing. Therefore, it is possible to prevent a large transient current from flowing due to a rapid resistance change as in Comparative Example 1. This effect is obtained by controlling the second stage gate voltage so that the change in the gate voltage at the second stage becomes gentle, for example, by reducing the transistor size of the second word line power supply circuit section, etc. By further mitigating the change and mitigating the potential change of the bit line, the transient current can be further prevented.

  Further, the variation in the maximum value (IWCOMP) of the first stage SET current is the same as the variation in ICOMP in the comparative example 2 shown in FIG. However, in the first embodiment shown in FIG. 11, since the maximum value ICOMP of the second stage SET current is performed by the SET driver 61 of the write amplifier circuit 60, the accuracy depends on the current accuracy of the SET driver 61. It is possible to control the maximum current value ICOMP well.

(Measures against variations in TSETW)
As described above, TSETW in FIG. 3 is a time that depends on device characteristics and the like, and it is necessary to control the timing after timing t5 in consideration of the time variation of TSETW. Therefore, the following measures can be taken.

(1) Time adjustment using ROM or the like by search during test TSETW period is a test chip, or in some cells of the product chip, a test mode is used to perform a write test to the cell in various TSETW periods, A TSETW period is derived in which (in some cases, almost) all cells change resistance and are minimized. The product chip is provided with a circuit for adjusting the TSETW period by switching a ROM switch such as a metal fuse or a laser fuse using a delay circuit or the like, and the derived optimum values are set in them. When a cell that cannot be rewritten correctly due to a short TSETW period is generated in the product chip, the cell is replaced with another cell (redundant memory cell) by the relief circuit.

(2) Time adjustment using feedback by reference cell A cell (reference cell) for determining TSETW is separately provided in the chip, and these are normally set in a reset state. During the write operation to this cell, the write operation is simultaneously performed on the reference cell (one or more). The reference cell is monitored for the potential of the bit line, and immediately after detecting a decrease in the potential of the bit line due to the resistance change of the reference cell, or after a certain period of time after the detection, a timing for shifting to the next operation (for example, , Timing t5 in FIG. When a plurality of reference cells are used, the end timing of the TSETW period is set after detecting potential changes in all the reference cells. In addition to the method of detecting the potential of the bit line, there is a method of monitoring a change in current.

[Second Embodiment]
In the first embodiment, as shown in FIG. 3, in SET write, after the selected sub-word line SWL is raised at timing t2, the switch control signal SETSELB of the SET driver 61 is lowered to low level at timing t3, and the SET driver 61 Connected to the common bit line. The timing of the fall of SETSELB and the timing of the rise of (selected) SWL, that is, the timing of charging the selected bit line LBL and the selected sub-word line SWL may be interchanged. For example, as shown in FIG. 12, the selected bit line LBL may be charged first at timing t3, and then the selected sub-word line SWL may be charged at timing t2. Although not shown, when SET writing is performed on a cell in the SET (low resistance) state, the method of charging the selected bit line LBL first does not use the two-stage start-up of the selected sub word line SWL. There is a concern that a transient current may flow through the selected cell due to the rise of the cell and change the resistance value of the selected cell further to the low resistance side. However, in the two-stage start-up described in the first embodiment, the cell is in the initial stage. Since the on-resistance of the transistor is high, suppression of this transient current can be expected. Note that the command control circuit 20 shown in FIG. 2 can perform timing control of the selected bit line LBL and the selected sub-word line SWL during SET writing. Therefore, the circuit configuration of the second embodiment is different only in the internal control timing of the command control circuit 20, and for the other configurations, the circuit configuration of the first embodiment shown in FIG. 1 is used as it is. Can do.

[Third Embodiment]
FIG. 13 is a circuit block diagram around the memory cell array of the semiconductor device according to the third embodiment. The circuit block diagram shown in FIG. 13 is the same as FIG. 1 except that the circuit block diagram according to the first embodiment shown in FIG. 1 and the configuration of the write amplifier circuit 60a and the third word line power supply circuit 55a are different from FIG. It is.

  In the first embodiment shown in FIG. 1, the constant current source transistor 62 serving as a set driver is a constant current source whose drain current depends only on the gate voltage (VGS) when operating in the saturation region. When the set current value is large or the VDS is small, the operation may be performed in a non-saturated region. In the non-saturated region, the drain current depends on VDS in addition to VGS. Since VDS varies depending on the resistance value of the resistance change element 41, the constant current source transistor 62 is unlikely to serve as a constant current source in the non-saturation region.

  Therefore, as shown in FIG. 13, a clamp transistor 63 for making VDS of the constant current source transistor 62 constant in series with the constant power source transistor 62 that is a P-type transistor is provided in the SET driver 61a. May be added. A constant voltage (VSDRREF) is applied to the gate electrode of the clamp transistor 63, and the drain potential of the constant current source transistor 62 is approximately the sum of the constant voltage VSDRREF and the threshold value VT of the clamp transistor 63. As a result, the VDS of the constant current source transistor 62 becomes a constant value of approximately (VSET− (VSDRREF + VT)) regardless of the impedance of the load connected to the set driver 61a. Thereby, the SET driver 61a can be operated as a current source even at an operating point where the constant current source transistor 62 is in a non-saturated region.

  In the word line power supply circuit unit 52 shown in FIG. 1, power is supplied (potential selection) using a P-type transistor, but the present invention is not limited to this, and a selection is made using a CMOS switch or an N-type transistor. May be. In FIG. 13, only the third word line power supply circuit 55a uses a CMOS switch, but other power supply circuits may similarly use a CMOS switch or an N-type transistor.

[Fourth Embodiment]
FIG. 14 is a circuit block diagram around the memory cell array of the semiconductor device according to the fourth embodiment. FIG. 14 is the same as the first embodiment shown in FIG. 1 except that the circuit configuration of the write amplifier circuit 60b is different from the write amplifier circuit 60 of the first embodiment shown in FIG.

  The SET driver 61b of the write amplifier circuit 60b shown in FIG. 14 further adds a differential amplifier 65 to the SET triver 61a of the write amplifier circuit 60a of the third embodiment shown in FIG. By using the differential amplifier 65 for the SET driver 61b, the drain-source voltage VDS of the constant current source transistor 62 is controlled to a constant value. In this method, although the layout area and current consumption of the write amplifier circuit 60b increase, the drain voltage of the constant current source transistor 62 can be controlled to the same value as the constant voltage VSDRREF, and the maximum current ICOMP at the time of writing with high accuracy can be obtained. Can be controlled.

[Fifth Embodiment]
On the other hand, when the resistance change characteristic of the cell is relatively insensitive to the write current at the time of writing, the SET driver can be further simplified as compared with the first embodiment shown in FIG. In the write amplifier circuit 60c shown in FIG. 15, a constant current is generated only by adjusting the size of the channel width W of the switch transistor 64 which is a selection switch for the write pulse. In this case, since the constant voltage reference signal line VSETREF is not required, the power supply circuit can be reduced and the number of wirings in the memory array can be reduced. In addition, the layout area of the write amplifier can be reduced.

[Sixth Embodiment]
The sixth and seventh embodiments are embodiments of arrangement in the memory array 11 (see FIG. 2). FIG. 16A is an overall layout diagram in the memory array 11 according to the sixth embodiment. In FIG. 16A, the one-dot chain line indicates a layout of one MAT unit with one memory cell array 30 as the center. Inside the memory array 11, memory cell arrays 30 are arranged in a matrix form in MAT units. In FIG. 16A, in addition to the memory cell array 30, a sub word driver 51, a write amplifier circuit 60, and a bit line selection circuit 70 are arranged for each MAT. As a wiring penetrating each MAT, the global bit line (GBL) 81 and the main word line (MWL) 84 are wired in a crossing direction. The sense amplifier 12 is connected to the global bit line 81 and is shared by each memory cell array 30 connected to the same global bit line 81. Similarly, the main word line 84 is wired from the X decoder 14 and is shared by the memory cell arrays 30 arranged in the main word line 84 direction. In FIG. 16A, a write amplifier circuit 60 is provided for each memory cell array 30. For example, the write amplifier circuit 60 is composed of two memory cell arrays 30 adjacent in the direction in which the global bit line 81 extends. It may be a shared arrangement.

[Seventh Embodiment]
FIG. 16B is an overall layout diagram in the memory array 11 according to the seventh embodiment. In the seventh embodiment, the write amplifier circuit 60 is shared by a large number of MATs via the global bit line 81 in the same manner as the sense amplifier 12 without arranging the write amplifier circuit 60 in MAT units. That is, the SET driver 61 and the RESET selector 67 shown in FIG. 1 are arranged outside the global bit line selection switch 83 via the global bit line 81.

  The arrangement of the memory array is not limited to FIGS. 16A and 16B, and various arrangements are possible. For example, as in the write amplifier circuit 60 in FIG. 16A, the global bit line 81 and the sense amplifier 12 may be arranged corresponding to each MAT. Further, in the configuration in which the write amplifier circuit 60 is provided for each MAT as shown in FIG. 16A, the number of write amplifiers per MAT is 2, 4, 8 corresponding to the number of simultaneously written cells per MAT. A plurality may be provided.

[Eighth Embodiment]
In FIG. 1, the word line power supply circuit unit 52 is described as being arranged around each memory cell array (MAT) 30, but the word line power supply circuit unit 52 may be arranged in the X decoder 14 or the like. In the eighth and ninth embodiments, the word line power supply circuit unit 52 is arranged in the X decoder 14 and the word line power supply circuit unit 52 has a decoding function.

  FIG. 17 shows a circuit block diagram of the X decoder 14 and the sub word driver 51 according to the eighth embodiment. In the figure, LA <0> to LA <3> indicate row addresses, which are decoded by the address decoder 58 and provided to the selector 56 provided in the word line power supply circuit unit 52 bit by bit and the main word line driver 57. Entered. A non-inverted signal and an inverted signal of the FX line are connected to the sub-word driver 51 from the selector 56 of the word line power supply circuit unit 52. Further, from the main word line driver 57, the main word line (MWL (B)) is connected to the sub word driver 51. In the sub word driver 51, one sub word line SWL is selected based on these signals. In the eighth embodiment shown in FIG. 17, the word line power supply circuits 53 to 55 all have a CMOS switch configuration or a CMIS switch configuration.

[Ninth Embodiment]
FIG. 18 shows a circuit block diagram of the X decoder 14 and the sub word driver 51 according to the ninth embodiment. In the ninth embodiment, only the non-inverted signal of the FX line is connected to the sub word driver 51 from the selector 56 of the word line power supply circuit unit 52, and the main word line (MWL ( B)) and the main word line (MWL (T)) of the non-inversion level are connected to the sub word driver 51. In the sub word driver 51, one sub word line SWL is selected based on these signals.

[Tenth embodiment]
The tenth embodiment is an embodiment in which the RSET (low resistance) state is controlled to multiple values by controlling the value of the maximum current ICOMP when performing SET writing to the variable resistance element in multiple stages. FIG. 19 is an IV characteristic diagram of the variable resistance element in the semiconductor device according to the tenth embodiment. In SET write, after setting the resistance value in the intermediate stage between the RRST (high resistance) state and the RSET (low resistance) state in the first stage, the multi-value memory is set by setting the maximum write current ICOMP in multiple stages. Can be realized. In the tenth embodiment, in addition to the resistance value in the RRST (high resistance) state, the resistance value in the RSET (low resistance) state is controlled in three stages, thereby realizing a multilevel memory having four values.

  FIG. 20 is a circuit block diagram around the memory cell array of the semiconductor device according to the tenth embodiment. Portions that are substantially the same as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

  The circuit block diagram according to the tenth embodiment shown in FIG. 20 is the same as the circuit block diagram of the first embodiment shown in FIG. 1 except for the circuit configuration of the SET driver 61d of the write amplifier circuit 60d. The SET driver 61d includes three pairs of constant current source transistors 62-n (n is an integer from 1 to 3) and switch transistors 64-n. Different constant voltages VSETREF (01), VSETREF (10), VSETREF (11) are applied to the gates of the respective constant current source transistors 62-n, and the constant current values of the respective constant current source transistors 62-n are different from each other. It is set to be a value. In the tenth embodiment, the constant current source transistor 62-1 has the smallest setting current, the constant current source transistor 62-3 has the largest setting current, and the constant current source transistor 62-2 is set to an intermediate value thereof. . Also, different control signals SETSELB (01), SETSELB (10), and SETSELB (11) are connected to the gate of each switch transistor 64-n.

  FIG. 21 is a write operation waveform diagram according to the tenth embodiment. The write timing itself is the same as that of the first embodiment described with reference to FIG. Multi-level writing can be realized by writing multi-level to a reset cell using a PRST (program reset) command using a PRST (program reset) command. For example, when writing four-valued data of 00, 01, 10, and 11, it can be realized as follows.

  First, when writing any one of the three values 01, 10, and 11 by the PSET (program set) command, one of SETSELB (01), SETSELB (10), and SETSELB (11) is selected in FIG. (Low level).

  On the other hand, when 00 is written, writing is masked by setting all SETSELB signals to non-selection (HIGH), and the RESET state of the cell is held. As a result, the write operation corresponding to FIG. 19 can be performed.

  In addition, the selection or reading operation of quaternary data is performed, for example, by substituting the binary memory with the second digit as an address and the first digit as data.

  FIG. 22 is a diagram for explaining the effect of the tenth embodiment. In FIG. 22, the horizontal axis represents the element resistance value, and the vertical axis represents the number of elements (element variation). Further, the variation according to the tenth embodiment is indicated by a solid line, and a comparative example in which the two-step writing is not performed (the power supply of the sub-word driver 51 without the word line power supply circuit unit 52 in FIG. 20 is VPP as shown in FIG. The variation due to (fixed) is indicated by a broken line. Note that FIG. 22 shows the case of a quaternary storage cell. The determination threshold is a voltage that is a determination criterion for each data at the time of reading. In the writing method according to the comparative example, when any of the three values 01, 10, and 11 is written by SET (set) writing, a desired maximum writing current (ICOMP (01), ICOMP (10), ICOMP (11)) The transient current IMAX exceeding the current flows instantaneously, and the resistance value may become too low. In FIG. 22, in the comparative example, the case where the resistance value becomes too low due to the transient current IMAX is indicated by a broken line. However, according to the tenth embodiment, a sufficient read margin can be ensured until the resistance value can be written with high accuracy in the SET write.

[Eleventh embodiment]
In the embodiment of the multilevel memory, the tenth embodiment SET driver 61d shown in FIG. 20 can be variously modified. FIG. 23 is a circuit block diagram around the memory cell array of the semiconductor device according to the eleventh embodiment. In the SET driver 61e of the eleventh embodiment shown in FIG. 23, the current source transistors 62-1 to 62-3 in FIG. 20 are omitted, and the transistor size W of the switch transistors (driver selection transistors) 64a-1 to 64a-3 is omitted. By setting to a different value for each driver, the amount of current is controlled with a simpler configuration. In the case of the eleventh embodiment, the gate voltages of the switch transistors 64a-1 to 64a-3 take only two values of a high level and a low level, and at the time of selection, the corresponding SETSELB is at the low level of the GND (VSS) potential.

[Twelfth embodiment]
FIG. 24 is a circuit block diagram around the memory cell array of the semiconductor device according to the twelfth embodiment. In the twelfth embodiment, the constant current source transistor 62 and the switch transistor 64 are shared for each multivalued value. In the twelfth embodiment shown in FIG. 24, the voltage value given to the constant current source transistor 62 by the VSETREF selector 69 is selected and given from three types of voltage values. In the twelfth embodiment, when the VSETREF selector 69 is arranged outside the array and the VSETREF selector 69 is shared by a plurality of write amplifier circuits 60, the layout area of the write amplifier circuit 60 can be reduced.

  However, in the tenth embodiment whose operation waveform diagram is shown in FIG. 21, when a plurality of cells are simultaneously written, different values can be simultaneously written. In the twelfth embodiment, however, the VSETREF selector 69 Is arranged outside the array and shared by a plurality of write amplifier circuits 60, it is necessary to write each of the multi-values (values of 01, 10, 11) in a time division manner. Specifically, in the case of a quaternary memory, it is necessary to write at least 01, 10, and 11 in three separate timings. At this time, the presence / absence of writing at each timing (corresponding to data (or address)) can be determined according to the selection status under each timing of the SETSELB signal. That is, writing is performed in three times 01, 10, and 11, and when writing is performed on 01, 10, and 11, writing is performed on cells whose write data is 01, 10, and 11, respectively.

[Thirteenth embodiment]
FIG. 25 is a circuit block diagram around the memory cell array of the semiconductor device according to the thirteenth embodiment. The thirteenth embodiment is yet another embodiment in which a SET driver is shared in the case of realizing a multi-level memory. By providing a VSETREF (**) signal selection transistor (CMOS switch or CMIS switch) and a VSETREF charge P-type transistor corresponding to each data, the same timing chart as in the tenth embodiment shown in FIG. It can be operated. Since the transistor size of each switch may be small, the thirteenth embodiment is effective when the size of the SET driver transistor (switch transistor) 64 must be increased.

  In addition, it goes without saying that the multilevel memory according to the tenth to thirteenth embodiments can be implemented in combination with the embodiments shown in the second to ninth embodiments.

[Fourteenth embodiment]
FIG. 26 is a block diagram of a memory system according to the fourteenth embodiment. The memory system 90 of FIG. 26 connects the control unit 92 that controls the entire memory system 90, the memory unit 10a using the resistance change element according to the first to thirteenth embodiments, and the control unit 92 and the memory unit 10a. System bus 91. As shown in FIG. 26, the system bus 91 may be further provided with different types of semiconductor memories such as an I / O device 93, DRAM 94, SRAM 95, and ROM 96 as required.

  The control unit 92 can perform data processing based on a program or data stored in the memory unit 10a or other memory, and store the result in the memory unit 10a or other memory. In the memory system 90 of FIG. 26, the memory unit 10a and the control unit 92 may each be configured by one chip or a plurality of semiconductor chips, or the entire memory unit 10a and the control unit 92 may be formed on the same semiconductor substrate. It may be configured as a one-chip memory system to be formed.

  The technical idea of the present application can be applied to a semiconductor device related to a nonvolatile memory cell. Further, the circuit format in each circuit block disclosed in the drawings and other circuits for generating control signals are not limited to the circuit format disclosed in the embodiments.

  The technical idea of the semiconductor device of the present invention can be applied to various semiconductor devices. For example, a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and an ASP (Amplified Semiconductor). The present invention can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (System on a Chip), MCP (Multi Chip Package), and POP (Package on Package). The present invention can be applied to a semiconductor device having any of these product forms and package forms.

  The transistor may be a field effect transistor (FET). In addition to a MOS (Metal Oxide Semiconductor), an MIS (Metal-Insulator Semiconductor), a TFT (Thin Film Transistor), or the like may be used. it can. Furthermore, at least a part of the transistors may be bipolar transistors.

  In the present invention, the variable resistance element may be a variable resistance element based on any operating principle as long as the resistance value can be changed by passing a current through the resistance. For example, the resistance change element may be a resistance change element that changes phase between an amorphous state and a crystalline state by passing a current.

  Further, the NMOS transistor (N-type channel MOS transistor) is a representative example of the first conductivity type transistor, and the PMOS transistor (P-type channel MOS transistor) is a representative example of the second conductivity type transistor.

  Further preferred forms of the present invention are listed below.

[Form 1]
Multiple bit lines,
A plurality of word lines wired in a direction intersecting the plurality of bit lines;
A plurality of memory cells provided in a matrix corresponding to intersections of the plurality of bit lines and the plurality of word lines;
Source line,
A memory cell array having:
A word line driving circuit which is provided corresponding to the memory cell array and drives a selected word line among the plurality of word lines;
A semiconductor device comprising:
Each memory cell has
A resistance change element having one end connected to the corresponding bit line and capable of writing in a state where the resistance value is high resistance and low resistance by an applied current;
Conduction between the other end of the variable resistance element and the source line is connected to the word line and the source line corresponding to the other end of the variable resistance element, and is applied to the corresponding word line. A transistor whose non-conduction is controlled,
With
When the word line driving circuit selects the bit line and the word line and writes the resistance value of the corresponding resistance change element, the word line driving circuit selects the second voltage of the selected level from the first voltage of the non-selected level. The word line to be selected is selected so that the voltage profile that transitions to the voltage of the corresponding resistance change element becomes gentler when writing from the high resistance to the low resistance than when writing the resistance value of the corresponding variable resistance element from the low resistance to the high resistance. A semiconductor device which is driven.

  According to the above [Mode 1], when the variable resistance element is changed from high resistance to low resistance, the on-resistance of the cell transistor is changed by gradually changing the selected word line from the first voltage to the second voltage. The current flowing through the resistance change element is gradually increased while gradually reducing the resistance of the resistance change element so that the resistance change element gradually transitions from a high resistance to a low resistance. As a result, a sudden decrease in potential of the bit line can be prevented, and the maximum current can be accurately controlled. On the other hand, in the case of transition from low resistance to high resistance, it is not necessary to control the maximum current with high accuracy, so that the potential of the word line is quickly transitioned to shorten the writing time.

[Form 2]
When the resistance value of the variable resistance element is written from a high resistance to a low resistance, the word line driving circuit divides the voltage level of the corresponding word line into a plurality of stages in a stepped manner from the first voltage to the first voltage. 2. The mode according to claim 1, wherein when the resistance value is written from a low resistance to a high resistance, a transition is made from the first voltage to the second voltage all at once when the resistance value is written from a low resistance to a high resistance. Semiconductor device.

  According to the above [Mode 2], by changing the voltage stepwise in a plurality of stages, the resistance value of the resistance change element is prevented from changing at once, and the resistance value is lowered stepwise. Therefore, it is possible to prevent a current greater than a desired current value from flowing through the resistance change element due to a sudden decrease in the resistance value. In each of the above embodiments, the voltage is changed in two steps as the step of changing the voltage stepwise. However, even if the gate voltage is controlled in three or more steps, the gate voltage is controlled. Good.

[Form 3]
A variable resistance element having one end connected to the first terminal;
A cell transistor in which one of the source and drain is connected to the other end of the variable resistance element, the other of the source and drain is connected to the second terminal, and a gate is connected to the third terminal;
And applying a voltage of a selection level to a third terminal to set the cell transistor in a conductive state, and passing a predetermined current between the first terminal and the second terminal, A resistance variable memory element writing method capable of writing a resistance value of a resistance change element to a predetermined resistance value,
When setting the resistance value from the high resistance state to the low resistance state,
The first terminal is connected to a current source for flowing a first current, and the third terminal is connected between the first voltage at a non-selection level and the second voltage at a selection level. The resistance value of the resistance change element is changed by causing the cell transistor to conduct in a relatively high resistance state and causing a current smaller than the first current to flow through the resistance change element. A first step of setting a first resistance value between the high resistance state and the low resistance state;
The voltage of the third terminal is gradually changed from the third voltage toward the second voltage, and the on-resistance of the cell transistor is gradually reduced, whereby the value of the current flowing through the resistance change element is gradually increased. A second step of gradually increasing the resistance value of the variable resistance element from the first resistance value to the resistance value in the low resistance state determined by the first current;
A third step of disconnecting the corresponding first terminal from the current source, returning the voltage of the third terminal to the first voltage of the non-selection level, and terminating writing;
A method for writing into a resistance-change memory element, comprising:

[Form 4]
When setting the resistance value from the low resistance state to the high resistance state,
A fourth step of setting the voltage of the third terminal from the first voltage to the second voltage;
After setting the voltage of the third terminal to the second voltage, a second current is passed between the first terminal and the second terminal in a direction opposite to the second step, A fifth step of setting a resistance value of the variable resistance element to the high resistance state;
A sixth step of stopping the second current, returning the voltage of the third terminal from the second voltage to the first voltage, and ending the writing;
The method for writing into a resistance-change memory element according to aspect 3, further comprising:

  Further preferred embodiments of the present invention are described below.

[Appendix 1]
Multiple bit lines,
A plurality of word lines wired in a direction intersecting the plurality of bit lines;
A plurality of memory cells provided in a matrix corresponding to the intersections of the plurality of bit lines and the plurality of word lines;
Source line,
A memory cell array having:
A word line driving circuit which is provided corresponding to the memory cell array and drives a selected word line among the plurality of word lines;
A semiconductor device comprising:
Each of the plurality of memory cells includes
One end is connected to the corresponding bit line, and the resistance change element is writable in a state where the resistance value is high resistance and low resistance by an applied current,
Conduction between the other end of the variable resistance element and the source line is connected to the other end of the variable resistance element, the corresponding word line, and the source line, and is applied to the corresponding word line. A transistor whose non-conduction is controlled,
With
The word line driving circuit includes:
When writing the resistance value of the corresponding variable resistance element from high resistance to low resistance,
The word line to be selected is selected from a first voltage at which the transistor is at a non-selection level to a third voltage at a selection level that is a voltage between the first voltage and a second voltage at which the transistor is at a selection level. And changing the resistance value of the corresponding variable resistance element to a first resistance value in a stage between the high resistance and the low resistance,
After a predetermined time after the transition to the third voltage, the selected word line is transitioned from the third voltage to the second voltage, and the resistance value of the corresponding variable resistance element is changed to the low resistance. A semiconductor device characterized by being set.

[Appendix 2]
The word line driving circuit includes:
When writing the resistance value of the variable resistance element from high resistance to low resistance,
After the first time has elapsed since the word line was transitioned from the first voltage to the third voltage, a second time was taken from the third voltage to the second voltage. The voltage of the word line is gradually changed,
When writing the resistance value of the variable resistance element from low resistance to high resistance,
Supplementary note 1 wherein the word line is transited from the first voltage to the second voltage within a third time shorter than the first time and shorter than the second time. The semiconductor device described.

[Appendix 3]
The word line driving circuit includes:
A word line driver connected to the word line;
A second word line driver power supply circuit for supplying the second voltage to the word line driver;
A third word line driver power supply circuit for supplying the third voltage to the word line driver;
The semiconductor device according to appendix 1 or 2, characterized by comprising:

[Appendix 4]
The word line driving circuit includes:
A word line driver that directly drives the selected word line;
A first word line driver power supply circuit for supplying the second voltage to the word line driver when the variable resistance element is written from a low resistance to a high resistance and when reading a memory cell;
A second word line driver power supply circuit for supplying the second voltage to the word line driver when the variable resistance element is written from a high resistance to a low resistance;
A third word line driver power supply circuit for supplying the third voltage to the word line driver;
With
The second word line driver power supply circuit has a higher output impedance than the first word line driver power supply circuit,
When writing the variable resistance element from a high resistance to a low resistance, the third word line triber power supply circuit is activated, and the selected word line is set from the first voltage to the third voltage. The third word line driver power supply circuit is deactivated, the second word line driver power supply circuit is activated, and the selected word line is further set to the second voltage from the third voltage. The semiconductor device according to appendix 1 or 2, wherein:

[Appendix 5]
The semiconductor device includes:
A light amplifier,
A bit line selection circuit for connecting a bit line selected at the time of writing to the write amplifier and a bit line not selected to be connected to the source line;
Further comprising
The write operation is performed on the resistance change element of the selected memory cell by causing a current to flow between the write amplifier and the source line via the bit line selection circuit, the selected bit line, and the selected memory cell. 5. The semiconductor device according to any one of appendices 1 to 4, wherein:

[Appendix 6]
When writing from the high resistance state to the low resistance state of the corresponding variable resistance element, the voltage of the word line to be selected is selected while conducting the current to the corresponding variable resistance element by turning on the write amplifier. The semiconductor device according to appendix 5, characterized by gradually transitioning the voltage to the second voltage.

[Appendix 7]
When writing the corresponding variable resistance element from a low resistance state to a high resistance state, the voltage of the selected word line is transitioned to a second voltage in advance, and then the write amplifier is turned on. 7. The semiconductor device according to appendix 6, wherein the writing is started.

[Appendix 8]
When the command given from the outside is a command to rewrite the resistance change element of the selected memory cell from high resistance to low resistance,
A first control for fixing the source line to a low potential, connecting a selected bit line of the plurality of bit lines to the write amplifier, and connecting a non-selected bit line to the source line;
After the first control, the selected word line is set to a third voltage, which is a voltage between the first voltage and the second voltage, and the write amplifier is turned on to A current is passed through the source line via the selected bit line and the selected memory cell, and a resistance value of the variable resistance element is changed from the high resistance to the high resistance and the low resistance. A second control for transitioning to a value;
After the second control, the voltage of the selected word line is slowly shifted from the third voltage to the second voltage, and the variable resistance element of the selected memory cell is changed to the first resistance value. A third control for making a transition from low to low resistance;
A fourth control for ending the driving of the write amplifier after the third control and ending the driving of the selected word line at the third voltage;
The semiconductor device according to any one of appendices 5 to 7, further comprising a command control circuit for executing

[Appendix 9]
9. The semiconductor device according to appendix 8, wherein in the second control, control for setting the selected word line to the third voltage is performed, and then control for turning on the write amplifier is performed.

[Appendix 10]
9. The semiconductor device according to appendix 8, wherein in the second control, control is performed to turn on the write amplifier, and then control to set the selected word line to the third voltage is performed.

[Appendix 11]
When the command given from the outside is a command to rewrite the resistance change element of the selected memory cell from low resistance to high resistance,
The command control circuit includes:
The source line is raised from a low potential to a high potential, and among the plurality of bit lines, a selected bit line is connected to the write amplifier, and a non-selected bit line is connected to the source line. Control,
After the fifth control, the selected word line is set to the second voltage, and the write amplifier is turned on to pass the selected memory cell and the selected bit line from the source line. A sixth control for passing a current to the write amplifier;
After the sixth control, the driving of the write amplifier is terminated, the driving of the selected word line at the second voltage is terminated, and the seventh control for returning the potential of the source line to a low potential When,
11. The semiconductor device according to any one of appendices 8 to 10, wherein:

[Appendix 12]
12. The semiconductor device according to any one of appendices 5 to 11, wherein the write amplifier includes a constant current source transistor that controls a constant current to flow through a selected bit line.

[Appendix 13]
13. The semiconductor device according to claim 12, wherein the write amplifier further includes a clamp transistor that is connected to a current output terminal of the constant current source transistor and clamps an output voltage of the current output terminal to a constant voltage.

[Appendix 14]
The current output terminal and the reference voltage are connected to the differential input terminal, the output terminal is connected to the gate of the clamp transistor, and the voltage of the current output terminal becomes a constant voltage based on the voltage value of the reference voltage 14. The semiconductor device according to appendix 13, further comprising a differential circuit that controls the above.

[Appendix 15]
When writing the variable resistance element from a high resistance to a low resistance, the resistance value of the variable resistance element is controlled to three or more multi-values by changing the value of the current flowing through the write amplifier and writing. 15. The semiconductor device according to any one of appendices 5 to 14, wherein the cell is a multi-value memory cell that stores three or more values.

[Appendix 16]
Each of the write amplifiers includes a plurality of current source transistors having different current values corresponding to the multi-values, and the write amplifier is configured to perform writing from among the plurality of current source transistors having different current values depending on the multi-values to be written. 16. The semiconductor device according to appendix 15, wherein the writing is executed by selecting a current source transistor to be used.

[Appendix 17]
The write amplifier further includes a plurality of switch transistors connected in series with the plurality of current source transistors, respectively, and by controlling conduction / non-conduction of the plurality of switch transistors, a current value flowing through the write amplifier is determined. 18. The semiconductor device according to appendix 16, wherein the semiconductor device is controlled.

[Appendix 18]
16. The semiconductor device according to appendix 15, further comprising a bias voltage selection circuit that controls a bias voltage applied to the current source transistor in multiple stages in accordance with the multi-value to control a current value to be supplied to the current source transistor.

[Appendix 19]
A plurality of the memory cell arrays;
A plurality of the word line drive circuits provided corresponding to the plurality of memory cell arrays,
A plurality of the bit line selection circuits provided corresponding to the plurality of memory cell arrays,
Global bit lines,
A sense amplifier connected to the global bit line;
A plurality of switches provided corresponding to the plurality of memory cell arrays, respectively, for connecting the bit lines of the corresponding memory cell array selected by the corresponding bit line selection circuit and the global bit lines;
With
During the read operation, the switch corresponding to the selected memory cell array among the plurality of memory cell arrays is turned on, and the memory cell selected by the word line and the bit line is selected in the selected memory cell array. The semiconductor device according to any one of appendices 5 to 18, wherein the semiconductor device is connected to a global bit line, and the resistance value of the variable resistance element of the selected memory cell is read as data by the sense amplifier.

[Appendix 20]
20. The semiconductor device according to claim 19, further comprising a plurality of the write amplifiers provided corresponding to the plurality of memory cell arrays, wherein the switch is controlled to be non-conductive during a write operation.

[Appendix 21]
The write amplifier is connected to the global bit line;
At the time of the write operation for performing the write to the resistance change element of the memory cell selected based on the data input from the outside,
The switch of the selected memory cell array is controlled to be conductive among the plurality of memory cell arrays, and the selected memory cell of the selected memory cell array includes the bit line selection circuit, the switch, and the global 20. The semiconductor device according to appendix 19, wherein the semiconductor device is connected to the light amplifier via a switch.

[Appendix 22]
When writing the selected variable resistance element from a high resistance to a low resistance, a current is passed from the write amplifier to the source line via the selected variable resistance element,
When writing the selected resistance change element from a low resistance to a high resistance, the current flows in the opposite direction from the case of writing from the high resistance to the low resistance from the source line to the write amplifier via the selected resistance change element. Shed
22. The semiconductor device according to any one of appendices 5 to 21, wherein writing is performed respectively.

[Appendix 23]
The variable resistance element is
A first electrode connected to the one end;
A second electrode connected to the other end;
An insulating film sandwiched between the first electrode and the second electrode;
The semiconductor device according to any one of appendices 1 to 22, wherein the semiconductor device is provided.

[Appendix 24]
A plurality of memory cells provided in a matrix corresponding to the intersections of a plurality of bit lines and a plurality of word lines, respectively,
Each of the memory cells
A resistance change element capable of writing in a state where a resistance value is high resistance and a state where the resistance value is low resistance by a current flowing at one end connected to the corresponding bit line;
The word line and the source line corresponding to the other end of the variable resistance element are connected to the word line and the source line, and a voltage applied to the corresponding word line causes conduction / conduction between the other end of the variable resistance element and the source line. A transistor whose non-conduction is controlled;
In a semiconductor device comprising:
When selecting the bit line and the word line and writing the resistance value of the corresponding variable resistance element from high resistance to low resistance,
The selected bit line is connected to a current source, and the selected word line is connected to a third voltage which is a voltage between the first voltage at the non-selection level and the second voltage at the selection level. A first control for making a transition to a voltage and changing a resistance value of the corresponding variable resistance element to a first resistance value in a stage between the high resistance and the low resistance;
A second control for transitioning the selected word line from the third voltage to the second voltage and setting the first resistance value of the corresponding variable resistance element to the low resistance;
A third control for returning the selected word line to the first voltage, disconnecting the selected bit line from the current source, and finishing writing to the corresponding variable resistance element;
A method for controlling a semiconductor device, comprising:

[Appendix 25]
When selecting the bit line and the word line and writing the resistance value of the corresponding variable resistance element from low resistance to high resistance,
A fourth control for causing the selected word line to transition from the first voltage to the second voltage;
A fifth control for causing a current to flow through the selected bit line in a state in which the selected word line has transitioned to the second voltage, and causing the resistance value of the corresponding variable resistance element to transition from the low resistance to the high resistance;
A sixth control for returning the selected word line to the first voltage and stopping the current flowing through the selected bit line to finish writing to the corresponding variable resistance element;
The method of controlling a semiconductor device according to appendix 24, further comprising:

[Appendix 26]
A memory section;
A control unit that controls the operation of the memory unit and performs information processing using information stored in the memory unit;
In a memory system comprising:
The memory unit is
Multiple bit lines,
A plurality of word lines wired in a direction intersecting the plurality of bit lines;
A plurality of memory cells provided in a matrix corresponding to intersections of the plurality of bit lines and the plurality of word lines;
Source line,
A word line driving circuit for driving a selected word line among the plurality of word lines;
With
Each memory cell has
A resistance change element capable of writing in a state where a resistance value is high resistance and a state where the resistance value is low resistance by a current flowing at one end connected to the corresponding bit line;
Conduction between the other end of the variable resistance element and the source line is connected to the word line and the source line corresponding to the other end of the variable resistance element, and is applied to the corresponding word line. A transistor whose non-conduction is controlled,
With
When the bit line and the word line are selected and the resistance value of the corresponding variable resistance element is written from a high resistance state to a low resistance state, the word line driving circuit selects the word line to be selected at a non-selection level. A gradual transition from a first voltage to a second voltage at a selected level, and before the transition to the second voltage is completed, the resistance value of the resistance change element is transitioned to the low resistance state;
When the memory unit receives a data write command from the control unit, the memory unit performs the writing by replacing data with a resistance value of the resistance change element, and when the memory unit receives a data read command from the control unit, the resistance change element A memory system that performs data reading by replacing the resistance value of data with data.

  Within the scope of the entire disclosure (including claims and drawings) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. In addition, various combinations or selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention naturally includes various modifications and changes that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

10: Semiconductor device 10a: Memory part 11: Memory array (Memory array)
12: Sense amplifier (Sense amp.)
13: Column decoder
14: X decoder
15: Mode register
16: Row address buffer
17: Column address buffer and burst counter (Column address buffer and burst counter)
18: Data control circuit (Data control circuit)
19: Command decoder
20: Command control circuit (Command control circuit)
21: Data input / output circuit (Data Input / Output circuit)
22: Clock generator
23: DLL circuit (DLL circuit)
30: Memory cell array 31: Bit line 32: (Sub) word line 33: Source line 36: Source line driver 40: Memory cell 41: Resistance change element 42: (Cell) transistor 45: First electrode 46: Second Electrode 47: Insulating film 50: Sub word line drive circuit 51, 151: Sub word driver 52, 152: Word line power supply circuit section 53: First word line power supply circuit 54: Second word line power supply circuit 55, 55a: Third 55-1: PMOS transistor 55-2: NMOS transistor 56: Selector 57: Main word line driver 58, 58-1, 58-2: Address decoder 60, 60a, 60b, 60c, 60d, 60e, 160: Write amplifier circuit 61, 61a, 61b, 61d, 61e: SET driver 62 Constant current source transistor 63: clamp transistor 64: switching transistor (PMOS transistor)
65: Differential amplifier 67: RESET selector 68: Switch transistor (NMOS transistor)
69: VSETREF selector 70: Bit line selection circuit 71-74: Bit line selection switch 75: Common bit line 76: Source line common bit line connection switch 80: Memory array 81: Global bit line 82: Sense amplifier 83: Switch (global Bit line selection switch)
84: Main word line 90: Memory system 91: System bus 92: Control unit 93: I / O device 94: DRAM
95: SRAM
96: ROM

Claims (29)

A memory cell including a resistance change element that stores information in a resistance value and that is connected in series with each other, and a transistor that accesses the resistance change element,
A bit line connected to one end of the memory cell;
A source line connected to the other end of the memory cell;
A word line connected to the gate electrode of the transistor;
A word line driving circuit for supplying a voltage to the word line,
The word line driving circuit includes:
When setting the resistance value of the variable resistance element from high resistance to low resistance,
The word line is a voltage between a first voltage that causes the transistor to become non-conductive, and a voltage between the first voltage and a second voltage that causes the transistor to become conductive with a first impedance. A transition is made to a third voltage for conducting with a second impedance higher than the first impedance, and the resistance value of the variable resistance element is changed to a first resistance value at a stage between the high resistance and the low resistance. Change
A predetermined time after the transition to the third voltage, the word line is transitioned from the third voltage to the second voltage, and the resistance value of the variable resistance element is set to the low resistance; A semiconductor device. The word line driving circuit includes:
When resetting the resistance value of the variable resistance element from low resistance to high resistance,
2. The semiconductor device according to claim 1, wherein the word line is transited from the first voltage to the second voltage without having the predetermined time. Furthermore, a bit line control circuit for controlling the voltage of the bit line is provided,
When the semiconductor device sets the resistance value of the variable resistance element,
3. The semiconductor device according to claim 2, wherein the bit line control circuit supplies a fourth voltage to the bit line after the word line transitions to the third voltage. A source line control circuit for controlling the voltage of the source line;
When the semiconductor device sets the resistance value of the variable resistance element,
4. The semiconductor device according to claim 3, wherein the source line control circuit supplies a fifth voltage that is lower in absolute value than the fourth voltage to the source line. When the semiconductor device resets the resistance value of the variable resistance element,
The semiconductor device according to claim 4, wherein the bit line control circuit supplies a sixth voltage to the bit line after the word line transitions to the second voltage. When the semiconductor device resets the resistance value of the variable resistance element,
6. The semiconductor device according to claim 5, wherein the source line control circuit supplies a seventh voltage that is higher in absolute value than the sixth voltage to the source line. Furthermore, a bit line control circuit for controlling the voltage of the bit line is provided,
When the semiconductor device sets the resistance value of the variable resistance element,
3. The semiconductor device according to claim 2, wherein the bit line control circuit supplies a fourth voltage to the bit line before the word line makes a transition to the third voltage. A source line control circuit for controlling the voltage of the source line;
When the semiconductor device sets the resistance value of the variable resistance element,
8. The semiconductor device according to claim 7, wherein the source line control circuit supplies a fifth voltage that is lower in absolute value than the fourth voltage to the source line. When the semiconductor device resets the resistance value of the variable resistance element,
The bit line control circuit supplies a sixth voltage to the bit line;
9. The semiconductor device according to claim 8, wherein the source line control circuit supplies a seventh voltage that is higher in absolute value than the sixth voltage to the source line. The word line driving circuit includes:
A word line driver connected to the word line;
A second word line driver power supply circuit for supplying the second voltage to the word line driver;
A third word line driver power supply circuit for supplying the third voltage to the word line driver;
The semiconductor device according to claim 1, further comprising: The word line driving circuit further includes:
A first word line driver power supply circuit for supplying the second voltage to the word line driver at the time of reset;
The second word line driver power supply circuit supplies the second voltage to the word line driver during the setting,
11. The semiconductor device according to claim 10, wherein the third word line driver power supply circuit supplies the third voltage to the word line driver at the time of setting. The word line driving circuit includes:
In the setting, the transition is made from the third voltage to the second voltage in a first time,
3. The semiconductor device according to claim 2, wherein, when the reset is performed, the transition is performed from the first voltage to the second voltage in a second time shorter than the first time. Furthermore, a bit line control circuit for controlling the voltage of the bit line is provided,
The bit line control circuit includes:
A set driver for supplying a fourth voltage to the bit line during the setting;
The semiconductor device according to claim 2, further comprising a reset driver that supplies a sixth voltage to the bit line at the time of the reset.   The set driver includes a constant current source transistor that supplies a constant current and a clamp transistor that makes a voltage between a drain terminal and a source terminal of the constant current source transistor constant, which are connected in series to each other. Item 14. A semiconductor device according to Item 13.   15. The semiconductor device according to claim 14, further comprising a differential amplifier having an output node connected to a gate terminal of the clamp transistor and comparing a voltage of a drain terminal of the constant current source transistor with a predetermined voltage. .   The semiconductor device according to claim 13, wherein the set driver includes a transistor that supplies a constant current defined by a channel width. The semiconductor device includes:
A plurality of the bit lines;
A plurality of the word lines wired in a direction intersecting with the plurality of bit lines;
A plurality of memory cells each including a plurality of memory cells provided in a matrix corresponding to respective intersections of the plurality of bit lines and the plurality of word lines;
A global bit line associated with the plurality of bit lines and a plurality of memory cell arrays;
A main word line associated with the plurality of word lines and a plurality of memory cell arrays;
The semiconductor device according to claim 2, further comprising: a bit line control circuit that controls voltages of the plurality of bit lines.   18. The semiconductor device according to claim 17, wherein the word line driving circuit is connected to the main word line.   The semiconductor device according to claim 18, wherein the bit line control circuit is connected to the global bit line.   20. The semiconductor device according to claim 19, wherein each of the plurality of memory cell arrays includes the bit line control circuit connected to the corresponding global bit line.   14. The semiconductor device according to claim 13, wherein the set driver supplies a plurality of constant currents having different current values and controlling the resistance value of the variable resistance element to multiple values to the bit line.   The semiconductor device according to claim 21, wherein the set driver includes a plurality of transistors that respectively supply the plurality of constant currents.   23. The semiconductor device according to claim 22, wherein channel widths of the plurality of transistors are different from each other.   23. The semiconductor device according to claim 22, wherein a plurality of signals each having a different voltage corresponding to the multi-value are supplied to each gate terminal of the plurality of transistors.   22. The semiconductor device according to claim 21, wherein the set driver includes a transistor that supplies the plurality of constant currents according to a voltage supplied to a gate terminal.   26. The semiconductor device according to claim 25, wherein the set driver further includes a selector that generates a voltage to be supplied to the gate terminal.   27. The semiconductor device according to claim 26, wherein the selector selects a plurality of different voltages corresponding to the multi-value and supplies the selected voltage to the gate terminal.   28. The set driver according to claim 25, wherein the set driver includes a transistor that supplies a constant current, and a clamp transistor that makes a voltage between a drain terminal and a source terminal of the transistor constant. The semiconductor device as described in any one. A memory section;
A control unit that controls the operation of the memory unit and performs information processing using information stored in the memory unit;
In a memory system comprising:
The memory unit is
A memory cell including a resistance change element that stores information in a resistance value and that is connected in series with each other, and a transistor that accesses the resistance change element,
A bit line connected to one end of the memory cell;
A source line connected to the other end of the memory cell;
A word line connected to the gate electrode of the transistor;
A word line driving circuit for supplying a voltage to the word line,
The word line driving circuit includes:
When setting the resistance value of the variable resistance element from high resistance to low resistance,
The word line is a voltage between a first voltage that causes the transistor to become non-conductive, and a voltage between the first voltage and a second voltage that causes the transistor to become conductive with a first impedance. A transition is made to a third voltage for conducting with a second impedance higher than the first impedance, and the resistance value of the variable resistance element is changed to a first resistance value at a stage between the high resistance and the low resistance. Change
A predetermined time after the transition to the third voltage, the word line is transitioned from the third voltage to the second voltage, and the resistance value of the variable resistance element is set to the low resistance;
A memory system characterized by that.

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