CN102074508A - Process for integrating Schottky diode in power MOS transistor - Google Patents

Process for integrating Schottky diode in power MOS transistor Download PDF

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Publication number
CN102074508A
CN102074508A CN2009102018564A CN200910201856A CN102074508A CN 102074508 A CN102074508 A CN 102074508A CN 2009102018564 A CN2009102018564 A CN 2009102018564A CN 200910201856 A CN200910201856 A CN 200910201856A CN 102074508 A CN102074508 A CN 102074508A
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CN
China
Prior art keywords
contact hole
mos transistor
schottky diode
process
power mos
Prior art date
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CN2009102018564A
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Chinese (zh)
Inventor
邵向荣
魏炜
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上海华虹Nec电子有限公司
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Application filed by 上海华虹Nec电子有限公司 filed Critical 上海华虹Nec电子有限公司
Priority to CN2009102018564A priority Critical patent/CN102074508A/en
Publication of CN102074508A publication Critical patent/CN102074508A/en

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Abstract

The present invention discloses a process for integrating a Schottky diode in a power MOS transistor, comprising the steps of: (1) performing Body injection, photo-resister stripping and Body propelling on a substrate sheet in order, wherein the substrate sheet has already undergone grid silica barrier layer etching; (2) performing grid channel etching to form a grid; (3) performing source injection and source region propelling; (4) performing contact aperture etching; (5) performing contact aperture injection for the first time; (6) performing contact aperture groove etching; (7) performing contact aperture injection for the second time; and (8) performing the follow-up process steps, i.e., performing metal deposition, exposure and etching in order. The process for integrating the Schottky diode in the power MOS transistor of the invention, which makes improvements on the basis of the existing process for integrating a Schottky diode in a power MOS transistor, has the advantages of eliminating photoetching layers, simplifying the process flow and reducing the product cost.

Description

The process of integrated schottky diode in the power MOS transistor

Technical field

The present invention relates to a kind of manufacture method of semiconductor device, relate in particular to the process of integrated schottky diode in a kind of power MOS transistor.

Background technology

In semiconductor integrated circuit, the structure of existing more advanced power MOS transistor integrated schottky diode as shown in Figure 1.

The power MOS transistor integrated schottky diode, the friendship that can significantly improve device is characteristic frequently.Existing advanced power MOS transistor integrated schottky diode structure shown in Figure 1, be infused in the contact hole channel bottom by contact hole and formed Schottky diode, its technical process needs one lithography layer to stop the contact hole zone when Body injects, form the process need twice etching at the contact hole groove, this technology obviously has following shortcoming:

Need lithography layer to stop the contact hole zone when (1) Body injects, increased photoetching and technology;

Contact hole etching groove when (2) forming schottky area need be divided into for two steps to carry out.

Though as seen existing advanced process can form schottky area in power MOS transistor contact hole bottom, still exists technological process to optimize inadequately, the more high shortcoming of cost has limited its market prospects.How reducing lithography layer, reduce processing step, reduce cost, is the purpose that the present invention will reach.

Summary of the invention

The technical problem to be solved in the present invention provides the process of integrated schottky diode in a kind of power MOS transistor, the present invention further improves on the technology basis of existing power MOS transistor integrated schottky diode, reduced lithography layer, simplify technological process, reduced product cost.

For solving the problems of the technologies described above, the invention provides the process of integrated schottky diode in a kind of power MOS transistor, comprise the steps:

(1) carrying out Body injection, removing photoresistance and Body successively on the substrate of finishing the gate silicon dioxide barrier etch advances;

(2) grid groove etching forms grid;

(3) source is injected and the source region propelling;

(4) contact hole etching;

(5) contact hole injects for the first time;

(6) contact hole etching groove;

(7) contact hole injects for the second time;

(8) subsequent technique comprises and carries out metal deposit, exposure and etching successively.

Compare with prior art, the present invention has following beneficial effect: the present invention is on the technology basis of existing power MOS transistor integrated schottky diode, inject and the contact hole injection technology by new Body, delete Body and injected lithography layer, reduced the contact hole etching groove one, realize the device function of existing technology equally, accomplished contact hole bottom integrated schottky diode, be implemented in integrated schottky diode in each MOS transistor unit.In the realization of concrete technology, do not increase complicated technical process, reduced product cost.

Description of drawings

Fig. 1 is the structural representation of existing power MOS transistor integrated schottky diode;

Fig. 2 is the structural representation of power MOS transistor integrated schottky diode of the present invention;

Fig. 3~Fig. 6 is the process implementation method schematic diagram of power MOS transistor device of the present invention;

After Fig. 3 was the silicon dioxide barrier etch, Body injected, removing photoresistance, the schematic diagram of propelling;

Fig. 4 is the grid groove etching, and grid forms, and the source region is injected, the schematic diagram of propelling;

Fig. 5 is the contact hole exposure, etching, the schematic diagram of contact hole injection for the first time;

Fig. 6 is the contact hole etching groove, removing photoresistance, and contact hole injects for the second time, the schematic diagram of rapid thermal annealing;

Fig. 7 is the process chart of the inventive method.

Wherein, 1 is silicon substrate, and 2 is the silicon dioxide barrier layer, and 3 are the Body district, and 4 is the source region, and 5 is the channel-type grid, and 6 is contact hole isolating layer, and 7 is that contact hole injects for the first time, and 8 is that contact hole injects for the second time, and 9 is the contact hole groove.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and Examples.

The power MOS transistor device that the present invention is mentioned, on the basis of original structure, inject and the contact hole injection technology by new Body, reduced the Body lithography layer, formed Schottky diode in the contact hole bottom of MOS transistor equally with the contact hole etching groove.As Fig. 3-shown in Figure 7, concrete technology realization flow of the present invention is as follows:

(1) carry out Body on the substrate of finishing gate silicon dioxide barrier layer 2 etchings (silicon substrate 1) and inject, remove photoresistance, thermal diffusion Body advances, and forms Body district 3, sees Fig. 3; According to different threshold voltage requirements, the energy that Body injects is 120KeV-240KeV in this step, and dosage is 0.8-2.4E13, and angle is the 0-15 degree, and the time of propelling is 30-100 minute, and temperature is at 1000-1150 degree centigrade; The Body district is formed on when guaranteeing that the MOS transistor device channel forms, and need guarantee that also the contact hole trenched side-wall contacts with the Body district, and guarantee that the Body district can not diffuse to contact hole channel bottom zone;

(2) grid groove etching, the degree of depth are 1.0 to 2.0um (microns), form channel-type grid 5;

(3) source is injected, energy 50-80KeV, and dosage 1.0-8.0E15, source region 4 advances temperature at 900-950 degree centigrade, and the time is 30-60 minute, sees Fig. 4;

(4) contact hole isolating layer 6 etchings (contact hole exposes, is etched to epi-layer surface, epitaxial loayer over etching 100-500 dust);

(5) contact hole injects 7 for the first time, sees Fig. 5; Heavy dose of contact hole injected and should guarantee that the contact hole sidewall forms ohmic contact this first time, and implantation dosage is the B+ ion of 1.0-5.0E15;

(6) contact hole groove 9 etchings, the degree of depth of contact hole groove 9 is the 4000-7000 dust, removes photoresistance;

(7) contact hole injects 8 for the second time, and rapid thermal annealing is seen Fig. 6.Low dose of contact hole is infused in contact hole groove bilateral and near the bottom, need guarantees not to be infused in channel bottom for the second time, forms Schottky contacts.The energy that this second time, contact hole injected is 20-60KeV, and dosage is the B+ ion of 0.3-1.2E13, and implant angle is adjusted from the 30-60 degree according to the contact hole depth-to-width ratio.

(8) subsequent technique and conventional power MOS transistor device making technology are in full accord, comprise and carry out metal deposit, exposure, etching successively.

The final power MOS transistor integrated schottky diode structure that forms as shown in Figure 2.Comparison diagram 1, Fig. 2 can find out significantly, compared to Figure 1 the contact hole groove is more level and smooth for its structure of technology after the improvement, help follow-up metal deposit, twice some difference of contact hole injection zone, all the other structures are in full accord, realized the device function same, but saved a layer photoetching, simplified technological process with the contact hole etching groove with existing technology.

Claims (8)

1. the process of the interior integrated schottky diode of power MOS transistor is characterized in that: comprise the steps:
(1) carrying out Body injection, removing photoresistance and Body successively on the substrate of finishing the gate silicon dioxide barrier etch advances;
(2) grid groove etching forms grid;
(3) source is injected and the source region propelling;
(4) contact hole etching;
(5) contact hole injects for the first time;
(6) contact hole etching groove;
(7) contact hole injects for the second time;
(8) subsequent technique comprises and carries out metal deposit, exposure and etching successively.
2. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (1), according to different threshold voltage requirements, the energy that described Body injects is 120KeV-240KeV, dosage is 0.8-2.4E13, angle is the 0-15 degree, and the time that Body advances is 30-100 minute, and temperature is 1000-1150 degree centigrade.
3. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (2), the degree of depth of described grid groove etching is 1.0 to 2.0 microns.
4. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (3), the energy that described source is injected is 50-80KeV, and dosage is 1.0-8.0E15, the temperature that described source region advances is at 900-950 degree centigrade, and the time is 30-60 minute.
5. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (4), described contact hole etching is specially: contact hole exposes, is etched to epi-layer surface, and epitaxial loayer over etching 100-500 dust forms contact hole isolating layer.
6. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (5), the described contact hole injection first time should guarantee that the contact hole sidewall forms ohmic contact, and implantation dosage is the B+ ion of 1.0-5.0E15.
7. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (6), the degree of depth of described contact hole groove is the 4000-7000 dust.
8. the process of integrated schottky diode in the power MOS transistor as claimed in claim 1, it is characterized in that: in the step (7), described second time, contact hole was infused in contact hole groove bilateral and near the bottom, need guarantee not to be infused in channel bottom, form Schottky contacts, the energy that this second time, contact hole injected is 20-60KeV, and dosage is the B+ ion of 0.3-1.2E13, and implant angle is adjusted from the 30-60 degree according to the contact hole depth-to-width ratio.
CN2009102018564A 2009-11-24 2009-11-24 Process for integrating Schottky diode in power MOS transistor CN102074508A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1547765A (en) * 2001-08-23 2004-11-17 通用半导体公司 Trench dmos transistor with embedded trench schottky rectifier
CN101404283A (en) * 2007-10-01 2009-04-08 万国半导体股份有限公司 Planar MOSFET integrated with schottky diode and its layout method
CN101465374A (en) * 2007-12-21 2009-06-24 万国半导体股份有限公司 MOS device with integrated schottky diode in active region contact trench

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1547765A (en) * 2001-08-23 2004-11-17 通用半导体公司 Trench dmos transistor with embedded trench schottky rectifier
CN101404283A (en) * 2007-10-01 2009-04-08 万国半导体股份有限公司 Planar MOSFET integrated with schottky diode and its layout method
CN101465374A (en) * 2007-12-21 2009-06-24 万国半导体股份有限公司 MOS device with integrated schottky diode in active region contact trench

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Application publication date: 20110525

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