CN102043416B - Low dropout linear voltage regulator - Google Patents
Low dropout linear voltage regulator Download PDFInfo
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- CN102043416B CN102043416B CN200910209941.5A CN200910209941A CN102043416B CN 102043416 B CN102043416 B CN 102043416B CN 200910209941 A CN200910209941 A CN 200910209941A CN 102043416 B CN102043416 B CN 102043416B
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Abstract
The invention provides a low dropout linear voltage regulator which comprises a differential amplifier, a first inverting amplifier, a last-stage inverting amplifier, a follower and a last-stage inverting amplifier output load, wherein the first inverting amplifier is connected with the differential amplifier in cascade; the output end of the first inverting amplifier is connected with a first inverting amplifier output load; the last-stage inverting amplifier output load is independent of the first inverting amplifier output load; the output end of the last-stage inverting amplifier is connected with the input end of the follower; the last-stage inverting amplifier output load is connected into the output end of the last-stage inverting amplifier; and the output end of the follower is connected with the output end of the first inverting amplifier. The low-differential-voltage linear voltage regulator has the advantages of high reaction speed, high stability and high cut-off current precision.
Description
Technical field
The present invention relates to a kind of low pressure difference linear voltage regulator voltage stabilizer.
Background technology
Voltage stabilizer in electronic circuit, for the burning voltage maintaining within the scope of certain tolerance is provided, powers to guarantee that to specific features it normally moves.Low pressure difference linear voltage regulator (LDO voltage stabilizer, Low Dropout Voltage Regulator) is to be described in 11/406,172,11/129,801 U.S. Patent application being merged in by reference sequence number herein.
Shown in Fig. 1 is the structure block diagram of LDO voltage stabilizer of the prior art.LDO voltage stabilizer 100 of the prior art comprises the differential amplifier A0 of cascade successively, the first inverting amplifier A1 and the second inverting amplifier A2, wherein the input end ref of differential amplifier A0 is connected to reference voltage REF0, the output terminal of the first inverting amplifier A1 is connected to the first inverting amplifier output load L1, between the inverting input fb of the output terminal of the second inverting amplifier A2 and differential amplifier, be connected with feedback circuit F, thereby differential amplifier A0, the first inverting amplifier A1, the second inverting amplifier A2, feedback circuit F forms the negative feedback amplifying return circuit with voltage regulation result.The output terminal of the second inverting amplifier A2 is as the output terminal of this LDO voltage stabilizer 100.LDO voltage stabilizer 100 also comprises positive amplifier A3 and final stage inverting amplifier A4, and positive amplifier A3 and final stage inverting amplifier A4 form the current limliting loop in LDO voltage stabilizer.The input end of this positive amplifier A3 is connected with the output terminal of described the first inverting amplifier A1, the output terminal of positive amplifier A3 is connected with the input end of final stage inverting amplifier A4, the output terminal of final stage inverting amplifier A4 is connected with the output terminal of the first inverting amplifier A1, and shares the first inverting amplifier output load L1 with the first inverting amplifier A1.The voltage of final stage inverting amplifier A4 output is used for the voltage of the input end of stablizing the second inverting amplifier A2.In the course of work of LDO voltage stabilizer, the electric current of external load increases, and the electric current of the output terminal of voltage stabilizer also increases thereupon.When external load electric current hour, the work of negative feedback amplifying return circuit, externally stable output voltage; When external loading Current rise to a certain extent, now can make the first inverting amplifier close, final stage inverting amplifier is opened, and starts working in current limliting loop, with stablize the second inverting amplifier A2 input end voltage and make LDO voltage stabilizer externally export steady current.
In the use of existing voltage stabilizer, conventionally wish that this voltage stabilizer for example, in the time of the electric current less (voltage stabilizer zero load) of the output terminal of voltage stabilizer, the quiescent current of system inside at different levels (for example, in differential amplifier, the first inverting amplifier and/or the first inverting amplifier output load) is less, reduce whereby internal loss, raise the efficiency; But, in the time that voltage stabilizer is under the duty of large current value or running current, due to relative power output, internal loss is negligible, so wish that again internal current can be suitably large, can improve system reaction velocity at different levels and stability whereby.For achieving the above object, feasible method be make such as differential amplifier and/or the first inverting amplifier variation tendency of electric current and curent change trend of the output terminal of described LDO voltage stabilizer at different levels consistent.
But said method can make the gain of final stage inverting amplifier output voltage reduce.Physical circuit figure below in conjunction with LDO voltage stabilizer is as shown in Figure 2 specifically described this problem.Fig. 2 is the concrete wiring diagram of LDO voltage stabilizer as shown in Figure 1.Wherein the first inverting amplifier A1 comprises PMOS field effect transistor P1, and the grid of P1 is connected with the output terminal of differential amplifier A0 as the input end of the first inverting amplifier A1, and the drain electrode of P1 is as the output terminal of the first inverting amplifier A1." connection " as referred to herein refers to both and is directly electrically connected.The second inverting amplifier A2 comprises PMOS field effect transistor P2, and the grid of P2 is connected as the second input end of inverting amplifier A2 and the drain electrode of P1, and the drain electrode of P2 is as the output terminal of the second inverting amplifier A2, that is the output terminal of LDO voltage stabilizer.Feedback circuit F comprises resistance R 1 and R2.The first inverting amplifier output load L1 comprises two NMOS field effect transistor N1 and N2, and the drain electrode of N1 and N2 is all connected with P1 output terminal, all ground connection of the source electrode of N1 and N2, and the grid of N1 is connected to reference voltage REF1, keeps grid voltage constant.The input end of positive amplifier A3 is connected with the output terminal of P1.Positive amplifier A3 comprises NMOS field effect transistor N3 and N4, PMOS field effect transistor P3 and resistance R t.The grid of P3 is as the input end of positive amplifier A3.The wherein gate interconnection of P3 and P2, the source electrode of P2 and P3 all connects constant pressure source, and therefore P3 and P2 form current mirroring circuit.Due to the characteristic of current mirror, the electric current I flowing through between the source electrode of P2 and drain electrode
p2and the electric current I flowing through between the source electrode of P3 and drain electrode
p3be directly proportional.The grid of NMOS field effect transistor N3 is connected the drain electrode of P3 with drain electrode, form diode and connect, the electric current I flowing through between the source electrode of P3 and drain electrode
p3and the electric current I flowing through between the drain electrode of N3 and source electrode
n3equate.The gate interconnection of NMOS field effect transistor N3 and N4, all ground connection of their source electrode, therefore N3 and N4 form another current mirror.Electric current I
n3and I
n4be directly proportional.NMOS field effect transistor N4 is connected with resistance R t, and the output terminal of positive amplifier 13 is the tie point of NMOS field effect transistor N4 and resistance R t.In positive amplifier A3, P3 and N3 form common-source stage inverting amplifier, and through this common-source stage inverting amplifier, anti-phase and amplification exports N4 to the voltage of input P3, and N4 and Rt form another common-source stage inverting amplifier, and therefore, voltage is through anti-phase and amplify again.Because wherein voltage is through twice anti-phase amplification, therefore amplifier 13 is positive amplifiers.
The grid of NMOS field effect transistor N2 in the first inverting amplifier load L1 is connected with the grid of the NMOS field effect transistor N3 in positive amplifier A3, and all ground connection of the source electrode of N2 and N3, therefore N2 and N3 form another current mirroring circuit, the electric current I on NMOS field effect transistor N3
n3and I
n2be directly proportional.In addition, the electric current I flowing through between the source electrode of P2 and drain electrode
p2split into the electric current of the output terminal of electric current on resistance R 1 circuit and LDO voltage stabilizer, but electric current on resistance R 1 circuit is less, negligible, therefore in fact can thinks electric current I
p2equate with the electric current of the output terminal of LDO mu balanced circuit.Therefore, as mentioned above, due to the electric current I on NMOS field effect transistor N3
n3with become I
n2direct ratio, and I
n3=I
p3, I
p3again with I
p2be directly proportional.Therefore, I
n2and I
p3be directly proportional.That is to say, the electric current on NMOS field effect transistor N2 is directly proportional to the electric current of the output terminal of LDO voltage stabilizer.The variation tendency of the electric current on N2 is consistent with the curent change trend of the output terminal of LDO voltage stabilizer so, and both are same phase change.Therefore, in the time that the electric current of the output terminal of LDO voltage stabilizer increases, the electric current on NMOS field effect transistor N2 increases, and between the drain-source utmost point of NMOS field effect transistor N2, voltage raises.
Because NMOS field effect transistor N1 and N2 are also connected to the output terminal of final stage inverting amplifier P4 as the first inverting amplifier load.NMOS field effect transistor N1 and N2 can equivalence regard a NMOS field effect transistor as on the whole, easy for what illustrate, and this equivalent NMOS field effect transistor still represents with the label L1 that represents the first inverting amplifier output load that N1 and N2 form here.When the electric current of the output terminal of LDO voltage stabilizer increases, the electric current on L1 increases, and between the drain-source utmost point of L1, voltage raises.P4 and L1 form common-source stage inverting amplifier, and the drain electrode of P4 is as the output terminal of this common-source stage inverting amplifier, and its output voltage and electric current are pressed curvilinear motion as shown in Figure 3.Fig. 3 is the output voltage curve of the common-source stage inverting amplifier of the PMOS field effect transistor P4 shown in Fig. 1 and the first inverting amplifier output load L1 formation.The curve description of describing with solid line be the relation between output voltage and the output current of NMOS field effect transistor L1, with the curve description of triangle symbol is the relation between output voltage and the output current of P4, the horizontal ordinate of two intersections of complex curve represents the output voltage of this common-source stage amplifier, and ordinate represents the output current on common-source amplifier.As can be seen from Figure 3, in the drain-source voltage of L1 keeps stable state, along with the rising of the source-drain electrode voltage of P4, the output voltage of this common-source stage amplifier becomes V2 from V1, now from the voltage gain of P4 output be (V2-V1)/Δ Vin (here, Δ Vin is the variable quantity of the input voltage Vgs of P4, i.e. Vp4gs2-Vp4gs1).But if make the output voltage of L1 increase and raise with the electric current of the output terminal of LDO voltage stabilizer according to connected mode above, now the curve of L1 also will rise, as shown in Figure 3 thereupon.Now the output voltage of common-source stage amplifier becomes the V3 that is less than V2, is now (V3-V1)/Δ Vin from the voltage gain of P4 output.Therefore, can find out in conjunction with the diagram of Fig. 3, because the output voltage of L1 increases and raises with the electric current of the output terminal of LDO voltage stabilizer, the output voltage gain of P4 reduces thereupon.The gain in the current limliting loop being made up of in-phase amplifier A3 and final stage inverting amplifier A4 (being P4) equals the product of the gain of amplifiers at different levels in in-phase amplifier and the gain of final stage inverting amplifier A4, and the output voltage gain of P4 reduces to mean the reducing of output voltage gain that will make whole current limliting loop.According to the above description, the electric current increase meeting of the output terminal of LDO voltage stabilizer of the prior art as above produces considerable influence to the output voltage gain in final stage inverting amplifier A4 and the whole current limliting loop that comprises final stage inverting amplifier.
The problem that reduces to bring of the output voltage gain of final stage inverting amplifier A4 is, the first, be difficult to accurately stablize the voltage of the input end (output terminal of the first inverting amplifier A1) of the second inverting amplifier A2; Second, for the production run of LDO voltage regulator circuit is brought adverse effect, due to LDO voltage stabilizer need to adjust positive amplifier A3 in production later stage of product in the resistance of Rt, for example, by the method for cut, thereby offset fabrication error and obtain the high-precision cut-off current of P2 output.But, the degree of accuracy reduction that reduces to cause this later stage adjustment of the output voltage gain of final stage inverting amplifier A4, thus be difficult to obtain high-precision cut-off current.
Summary of the invention
Propose the present invention for overcoming the above-mentioned problems in the prior art, the output gain that the object of this invention is to provide a kind of final stage inverting amplifier is not subject to the LDO voltage stabilizer of the impact of the curent change of the output terminal of the voltage stabilizer of LDO.
A kind of low pressure difference linear voltage regulator provided by the invention, comprises differential amplifier; With the first inverting amplifier of described differential amplifier cascade, the output terminal of described the first inverting amplifier is connected to the first inverting amplifier output load; And final stage inverting amplifier; Described low pressure difference linear voltage regulator further comprises follower and is independent of the final stage inverting amplifier output load of described the first inverting amplifier output load, wherein, the output terminal of described final stage inverting amplifier is connected with the input end of described follower, and the output load of described final stage inverting amplifier accesses the output terminal of described final stage inverting amplifier, and the output terminal of described follower is connected with the output terminal of described the first inverting amplifier.
LDO voltage stabilizer provided by the invention, have reaction velocity and stability faster, and cut-off current precision is higher.
Brief description of the drawings
The general structure that realizes each feature of the present invention is below described with reference to the accompanying drawings.The accompanying drawing providing and associated description be in order to embodiments of the invention to be described, but do not limit the scope of the invention.
Fig. 1 is the structure block diagram of LDO voltage stabilizer of the prior art.
Fig. 2 is the physical circuit figure of LDO voltage stabilizer as shown in Figure 1.
Fig. 3 is output voltage and the output current change curve that illustrates the common-source stage inverting amplifier that PMOS field effect transistor P4 as shown in Figure 1 and the first inverting amplifier output load L1 form.
Fig. 4 is the concrete structure block diagram of LDO voltage stabilizer according to a particular embodiment of the invention.
Fig. 5 is the physical circuit figure of LDO voltage stabilizer as shown in Figure 4.
Embodiment
According to a kind of LDO voltage stabilizer of the first embodiment of the present invention, identical with LDO voltage stabilizer of the prior art, this LDO voltage stabilizer comprise differential amplifier, with the first inverting amplifier of differential amplifier cascade, the input end ref of differential amplifier A0 is connected to reference voltage REF0, and the output terminal of this first inverting amplifier is connected to the first inverting amplifier output load; And final stage inverting amplifier, this LDO voltage stabilizer further comprises follower and is independent of the final stage inverting amplifier output load of the first inverting amplifier output load, the output terminal of final stage inverting amplifier is connected with the input end of follower, and the output terminal of final stage inverting amplifier output load access final stage inverting amplifier, the output terminal of follower is connected with the output terminal of the first inverting amplifier.The first embodiment of the present invention is with respect to the improvements of prior art, the output terminal of this final stage inverting amplifier changes into the input end of follower and being connected, make the disconnection that is connected of the output terminal of final stage inverting amplifier and the output terminal of the first inverting amplifier, and not sharing the first inverting amplifier output load with the first inverting amplifier, only output load is connected the output terminal of final stage inverting amplifier with final stage inverting amplifier with the input end of follower.
Further, the first inverting amplifier output load can comprise two metal-oxide-semiconductor field effect transistors that source class and source class, drain electrode and drain electrode are in parallel, the drain electrode of two metal-oxide-semiconductor field effect transistors accesses the output terminal of the first inverting amplifier simultaneously, and the grid voltage of one of them metal-oxide-semiconductor field effect transistor is constant, the variation tendency of the electric current on another metal-oxide-semiconductor field effect transistor is consistent with the curent change trend of the output terminal of described LDO voltage stabilizer.Electric current in the output load of final stage inverting amplifier is not subject to the impact of the curent change of the output terminal of LDO voltage stabilizer, it is that grid connects constant voltage, drain electrode connects metal-oxide-semiconductor field effect transistor or a termination constant pressure source of final stage inverting amplifier output terminal, the ohmic load of another termination final stage inverting amplifier output terminal.
There is above-mentioned structure, can provide a kind of electric current of the output terminal that can meet the inner quiescent current of voltage stabilizer and LDO voltage stabilizer to change with trend, and the output gain of final stage inverting amplifier is not subject to the LDO voltage stabilizer of the impact of the curent change of the output terminal of LDO voltage stabilizer.
Below in conjunction with Fig. 4 and Fig. 5, LDO voltage stabilizer is according to a second embodiment of the present invention described.Fig. 4 is the concrete structure block diagram of LDO voltage stabilizer 1 according to a second embodiment of the present invention.Fig. 5 is the physical circuit figure of LDO voltage stabilizer 1 as shown in Figure 4.
As shown in Figure 4, LDO voltage stabilizer 1 comprises N-type differential amplifier A0, the first inverting amplifier A1 and the second inverting amplifier A2 of cascade successively.Wherein, the first inverting amplifier A1 comprises the PMOS field effect transistor P1 as the example of amplifier tube wherein, and the grid of P1 and drain electrode are respectively as input end and the output terminal of the first inverting amplifier A1, and the source electrode of P1 connects constant pressure source.The second inverting amplifier A2 comprises the PMOS field effect transistor P2 as the example of amplifier tube wherein, the source electrode of P2 connects constant pressure source, the grid of P2 and drain electrode are respectively as input end and the output terminal of the second inverting amplifier A2, the grid of P2 is connected with the drain electrode of P1, between the inverting input fb of the drain electrode of P2 and differential amplifier A0, be connected with feedback circuit F to form negative-feedback circuit, and the drain electrode of P2 is as the output terminal of this LDO voltage stabilizer 1.Feedback circuit F comprises resistance R 1 and R2.
The output terminal of the first inverting amplifier A1, i.e. the drain electrode of P1 is connected to the variation tendency of electric current wherein and consistent the first inverting amplifier output load L1 of the curent change trend of the output terminal of described LDO voltage stabilizer.The first inverting amplifier output load L1 comprises two NMOS field effect transistor N1 and N2, and wherein the drain electrode of N1 and N2 is all connected with the drain electrode of P1, all ground connection of the source electrode of N1 and N2, and the grid of N1 is connected to reference voltage REF1, keeps grid voltage constant.
The input end of the positive amplifier A3 that LDO voltage stabilizer 1 comprises is connected with the output terminal of described the first inverting amplifier A1, and the output terminal of positive amplifier A3 is connected with the input end of described final stage inverting amplifier A4.Particularly, positive amplifier A3 comprises NMOS field effect transistor N3 and N4, PMOS field effect transistor P3 and resistance R t.The grid of P3 is as the input end of positive amplifier A3.The gate interconnection of P3 and P2, the source electrode of P2 and P3 all connects constant pressure source, and therefore P3 and P2 form current mirroring circuit.Due to the characteristic of current mirroring circuit, the electric current I flowing through between the source electrode of P2 and drain electrode
p2and the electric current I flowing through between the source electrode of P3 and drain electrode
p3be directly proportional.The grid of NMOS field effect transistor N3 is connected the drain electrode of P3 with drain electrode, form diode and connect, the electric current I flowing through between the source electrode of P3 and drain electrode
p3and the electric current I flowing through between the drain electrode of N3 and source electrode
n3equate.The gate interconnection of NMOS field effect transistor N3 and N4, all ground connection of their source electrode, therefore N3 and N4 form another current mirror.Electric current stream I
n3with stream I
n4be directly proportional.NMOS field effect transistor N4 is connected with resistance R t, and the output terminal of positive amplifier 13 is the tie point of NMOS field effect transistor N4 and resistance R t.In positive amplifier A3, P3 and N3 form common-source stage inverting amplifier, and through this common-source stage inverting amplifier, anti-phase and amplification exports N4 to the voltage of input P3, and N4 and Rt form another common-source stage inverting amplifier, and therefore, voltage is through anti-phase and amplify again.Therefore, voltage through twice anti-phase amplification, is amplified by positive in amplifier A3.
The grid of NMOS field effect transistor N2 in the first inverting amplifier load L1 is connected with the grid of the NMOS field effect transistor N3 in positive amplifier A3, and all ground connection of the source electrode of N2 and N3, therefore N2 and N3 form another current mirroring circuit, therefore the electric current I on NMOS field effect transistor N3
n3and I
n2be directly proportional.Introduce as mentioned above the electric current I flowing through between the source electrode of P2 and drain electrode
p2in fact equate with the electric current of the output terminal of LDO mu balanced circuit.Electric current I on NMOS field effect transistor N3
n3with become I
n2direct ratio, and I
n3=I
p3, I
p3again with I
p2be directly proportional.Therefore, I
n2and I
p2be directly proportional.That is to say, the electric current of the electric current on NMOS field effect transistor N2 and the output terminal of LDO voltage stabilizer is approximate proportional, and therefore the variation tendency of the electric current on N2 is consistent with the curent change trend of the output terminal of LDO voltage stabilizer, and both are same phase change.
Therefore, when the electric current of the output terminal of LDO voltage stabilizer hour, when as unloaded in voltage stabilizer, the electric current on NMOS field effect transistor N2 is also less, the quiescent current of voltage stabilizer inside is little, loss is also just less.When the electric current of the output terminal of LDO voltage stabilizer increases, as voltage stabilizer in large current value duty time, also corresponding increase of the electric current on NMOS field effect transistor N2, the electric current on P1 pipe also increases, thus the reaction velocity of this grade raising corresponding to stability in voltage stabilizer.In addition, also position that can be suitable in differential amplifier arranges the NMOS field effect transistor that same grid is connected with the grid of N3, make the principle of differential amplifier based on same internal loss in the time that voltage stabilizer is unloaded less, in the time that voltage stabilizer is in large current value duty, reaction velocity and stability improve.
The voltage that the final stage inverting amplifier A4 that LDO voltage stabilizer 1 comprises exports is for stablizing the voltage of input end of the second inverting amplifier.According to a second embodiment of the present invention, final stage inverting amplifier A4 comprises the PMOS field effect transistor P4 as the example of amplifier tube wherein.The source electrode of P4 connects constant pressure source, and the grid of P4 is as the input end of final stage inverting amplifier A4, and drain electrode is as the output terminal of final stage inverting amplifier A4.The present invention is with respect to the improvement of documents 1, and this LDO voltage stabilizer 1 further comprises follower A5 and is independent of the final stage inverting amplifier output load L2 of the first inverting amplifier output load L1.As shown in Figure 5, follower A5 comprises the NMOS field effect transistor N6 as the example of amplifier tube wherein, and the source electrode of N6 connects constant pressure source, and grid is as the input end of follower A5, and drain electrode is as the output terminal of follower A5.Final stage inverting amplifier output load L2 comprises grid and connects the NMOS field effect transistor N5 of constant pressure source, the source ground of N5, and the drain electrode of N5 is connected to the drain electrode of P4.
Difference from prior art is, in the second embodiment of the present invention, the drain electrode of P4 changes the grid of access N4 into, make the output terminal of P4, be the drain electrode of P4 and the output terminal of P1, i.e. connection between the drain electrode of P1 disconnects, and by being connected with the drain electrode of N5, the drain electrode of P4 be connected to grid connect constant voltage REF2 NMOS field effect transistor N5 form final stage inverting amplifier output load L2, thereby P4 and L2 form a common-source stage inverting amplifier.
Due to the drain electrode of P1 and the drain electrode of P4 disconnection, therefore the connection of P4 and the first inverting amplifier output load L1 of being made up of N1 and N2 also disconnects, the substitute is the current source load L2 that grid connects the N5 formation of constant pressure source, therefore there will not be while increase as the electric current of the output terminal when LDO voltage stabilizer such in prior art the affected problem of output voltage gain of the common-source stage inverting amplifier that comprises P4.
In addition, the grid of N6 connects the drain electrode of P4, accepts the output voltage from P4, and the drain electrode of N6 is connected with the drain electrode of P1, be also just connected with the first inverting amplifier load L1, thereby N6 and L1 forms source follower.The operating characteristic of source follower is, in load L1, how changing of the source-drain electrode voltage of NMOS can not exert an influence to the output voltage gain of source follower, and the output voltage gain of source follower maintains all the time and approximates 1 (the variable quantity ≈ 1 of the variable quantity/input voltage of output voltage).Therefore, the source follower that the voltage of exporting from the common-source stage inverting amplifier of P4 and L2 formation can form via N6 and L1 and voltage gain substantially remain unchanged and be output to the drain electrode of P1, and the voltage of the voltage of the output terminal (being the input end of P2) of stablizing P1 is provided whereby.Thereby, in the case of the curent change of the output terminal of LDO voltage stabilizer, also can accurately stablize the voltage of the output terminal of P1.In addition, the problem that in the adjustment of the later stage of LDO voltage stabilizer, degree of accuracy reduces is also just avoided.
In variation according to a second embodiment of the present invention, the output load of final stage inverting amplifier is ohmic load, and one end of this ohmic load connects constant pressure source, and the other end is connected with the drain electrode of P4.
In addition; as another variation of the second embodiment of the present invention; PMOS field effect transistor in Fig. 5 can all replace with NMOS; and NMOS field effect transistor all replaces with PMOS field effect transistor simultaneously; N-type differential amplifier replaces to P type differential amplifier simultaneously; and the source electrode of each field effect transistor, drain electrode can be done corresponding change according to those skilled in the art's technology general knowledge with being connected of constant pressure source, ground connection respectively, and this does not depart from protection scope of the present invention.
In addition; as the another variation of the second embodiment of the present invention; metal-oxide-semiconductor field effect transistor in Fig. 5 can substitute with PNP pipe or NPN pipe; wherein the grid of metal-oxide-semiconductor field effect transistor, source electrode and drain electrode correspond respectively to base stage, the emitter and collector of PNP or NPN pipe; those skilled in the art can make corresponding change according to technology general knowledge, and this does not depart from protection scope of the present invention.For instance, in this variation, the inverting amplifier that the inverting amplifier that P1 and L1 form and P4 and L2 form is common emitter inverting amplifier, and what N6 and L1 formed is emitter follower (claiming again common-collector amplifier).
In above-mentioned specific embodiment, first, second, the quantity of amplifier tube in final stage inverting amplifier, follower, in-phase amplifier just illustrates, and is not intended to limit the present invention.For instance, the first inverting amplifier can be that more than one amplifier tube cascade forms.
Although specific embodiment of the present invention is described, these embodiment only explain by the mode of example, are not intended to limit scope of the present invention.In fact, innovative approach described herein can be implemented by various other forms; In addition, also can carry out various omissions to method and system described herein, substitute and change and do not deviate from spirit of the present invention.Attached claim and the object of equivalents thereof are to contain the such various forms or the amendment that fall in scope and spirit of the present invention.
Claims (8)
1. a low pressure difference linear voltage regulator, comprising:
Differential amplifier;
With the first inverting amplifier of described differential amplifier cascade, the output terminal of described the first inverting amplifier is connected to the first inverting amplifier output load; And
Final stage inverting amplifier;
It is characterized in that, described low pressure difference linear voltage regulator further comprises follower and the final stage inverting amplifier output load that is independent of described the first inverting amplifier output load,
Wherein, the output terminal of described final stage inverting amplifier is connected with the input end of described follower, and the output load of described final stage inverting amplifier accesses the output terminal of described final stage inverting amplifier, and
The output terminal of described follower is connected with the output terminal of described the first inverting amplifier.
2. low pressure difference linear voltage regulator as claimed in claim 1, is characterized in that,
Described the first inverting amplifier output load comprises two metal-oxide-semiconductor field effect transistors that source electrode is in parallel with source electrode, drain electrode is in parallel with drain electrode, the drain electrode in parallel of described two metal-oxide-semiconductor field effect transistors accesses the output terminal of described the first inverting amplifier, and the grid voltage of one of them metal-oxide-semiconductor field effect transistor is constant, the variation tendency of the electric current on another metal-oxide-semiconductor field effect transistor is consistent with the curent change trend of the output terminal of described low pressure difference linear voltage regulator.
3. low pressure difference linear voltage regulator as claimed in claim 2, is characterized in that, described low pressure difference linear voltage regulator comprises
The second inverting amplifier with described the first inverting amplifier cascade, between the output terminal of wherein said the second inverting amplifier and the inverting input of described differential amplifier, be connected with feedback circuit, and the output terminal of described the second inverting amplifier is as the output terminal of described low pressure difference linear voltage regulator, and
Positive amplifier, the input end of described positive amplifier is connected with the output terminal of described the first inverting amplifier, and the output terminal of described positive amplifier is connected with the input end of described final stage inverting amplifier.
4. low pressure difference linear voltage regulator as claimed in claim 3, is characterized in that,
The output load of described final stage inverting amplifier is resistance.
5. low pressure difference linear voltage regulator as claimed in claim 3, is characterized in that,
The output load of described final stage inverting amplifier is the constant metal-oxide-semiconductor field effect transistor of grid voltage, and the drain electrode of the constant metal-oxide-semiconductor field effect transistor of grid voltage is connected with the output terminal of described final stage inverting amplifier.
6. the low pressure difference linear voltage regulator as described in claim 4 or 5, is characterized in that,
Amplifier tube in described the first inverting amplifier, the second inverting amplifier, final stage inverting amplifier, positive amplifier, follower is metal-oxide-semiconductor field effect transistor.
7. low pressure difference linear voltage regulator as claimed in claim 4, is characterized in that,
Amplifier tube in described the first inverting amplifier, the second inverting amplifier, final stage inverting amplifier is PMOS field effect transistor,
Amplifier tube in described follower is NMOS field effect transistor, and
In described the first inverting amplifier output load, included metal-oxide-semiconductor field effect transistor is NMOS field effect transistor.
8. low pressure difference linear voltage regulator as claimed in claim 5, is characterized in that,
Amplifier tube in described the first inverting amplifier, the second inverting amplifier, final stage inverting amplifier is PMOS field effect transistor,
Amplifier tube in described follower is NMOS field effect transistor,
In described the first inverting amplifier output load, included metal-oxide-semiconductor field effect transistor is NMOS field effect transistor, and
The output load of described final stage inverting amplifier is NMOS field effect transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209941.5A CN102043416B (en) | 2009-10-26 | 2009-10-26 | Low dropout linear voltage regulator |
| JP2010239003A JP5804688B2 (en) | 2009-10-26 | 2010-10-25 | Low dropout linear regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209941.5A CN102043416B (en) | 2009-10-26 | 2009-10-26 | Low dropout linear voltage regulator |
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| CN102043416A CN102043416A (en) | 2011-05-04 |
| CN102043416B true CN102043416B (en) | 2014-06-18 |
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| CN200910209941.5A Expired - Fee Related CN102043416B (en) | 2009-10-26 | 2009-10-26 | Low dropout linear voltage regulator |
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| CN (1) | CN102043416B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5715587B2 (en) | 2012-03-21 | 2015-05-07 | 株式会社東芝 | regulator |
| CN109683655B (en) * | 2018-12-29 | 2020-08-07 | 上海贝岭股份有限公司 | L DO circuit with transient enhancement |
| CN113093853B (en) * | 2021-04-15 | 2022-08-23 | 东北大学 | Improved LDO circuit for realizing low input/output voltage difference in low-voltage starting process |
| CN114647268B (en) * | 2022-03-24 | 2024-05-24 | 中国科学院微电子研究所 | Low-dropout linear voltage stabilizing circuit |
| CN115268550B (en) * | 2022-09-30 | 2022-12-06 | 上海芯炽科技集团有限公司 | Quick-response low-dropout linear voltage stabilizing circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1700129A (en) * | 2004-05-17 | 2005-11-23 | 精工电子有限公司 | Voltage regulator |
| CN1848018A (en) * | 2005-04-15 | 2006-10-18 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| US7173401B1 (en) * | 2005-08-01 | 2007-02-06 | Integrated System Solution Corp. | Differential amplifier and low drop-out regulator with thereof |
| CN1949121A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Double ring low differential voltage linear voltage stabilizer circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4781831B2 (en) * | 2006-01-31 | 2011-09-28 | 株式会社リコー | Constant voltage circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1700129A (en) * | 2004-05-17 | 2005-11-23 | 精工电子有限公司 | Voltage regulator |
| CN1848018A (en) * | 2005-04-15 | 2006-10-18 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| US7173401B1 (en) * | 2005-08-01 | 2007-02-06 | Integrated System Solution Corp. | Differential amplifier and low drop-out regulator with thereof |
| CN1949121A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Double ring low differential voltage linear voltage stabilizer circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102043416A (en) | 2011-05-04 |
| JP2011090683A (en) | 2011-05-06 |
| JP5804688B2 (en) | 2015-11-04 |
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