CN102024708A - 引线框及其形成方法 - Google Patents

引线框及其形成方法 Download PDF

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CN102024708A
CN102024708A CN2009101731728A CN200910173172A CN102024708A CN 102024708 A CN102024708 A CN 102024708A CN 2009101731728 A CN2009101731728 A CN 2009101731728A CN 200910173172 A CN200910173172 A CN 200910173172A CN 102024708 A CN102024708 A CN 102024708A
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lead frame
lead
frame structure
punching out
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高勖
贺青春
徐南
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

本发明公开了用于半导体封装的引线框和制作引线框的方法。该引线框是通过将引线框材料冲制为期望结构而形成的。冲制的引线框随后附到支撑材料。当使用该引线框组装半导体封装时，在划锯单颗化过程中，划锯刀不必切穿大部分引线框材料。因此，划锯刀不会快速磨损。

Description

引线框及其形成方法
技术领域
本发明通常涉及一种用于半导体器件的引线框的装置和方法，并且更具体地涉及一种用于在半导体器件(诸如例如区域安装型半导体器件)中使用的被支撑的冲制的(stamped)引线框。
背景技术
近来在半导体器件技术中已进行开发以实现更小尺寸和规格的半导体器件和达到更高的器件性能。考虑到可实现的元件的较小的规格和尺寸，半导体管芯和封装中的元件密度增加。因此，半导体器件技术的进步超越了半导体封装技术的进步。尽管单独的半导体元件的规格减小，但是在半导体器件封装中仍存在用于半导体元件的空间的不足。
然而，通过对大部分进行比较在近来的开发中保持相对不变的半导体器件的一个方面是引线框设计。典型地，传统的引线框设计不能使其自身适合于在元件的更小规格和尺寸中的其他进步。例如，典型地在区域安装型半导体器件中的引线框的形成中，在诸如四方扁平封装无引线(QFN)、小外形无引线(SON)无引线集成电路(IC)的封装组件和设计中，具有经由元件底侧上的对印刷电路板(PCB)的连接基板表面的接触而到器件的连接。由于引线框材料的易碎或易弯的性质，传统的引线框仅可被设计为具有最小薄度或窄度的引线部分，这是因为该薄的或窄的引线框部分易于在半导体器件的加工环境过程中弯曲或移位。传统的引线框设计典型地不能容易地允许设计人员选择超过有限数目的传统引线设计的关于引线位置的任何期望的配置。例如，在其中实现半刻蚀引线框(half-etching lead frame)的配置中，难以在典型的引线框设计下实现期望的引线配置，这是因为不能通过传统的引线框达到引线框的半刻蚀。放置引线框的引线的传统的技术和设计不适用于业界中的新要求。
因此，需要扩展传统的引线框技术以在使半导体封装组件中的空间最大化的同时允许许多期望的引线位置配置。
附图说明
为了全面地和更加清楚地理解作为非限制性示例的本发明的实施例，结合附图进行下面的描述，在附图中相同的参考数字表示相似的或对应的元件、区域和部分，并且其中：
图1形象化地示出了根据本发明的实施例的引线框制造；
图2A～2D示出了在根据本发明的实施例的工艺的不同步骤中的用于形成引线框的冲压器和模具的横截面图；
图3是根据本发明的实施例的方法的流程图；
图4A～4C示出了根据本发明的实施例的在冲制工艺之后(图4A)，在线接合(图4B)之后和在模制成型(图4C)之后的引线框；
图5A～5B更加详细地示出了根据本发明的实施例的如图3B中指出的区域A(图5A)和B(图5B)的线接合之后的引线框的区域；并且
图6更加详细地示出了根据本发明的实施例的图4C的模制成型之后的引线框。
具体实施方式
一种用于在半导体器件中使用的被支撑的冲制的引线框的装置和方法。该器件包括方形扁平封装无引线(QFN)/功率方形扁平封装无引线(PQFN)集成电路(IC)器件等。通过在引线框加工的冲制过程中添加支撑物或带，被支撑的/带载的冲制的引线框经历包括管芯接合(die bond)线接合、模制成型和划锯单颗化(saw singulation)的组装加工，其中在加工过程中在划锯道中没有金属或其他支撑结构。由于在划锯道中不需要金属，因此可以增加划锯刀的寿命。
本发明的一个方面提供了一种制造引线框的方法，该方法包括将引线框材料冲制为期望的引线框结构；并且使用支撑材料支撑冲制的引线框材料。
在一个实施例中，支撑材料与冲制的引线框材料粘合在一起。支撑材料可以粘合到冲制的引线框材料。
本发明的一个方面提供了一种加工具有引线框的半导体器件的方法，该方法包括将引线框材料冲制为期望的引线框结构；使用支撑材料支撑冲制的引线框材料；将半导体管芯管芯接合在引线框上；使用线使半导体管芯与引线框线接合；使引线框、半导体管芯和线模制成型以形成具有支撑材料的半导体封装；移除支撑材料；并且将半导体器件的单元单颗化，以形成单元半导体器件。
本发明的一个方面提供了一种用于制造引线框的装置，该装置包括：冲压器，其具有用于冲制引线框的表面；用于期望的引线框结构的模具，该模具具有用于定义期望的引线框结构的边缘；和引线框材料容纳区域，在冲压器的所述表面和模具的所述边缘之间，用于容纳引线框材料；和支撑材料容纳区域，用于容纳支撑材料，该支撑材料用于支撑冲压器所冲制的期望的引线框结构。
本发明的一个方面提供了一种引线框，其包括被冲制成期望的引线框结构的引线框材料；和用于支撑引线框的支撑材料。
参考图1，示出了用于由引线框材料20冲制引线框的装置10。引线框材料可由主卷材(master coil)12、主卷材单元14、和/或单卷材单元16形成。该引线框材料可以是铜等，例如铜或者诸如铜CDA194ES的铜材料类型，以及诸如合金42等的其他合金。装置10进一步包括用于将引线框材料冲制为期望的形状和结构的冲制设备18。该装置还固持带材料22，并且被布置为使得当引线框由冲制设备冲制时，冲制的引线框直接固定到支撑物或带材料的表面上。该支撑物可以是例如丙烯酸带、硅带等。
图2A～2D示出了在根据本发明的实施例的工艺的不同步骤中的形成引线框工艺中的冲压器和模具装置之间的交互的横截面图。在图2A中示出了空闲开始50时的引线框冲制和支撑或带载设备的横截面图。该设备包括配置在引线框材料56上面的冲压器52和冲孔模板(stripper)54。引线框材料56安置在冲压器52下面且在模具58上面。模具的边缘57形成了期望的引线框的形状和形态。模具的内侧面59是从边缘57向外张开的或者渐缩远离边缘57的，以确保在加工过程中引线框避免与模具侧面接触。支撑物或带62被安置在引线框材料56和冲压器52下面的模具58下面。
在图2B中，引线框冲制和带载设备被示出为：冲压器开始冲击过程60并且冲压器沿冲孔模板55下落或向下移动。
在图2C中，冲压器52通过冲压器的表面53和模具58的边缘冲压70引线框材料56，以形成期望的引线框64。冲压器连续向下冲击通过模具的边缘57并且通过模具的侧面59。
在图2D中，冲压的引线框64被置于带62上并且形成引线框的引线和标志(flag)66。未形成冲压的引线框64部分的引线框材料56是废料56。冲压的引线框64被固定到支撑物62。
支撑物62支撑冲压的引线框64。该支撑物可以采取不同的形式，例如，该支撑物可以是带、基板、载体等。其他类型的支撑物可以是例如丙烯酸带、硅带等。引线框被从卷材冲离并且附连到支撑物。在支撑物是带的情况中，该带具有将冲压的引线框64固定到该带的粘合剂。
根据本发明的实施例的引线框可被设计为具有比之前可实现的引线框薄或窄的引线。而且，通过本发明的实施例，引线框可被制造用于区域安装型半导体器件。例如，引线框可以布置在诸如方形扁平封装无引线(QFN)、小外形无引线(SON)的无引线集成电路(IC)封装的封装组件中，并且具有经由元件底侧上的对印刷电路板(PCB)的连接基板表面的接触到器件的连接。由于该引线框由支撑物或带62支撑，因此引线框材料被支撑，以耐受在半导体器件封装的加工和封装组装过程中的移动或移位。通过本发明的实施例，引线框可被设计用于具有最小厚度的引线框材料的对于引线位置的任何期望配置。因此，根据本发明的实施例的引线框可以配置在例如半刻蚀引线框中。
该支撑物提供对冲压的引线框的支撑以确保引线框在半导体器件的加工过程中保持期望的冲压的引线框的形状。通过在加工过程中提供对冲压的引线框的额外支撑，引线框的设计可以更加精确地和复杂地进行。由于材料被支撑，因此该引线框可被配置为比使用相同材料的传统引线框可实现的引线框更薄。
图3示出了根据本发明的实施例的方法100。该方法示出了引线框被冲制或冲压102并且随后被置于104诸如带的载体或支撑物上。将认识到，可以在冲制之前将引线框固定到该支撑物。形成用于半导体器件的管芯的基板被安装和划锯106，用于形成管芯。管芯在适当的位置与引线框接合108并且被线接合110。随后使诸如引线框、管芯和导线的半导体元件模制成型112，用于封装工艺。从半导体封装组件移除114诸如带的载体。对半导体封装组件执行划锯单颗化116以形成单独的单元118。
通过在冲制引线框的过程中添加支撑或带载工艺，可以形成用于单独单元的引线和标志，并且随后引线框单独单元直接附连到诸如带的支撑物。当被支撑的冲制的引线框到达组装工厂，并且经历管芯接合线接合加工、模制成型和划锯单颗化时，由于在划锯道中不存在金属，因此使划锯刀的寿命最大化。此外，由于在划锯道中不存在金属，因此在划锯单颗化过程中仅划锯模制成型料，这防止了在划锯单颗化过程中达到高温。通过在划锯单颗化过程中保持较低的温度，延长了划锯刀的寿命，这是因为划锯单颗化过程中的高温引发了划锯刀的磨损。在传统设计中，金属位于划锯道中以在组装工艺过程中提供强的物理连接和单独单元的稳定性。根据本发明的实施例，由于支撑物在组装工艺过程中提供稳定性，因此不需要划锯道中的金属。有利地，由于在本发明的实施例中在划锯道中不存在金属，因此使引线框的材料和制造成本最小化并且低于传统设计。此外，本发明的实施例提供了灵活的引线布局和设计，以及增加的多行引线的能力。
本发明的实施例在区域安装类型的半导体器件配置中是特别有利的，所述配置诸如方形扁平封装无引线(QFN)、小外形无引线(SON)的无引线封装，其具有经由元件底侧的对印刷电路板(PCB)的连接基板表面的接触到器件的连接。在这些类型的器件中，使用半刻蚀引线框。出于上文讨论的节约划锯刀寿命的原因，通过本发明的实施例，每个单元之间的引线和标志通过划锯道连接，并且引线框划锯道被制作为达到半刻蚀。此外，相比于根据本发明的实施例的冲制引线框，刻蚀引线框具有相对较高的成本。通过在引线框冲制中添加带载工艺，允许通过冲压或冲制制造单独单元并且将其直接置于诸如带的支撑物上。在该工艺中，支撑物消除了对划锯道金属的任何要求或需要，并且还减少了划锯单颗化工艺过程中的划锯刀的磨损。
因此，考虑到这些优点，使封装成本最小化。冲制引线框相比于刻蚀引线框成本下降60～70％。可以降低划锯单颗化工艺过程中的封装成本。在实施例的工艺中，通过移除带载工艺，划锯单颗化机能够使用单切割(single cut)模式。
将认识到，实施例可以在其他器件中实现，诸如在所有方形扁平封装无引线(QFN)/功率方形扁平封装无引线(PQFN)产品中实现。
在冲制引线框程序中添加带载工艺。冲制工艺制作用于单独单元的引线和标志，然后单独单元附连在带上。当带载的冲制的引线框到达组装工厂，并且经历管芯接合线接合、模制成型和划锯单颗化时。由于在划锯道中不存在金属，因此划锯刀寿命将增加。
当前，用于方形扁平无引线(QFN)封装的多阵列引线框使用半刻蚀的引线框。每个单元之间的引线和标志由划锯道连接。为了在划锯过程中防止将导致划锯刀快速磨损的高温，该引线框划锯道是半刻蚀的。正常的冲制类型引线框不能达到半刻蚀。刻蚀的引线框相比于冲制的引线框具有较高的成本。在引线框冲制中添加带工艺，目的在于制作直接置于带上的单独单元以消除划锯道金属，从而减少划锯单颗化工艺过程中的划锯刀磨损，随之减少了封装成本。
通过在引线框冲制工艺中添加带载工艺，不象当前的传统引线框设计那样需要金属划锯道引线框。因此增加了划锯单颗化中使用的机器和划锯刀的寿命，特别是对于QFN类型的IC更是如此。而且，由于在引线框中需要使用较少的金属，因此带载的冲制引线框对整体半导体器件较低的封装成本和引线框的较低成本有贡献。由于可以容易地设计和应用多行引线，因此还可以增加引线计数，这也对使封装成本最小化有贡献。有利地，该封装是“绿色”封装，其中不需要Pb镀工艺，这限制了任何环境影响。
尽管描述和说明了本发明的实施例，但是相关技术领域的技术人员将理解，可以进行设计或构造细节中的许多变化或修改而不偏离本发明。

Claims (11)

1.一种制造引线框的方法，所述方法包括：
将引线框材料冲制为期望的引线框结构，所述引线框结构包括多个引线和管芯标志；和
使用支撑材料支撑所述冲制的引线框结构。
2.如权利要求1所述的方法，进一步包括将所述冲制的引线框结构粘合到所述支撑材料。
3.如权利要求1所述的方法，其中所述支撑材料是粘合带。
4.如权利要求3所述的方法，其中所述粘合带是硅带或丙烯酸带。
5.一种组装多个半导体封装的方法，包括：
通过将引线框材料冲制为多个期望的引线框结构形成多个引线框，每个引线框结构包括多个引线和管芯标志；
使用支撑材料支撑所述冲制的引线框结构；
将对应的多个半导体管芯接合到所述多个引线框的管芯标志；
使用线将所述半导体管芯与各引线框结构的所述引线线接合；
使所述引线框结构、半导体管芯和线模制成型，以形成所述多个半导体封装；
移除所述支撑材料；和
经由划锯单颗化使所述多个半导体封装分离。
6.如权利要求5所述的方法，进一步包括将引线框结构粘合到所述支撑材料。
7.如权利要求5所述的方法，其中所述支撑材料是粘合带。
8.如权利要求7所述的方法，其中所述粘合带是硅带或丙烯酸带。
9.一种用于半导体封装的引线框，包括：
通过冲制引线框材料形成的引线框结构；和
支撑所述引线框结构的支撑材料。
10.如权利要求9所述的引线框，其中所述支撑材料是粘合带。
11.如权利要求10所述的引线框，其中所述粘合带是硅带或丙烯酸带。
CN2009101731728A 2009-09-14 2009-09-14 引线框及其形成方法 Pending CN102024708A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300689A (zh) * 2018-11-02 2019-02-01 北京元六鸿远电子科技股份有限公司 带有防滑槽的模压表贴瓷介电容器及制备方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8906803B2 (en) 2013-03-15 2014-12-09 Sandia Corporation Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate
US9490146B2 (en) 2014-06-02 2016-11-08 Stmicroelectronics, Inc. Semiconductor device with encapsulated lead frame contact area and related methods
US9165867B1 (en) 2014-08-01 2015-10-20 Stmicroelectronics, Inc. Semiconductor device with lead frame contact solder balls and related methods

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4798649A (en) * 1983-02-04 1989-01-17 National Semiconductor Corporation Discrete strip taper
US5406124A (en) * 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
KR100204098B1 (ko) * 1995-10-25 1999-06-15 이해규 리이드 프레임 테이핑 장치 및 테이핑 방법
US5729049A (en) * 1996-03-19 1998-03-17 Micron Technology, Inc. Tape under frame for conventional-type IC package assembly
KR100347706B1 (ko) * 2000-08-09 2002-08-09 주식회사 코스타트반도체 이식성 도전패턴을 포함하는 반도체 패키지 및 그 제조방법
US6437429B1 (en) * 2001-05-11 2002-08-20 Walsin Advanced Electronics Ltd Semiconductor package with metal pads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300689A (zh) * 2018-11-02 2019-02-01 北京元六鸿远电子科技股份有限公司 带有防滑槽的模压表贴瓷介电容器及制备方法
CN109300689B (zh) * 2018-11-02 2024-05-10 北京元六鸿远电子科技股份有限公司 带有防滑槽的模压表贴瓷介电容器及制备方法

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