JP4455166B2 - リードフレーム - Google Patents
リードフレーム Download PDFInfo
- Publication number
- JP4455166B2 JP4455166B2 JP2004160230A JP2004160230A JP4455166B2 JP 4455166 B2 JP4455166 B2 JP 4455166B2 JP 2004160230 A JP2004160230 A JP 2004160230A JP 2004160230 A JP2004160230 A JP 2004160230A JP 4455166 B2 JP4455166 B2 JP 4455166B2
- Authority
- JP
- Japan
- Prior art keywords
- slit
- lead
- die pad
- lead frame
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
100 パターン
110 ダイパッド
112 薄肉部
120 インナーリード
122 薄肉部
130 セクションバー
140 吊りリード
150 第1のスリット
160 第2のスリット
100A パターン
150A 第1のスリット
Claims (3)
- 各々が半導体装置を形成する複数の行列状に配置された形成領域を有するリードフレームであって、
前記形成領域は、
半導体チップを載置するダイパッドと、
前記ダイパッド側に向かって前記行列の行方向の幅が広くなるT字形状からなる第1のスリットを有すると共に、前記行列の列方向において前記ダイパッドを支持し、前記第1のスリットに規定される階段形状を有し、全体に圧印加工が施される一対の吊りリードと、
前記吊りリードの前記ダイパッド側とは反対側の根元に設けられて前記行方向に延びる第2のスリットとを有し、
前記T字形状の第1のスリットの前記行方向に延びる部分の前記行方向の幅は、前記階段形状の吊りリードにおいて幅狭となる部分の前記行方向の幅よりも幅広に形成されていることを特徴とするリードフレーム。 - 前記T字形状の第1のスリットの前記列方向に延びる部分は、前記第2のスリットと接続していることを特徴とする請求項1に記載のリードフレーム。
- 前記第2のスリットは、前記行方向の端部位置において前記ダイパッド側が切り欠かれた切り欠き部を有することを特徴とする請求項1又は2に記載のリードフレーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004160230A JP4455166B2 (ja) | 2004-05-28 | 2004-05-28 | リードフレーム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004160230A JP4455166B2 (ja) | 2004-05-28 | 2004-05-28 | リードフレーム |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005340669A JP2005340669A (ja) | 2005-12-08 |
JP2005340669A5 JP2005340669A5 (ja) | 2007-06-14 |
JP4455166B2 true JP4455166B2 (ja) | 2010-04-21 |
Family
ID=35493857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004160230A Expired - Fee Related JP4455166B2 (ja) | 2004-05-28 | 2004-05-28 | リードフレーム |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4455166B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101867106B1 (ko) | 2010-03-30 | 2018-06-12 | 다이니폰 인사츠 가부시키가이샤 | Led용 수지 부착 리드 프레임, 반도체 장치, 반도체 장치의 제조 방법 및 led용 수지 부착 리드 프레임의 제조 방법 |
KR101778832B1 (ko) | 2010-11-02 | 2017-09-14 | 다이니폰 인사츠 가부시키가이샤 | Led 소자 탑재용 리드 프레임, 수지 부착 리드 프레임, 반도체 장치의 제조 방법 및 반도체 소자 탑재용 리드 프레임 |
CN107742472B (zh) * | 2017-09-25 | 2021-03-26 | 昆山国显光电有限公司 | 封装掩膜板、封装方法及显示面板 |
-
2004
- 2004-05-28 JP JP2004160230A patent/JP4455166B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005340669A (ja) | 2005-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI474455B (zh) | 先進四方扁平無引腳封裝結構 | |
US7019388B2 (en) | Semiconductor device | |
US7339259B2 (en) | Semiconductor device | |
US8174096B2 (en) | Stamped leadframe and method of manufacture thereof | |
US20010042904A1 (en) | Frame for semiconductor package | |
US9793194B2 (en) | Leadframe | |
JP2001274308A (ja) | リードフレームおよび半導体装置の製造方法 | |
JP6357371B2 (ja) | リードフレーム、半導体装置及びリードフレームの製造方法 | |
US9984958B2 (en) | Leadframe and semiconductor device | |
US6979886B2 (en) | Short-prevented lead frame and method for fabricating semiconductor package with the same | |
US20020149090A1 (en) | Lead frame and semiconductor package | |
JP2005142554A (ja) | リードフレーム及びこれを適用した半導体パッケージの製造方法 | |
JP2000294711A (ja) | リードフレーム | |
JP2011091145A (ja) | 半導体装置及びその製造方法 | |
JP4243270B2 (ja) | 半導体装置の製造方法 | |
JP4455208B2 (ja) | リードフレーム及び半導体装置の製造方法 | |
JP4455166B2 (ja) | リードフレーム | |
JP2008113021A (ja) | 半導体装置の製造方法 | |
JP5971531B2 (ja) | 樹脂封止型半導体装置及びその製造方法 | |
JP5467506B2 (ja) | 樹脂封止型半導体装置及びその製造方法 | |
US20030098503A1 (en) | Frame for semiconductor package | |
KR100819794B1 (ko) | 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법 | |
JP2002026192A (ja) | リードフレーム | |
EP4425537A2 (en) | Hybrid multi-die qfp-qfn package | |
JP3805767B2 (ja) | リードフレームの製造方法およびそれを用いた半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070418 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070418 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090701 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090707 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090903 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091013 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091209 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100202 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100203 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130212 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130212 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130212 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130212 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |