CN101931010A - Diode and manufacturing method thereof - Google Patents
Diode and manufacturing method thereof Download PDFInfo
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- CN101931010A CN101931010A CN 201010208844 CN201010208844A CN101931010A CN 101931010 A CN101931010 A CN 101931010A CN 201010208844 CN201010208844 CN 201010208844 CN 201010208844 A CN201010208844 A CN 201010208844A CN 101931010 A CN101931010 A CN 101931010A
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Abstract
The invention discloses a diode. The diode comprises a P/N-type substrate, an N+/P+ layer, a first P+/N+ layer, an oxide mask, a lead hole, a front side metal electrode and a back side metal electrode, wherein the N+/P+ layer is formed in the central area of a top surface of the P/N-type substrate; the first P+/N+ layer is formed on the top surface of the P/N-type substrate and in the partial area of the top surface of the N+/P+ layer and is abutted against the P/N-type substrate and the N+/P+ layer respectively; the oxide mask is formed on the first P+/N+ layer and on the top surface of the N+/P+ layer; the lead hole is formed on the oxide mask; the front side metal electrode is formed on the lead hole and on the top surface of the oxide mask; and the back side metal electrode is formed on the bottom surface of the P/N-type substrate. The invention correspondingly provides a manufacturing method of the diode. As dynamic parameters (such as backward recovery time) of the diode are improved, the diode is more suitable for a structure reversely connected in parallel with the diode among BE electrodes of a power switch triode in a switch circuit, and can improve the working stability and reliability of the switch circuit.
Description
Technical field
The present invention relates to semi-conductive manufacturing, relate in particular to a kind of being used between the power switch transistor BE utmost point oppositely and the diode and the manufacture method thereof that connect.
Background technology
As shown in Figure 1, extensively adopt between power switch transistor base stage and emitter oppositely and connect the structure of diode in switching circuits such as electric ballast, electronic transformer and Switching Power Supply, this diode is commonly called the BE diode.The BE diode is that the Switching Power Supply DC converting is the important devices of high-frequency ac, and it plays a very important role to the stability that improves line work, in some electronic circuit, does not have BE diode circuit just can not work.
At present, the BE diode that is used for power switch transistor adopts the 1N4007 rectifier diode usually.But 1N4007 rectifier diode cost is higher, it is mainly used in the high-voltage rectifying field, parameter characteristic is high withstand voltage, dynamic parameter (as reverse recovery time) is not required, chip adopts mesa technique to make, and the 1N4007 rectifier diode of selling on the market does not pass through dynamic parametric test yet.Therefore, the actual parameters needed of BE diode of 1N4007 rectifier diode parameter and power switch transistor BE interpolar does not also match, the use cost height, and effect is relatively poor.
In summary, existing BE diode obviously exists inconvenience and defective on reality is used, so be necessary to be improved.
Summary of the invention
At above-mentioned defective, the object of the present invention is to provide a kind of diode, it has improved the dynamic parameter (as reverse recovery time) of diode, be applicable in the switching circuit between power switch transistor base stage and emitter oppositely and connect the structure of diode more, it can improve the stability and the reliability of switching circuit work.
To achieve these goals, the invention provides a kind of diode, the N+/P+ layer that it comprises P/N type substrate and is formed at described P/N type top surface central area, described diode also comprises: be formed at the top surface of described P/N type substrate and a P+/N+ layer of described N+/P+ layer top surface subregion, a described P+/N+ layer and described P/N type substrate and described N+/P+ layer be adjacency respectively; Be formed at the oxide mask of a described P+/N+ layer and described N+/P+ layer top surface; And being formed at fairlead on the described oxide mask, described fairlead is corresponding with described N+/P+ layer.
According to diode of the present invention, the 2nd P+/N+ layer that described P/N type substrate comprises the P-/N-layer that is connected with described N+/P+ layer and is positioned at described P-N-layer basal surface; And described P/N type substrate forms by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.
According to diode of the present invention, described diode also comprises: the back metal electrode that is formed at the front metal electrode of described fairlead and described oxide mask top surface and is formed at described P/N type substrate basal surface.
According to diode of the present invention, described N+/P+ layer is formed at described P/N type top surface central area by doping and knot, and described P/N type substrate is the groove shape that extend the top surface central area downwards.
According to diode of the present invention, described diode is the BE diode that is used between power switch transistor BE knot.
The present invention is corresponding to provide a kind of diode making process, may further comprise the steps:
A, form the N+/P+ layer in the top surface central area of P/N type substrate;
B, carry out oxidation at the top surface of described P/N type substrate and described N+/P+ layer and form oxide mask;
C, on described oxide mask, carry out photoetching to form the photoetching window with the corresponding zone of described N+/P+ layer;
D, by described photoetching window to described N+/P+ layer mix and knot to form and a described P/N type substrate and described N+/P+ layer P+/N+ layer of adjacency respectively;
E, fairlead photoetching form and the corresponding fairlead of described N+/P+ layer.
According to diode making process of the present invention, also comprise before the described step e: the top surface at a described N+/P+ layer and a described P+/N+ layer carries out oxidation; Also comprise after the described step e: forming the front metal electrode, and metallize to form the back metal electrode at the basal surface of described P/N type substrate in described oxide mask top surface and the enterprising row metalization of described fairlead and metallization photoetching.
According to diode making process of the present invention, the 2nd P+/N+ layer that described P/N type substrate comprises the P-/N-layer that is connected with described N+/P+ layer and is positioned at described P-N-layer basal surface; And described P/N type substrate forms by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.
According to diode making process of the present invention, described steps A comprises:
A1, carry out oxidation at the top surface of described P/N type substrate and form oxide mask;
A2, described steps A 1 formed oxide mask is carried out the part photoetching is positioned at described P/N type top surface central area with formation photoetching window;
A3, the photoetching window that forms to described steps A 2 by mix and knot to form described N+/P+ layer.
According to diode making process of the present invention, described N+/P+ layer is formed in the groove that extends downwards described P/N type top surface central area by doping and knot.
A kind of diode of the present invention comprises P/N type substrate, described P/N type top surface central area forms the N+/P+ layer, the top surface of described P/N type substrate and N+/P+ layer top surface subregion form a P+/N+ layer, and a described P+/N+ layer and described P/N type substrate and described N+/P+ layer be adjacency respectively, and a described P+/N+ layer and N+/P+ layer top surface form oxide mask; Form fairlead on the described oxide mask, described fairlead and the corresponding setting of described N+/P+ layer.The present invention forms a P+/N+ layer by top surface and the N+/P+ layer top surface subregion at P/N type substrate, than the general-purpose diode diffusion of manying one deck P+/N+ layer, and with P/N type substrate and N+/P+ layer adjacency respectively, form (P+, P-, N+) diode and (P+, P-, P+, N+) structure of diode parallel connection or (P+, N-, N+) diode and (P+, N+, N-, N+) structure of diode parallel connection, increased the area of diode pn knot, improved the dynamic parameter (as reverse recovery time) of diode, be applicable in the switching circuit between power switch transistor base stage and emitter oppositely and connect the structure of diode more, it can improve the stability and the reliability of switching circuit work.
Description of drawings
Fig. 1 be between power switch transistor base stage and emitter oppositely and connect the structure of diode;
Fig. 2 is the generalized section of existing diode;
Fig. 3 is the generalized section of an embodiment of the present invention;
Fig. 4 is the generalized section of P type substrate diode;
Fig. 5 is the equivalent structure figure of P type substrate diode;
Fig. 6 is the generalized section of N type substrate diode;
Fig. 7 is the equivalent structure figure of N type substrate diode;
Fig. 8 A is the vertical view of the P/N type substrate of an embodiment of the present invention;
Fig. 8 B is the vertical view of domain structure of the N+/P+ layer of an embodiment of the present invention;
Fig. 8 C is the vertical view of domain structure of a P+/N+ layer of an embodiment of the present invention;
Fig. 8 D is the vertical view of domain structure of the fairlead of an embodiment of the present invention;
Fig. 8 E is the vertical view of domain structure of the front metal electrode of an embodiment of the present invention;
Fig. 9 is exemplary electronic ballast circuit figure;
Figure 10 A is a diode provided by the present invention during as the BE diode, the IC of power switch transistor and VCE oscillogram;
Figure 10 B is an ordinary construction diode during as the BE diode, the IC of power switch transistor and VCE oscillogram;
Figure 10 C is when reverse recovery time, long 1N4007 rectifier diode (trr ≈ 1700ns) was as the BE diode, the IC of power switch transistor and VCE oscillogram;
Figure 10 D is when reverse recovery time, short 1N4007 rectifier diode (trr ≈ 1000ns) was as the BE diode, the IC of power switch transistor and VCE oscillogram;
Figure 11 is a diode manufacturing flow chart of the present invention;
Figure 12 is the flow chart that the present invention forms the N+/P+ layer;
Figure 13 A～Figure 13 I has illustrated that the present invention is in the embodiment in each fabrication stage.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
As shown in Figure 3, a kind of diode 100 of the present invention is used for the BE diode between switching circuit power switch transistor base stage and emitter.It comprises P/N type substrate 10 (being P type substrate or N type substrate), N+/P+ layer 20 (being N+ layer or P+ layer), a P+/N+ layer 30 (i.e. a P+ layer or a N+ layer), oxide mask 40, front metal electrode 50 and back metal electrode 60, and front metal electrode 50 and back metal electrode 60 are connected with lead-in wire respectively.P/N type substrate 10 can form by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.
N+/P+ layer 20 is formed at P/N type substrate 10 top surface central areas by doping and knot, and P/N type substrate 10 is the groove shape that extend the top surface central area downwards.
The one P+/N+ layer 30 is formed at the top surface and the N+/P+ layer 20 top surface subregion of P/N type substrate 10, and a P+/N+ layer 30 and P/N type substrate 10 and N+/P+ layer 20 be adjacency respectively.
The one P+/N+ layer 30 and N+/P+ layer 20 top surface form oxide mask 40.Preferably, oxide mask 40 is SiO2.
Fairlead is formed on the oxide mask 40, and fairlead is corresponding with N+/P+ layer 20.
The 2nd P+/N+ layer 12 that P/N type substrate 10 comprises the P-/N-layer 11 that is connected with N+/P+ layer 20 and is positioned at P-N-layer 11 basal surface; And P/N type substrate 10 can form by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.The 2nd P+/N+ layer 12 is to contact the high-doped zone that forms for forming good ohmic with back metal electrode 60.
In embodiment as shown in Figure 4, the substrate of diode 100 is a P type semiconductor, then P type substrate 10 the 2nd P+ layer 12 that comprises P-layer 11 and be positioned at P-layer 11 basal surface; Form N+ layer 20 in P type substrate 10 top surface central areas; Top surface and N+ layer 20 top surface subregion at P type substrate 10 form a P+ layer 30, the one P+ layer 30 and P type substrate 10 and N+ layer 20 adjacency respectively.As shown in Figure 5, the equivalent structure of diode 100 is (P+, P-, N+) diode and (P+, P-, P+, N+) diode parallel connection.At this moment, the polarity of front metal electrode 50 is for negative; The polarity of back metal electrode 60 is for just.
In embodiment as shown in Figure 6, the substrate of diode 100 is a N type semiconductor, then N type substrate 10 the 2nd N+ layer 12 that comprises N-layer 11 and be positioned at N-layer 11 basal surface; Form P+ layer 20 in N type substrate 10 top surface central areas; Top surface and P+ layer 20 top surface subregion at N type substrate 10 form a N+ layer 30, the one N+ layer 30 and N type substrate 10 and P+ layer 20 adjacency respectively.As shown in Figure 7, then the equivalent structure of diode 100 is (P+, N-, N+) diode and (P+, N+, N-, N+) diode parallel connection.At this moment, the polarity of front metal electrode 50 is for just; The polarity of back metal electrode 60 is for negative.
The main feature of diode 100 provided by the present invention is to increase a P+/N+ layer doping diffusion than general-purpose diode, and by special layout design, the P+/N+ layer 30 of winning is linked together with P/N type substrate 10, its generalized section as shown in Figure 3, its typical layout design is shown in Fig. 8 A～Fig. 8 E.Fig. 8 A is the vertical view of the P/N type substrate of an embodiment of the present invention, and the vertical view of back metal electrode 60 is identical with P/N type substrate 10; Fig. 8 B is the vertical view of domain structure of the N+/P+ layer of an embodiment of the present invention, and the dash area among Fig. 8 B is a N+/P+ layer 20; Fig. 8 C is the vertical view of domain structure of a P+/N+ layer of an embodiment of the present invention, and dash area is a P+/N+ layer 30 among Fig. 8 C; Fig. 8 D is the vertical view of domain structure of the fairlead of an embodiment of the present invention, and dash area is a fairlead among Fig. 8 D; Fig. 8 E is the vertical view of domain structure of the front metal electrode of an embodiment of the present invention, and Fig. 8 E empty partly is the front metal electrode zone.Obviously, domain structure of the present invention is not restricted to the structure shown in Fig. 8 A～Fig. 8 E, also can be other distortion or designs that P+/N+ layer 30 of winning is connected to P/N type substrate 10 and N+/P+ layer 20.
Table 1
Tester adopts the diode reverse recovery time test instrument of Changzhou innovation Electronics Equipment Co., Ltd, and the range of this instrument is 1931ns, surpasses 1931ns and also is shown as 1931ns.Test condition: IF=0.5A, IR=-1A, Irr=-0.25A, R=1 Ω.
As can be seen from Table 1, adopt diode 100 provided by the present invention long more a lot of than trr reverse recovery time of ordinary construction diode and 1N4007 rectifier diode, and trr reverse recovery time of 1N4007 rectifier diode is not of uniform size, parameter is inconsistent.
Fig. 9 is the exemplary electronic ballast circuit figure that has adopted between power switch transistor base stage and emitter oppositely and connect the structure of diode.Performance for contrast ordinary construction diode, 1N4007 rectifier diode and diode provided by the present invention 100, respectively it is tested as machine on the BE diode, thereby when obtaining ordinary construction diode, 1N4007 rectifier diode and diode provided by the present invention 100 respectively as the BE diode, the IC of power switch transistor, VCE oscillogram.IC is a collector current, and VCE is the voltage at collector electrode and emitter two ends.
Figure 10 A is a diode 100 provided by the present invention during as the BE diode, the IC of power switch transistor, VCE oscillogram; Figure 10 B is an ordinary construction diode during as the BE diode, the IC of power switch transistor, VCE oscillogram; Figure 10 C is when reverse recovery time, long 1N4007 rectifier diode (trr ≈ 1700ns) was as the BE diode, the IC of power switch transistor, VCE oscillogram; Figure 10 D is when reverse recovery time, short 1N4007 rectifier diode (trr ≈ 1000ns) was as the BE diode, the IC of power switch transistor, VCE oscillogram.In Figure 10 A～Figure 10 D, solid line partly is the IC oscillogram, and dotted portion is the oscillogram of VCE.
Shown in Figure 10 A, diode 100 provided by the present invention is during respectively as the BE diode, and the burr spike does not appear in power switch transistor IC waveform and VCE waveform, and curve is normal.
Shown in Figure 10 B, the ordinary construction diode is during as the BE diode, and there is burr spike (seeing in the dotted line circle) in the IC waveform of power switch transistor.Because the product of IC and VCE is the instantaneous power consumption of power switch transistor, the existence of this IC spike makes that the power consumption of power switch transistor this moment is very big, and temperature is very high, thereby causes power switch transistor to damage because of oneself power consumption is excessive easily.
Shown in Figure 10 C, when reverse recovery time, long 1N4007 rectifier diode (trr ≈ 1700ns) was as the BE diode, the burr spike did not appear in power switch transistor IC waveform and VCE waveform, and curve is normal.
Shown in Figure 10 D, when reverse recovery time, short 1N4007 rectifier diode (trr ≈ 1000ns) was as the BE diode, there was burr spike (seeing in the dotted line circle) in the IC waveform of power switch transistor.Because the product of IC and VCE is the instantaneous power consumption of power switch transistor, the existence of this IC spike makes that the power consumption of power switch transistor this moment is very big, and temperature is very high, thereby causes power switch transistor to damage because of oneself power consumption is excessive easily.
From above learning, the BE diode reverse recovery time is grown, the IC electric current of power switch transistor does not have the burr spike, the power consumption of power switch transistor self can reduce, the reliability and stability of work can improve, and the BE diode reverse recovery time lacks, the jagged spike of IC electric current of power switch transistor, the power switch transistor oneself power consumption can increase, and the reliability and stability of work can reduce.Diode 100 provided by the present invention increases a P+/N+ layer doping diffusion than general-purpose diode, increased the area of diode pn knot, make that the diode reverse recovery time is longer, thereby be applicable in the switching circuit between power switch transistor base stage and emitter oppositely and connect the structure of diode more, can improve the stability and the reliability of switching circuit work.
As shown in figure 11, the present invention also provides a kind of method that is used to make above-mentioned diode 100, and it mainly may further comprise the steps:
S101 forms N+/P+ layer 20 in the top surface central area of P/N type substrate 10; N+/P+ layer 20 is by mixing and knot is formed at the top surface central area of P/N type substrate 10, and P/N type substrate 10 is the groove shape that extend the top surface central area downwards.
S102 carries out oxidation at the top surface of P/N type substrate 10 and N+/P+ layer 20 and forms oxide mask 40.Oxide mask 40 is preferably SiO2.
S103 carries out photoetching to form the photoetching window with N+/P+ layer 20 corresponding zone on oxide mask 40.
S104, by the photoetching window to N+/P+ layer 20 mix and knot to form and P/N type substrate 10 and N+/P+ layer 20 a P+/N+ layer 30 of adjacency respectively.
S105, the fairlead photoetching forms and N+/P+ layer 20 corresponding fairlead.
Also comprise before the step S105: the top surface at a N+/P+ layer 20 and a P+/N+ layer 30 carries out oxidation, forms one deck oxide film.Also comprise after the step S105: in oxide mask 40 top surfaces and the enterprising row metalization of fairlead and metallization photoetching to form front metal electrode 50; Basal surface at P/N type substrate 10 metallizes to form back metal electrode 60.
Preferably, the 2nd P+/N+ layer 12 that P/N type substrate 10 comprises the P-/N-layer 11 that is connected with N+/P+ layer 20 and is positioned at P-N-layer 11 basal surface, and P/N type substrate 10 can form by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.
Single-chip substrate diffusion way: at first choose the P-/N-monocrystal material, its resistivity is typically chosen in 30-60 Ω * cm thickness and is typically chosen in 500-550 μ m; Again by two-sided diffusion the 2nd P+/N+ layer 12 of substrate, and with wherein attenuate, a polishing back form P/N type substrate 10.In the present embodiment, P-/N-layer 11 thickness generally are controlled at 40-80 μ m, and the thickness of the 2nd P+/N+ layer 12 is typically chosen in 150-200 μ m, and surperficial square resistance is typically chosen in 0.005-0.015 Ω/mouth.
The single-chip diffusion way: at first choose the P-/N-monocrystal material, its resistivity is typically chosen in 30-60 Ω * cm, the about 180-250 μ of thickness m; On this material foundation, form N+/P+ layer 20 earlier, form a P+/N+ layer 30 again, when forming a P+/N+ layer 30 in the front, form the 2nd P+/N+ layer 12 overleaf simultaneously, form P/N type substrate 10 whereby, and then form fairlead, positive back metal electrode etc.The 2nd P+/N+ layer 12 technological parameter are identical with a P+/N+ layer 30, concrete technological parameter: emitter region pre-expansion: 950-1050 ℃, and R mouth=4-15 Ω/mouth; Knot temperature: T=1100-1200 ℃; Knot time: t=30-150min, N2 atmosphere; Knot junction depth: 3-10 μ m, R mouth=3-12 Ω/mouth.
The epitaxial wafer mode: choose the P+/N+ monocrystal material, its resistivity is typically chosen in 0.01-0.02 Ω * cm, the about 450-550 μ of thickness m; Form P/N type substrate 10 by extension one deck P-/N-layer on the 2nd P+/N+ layer 12 11 again.General SiHC13 (trichlorosilane) or the SiH2C12 (dichloro-dihydro silicon) of adopting, at 1000-1150 ℃ of epitaxial growth P-/N-layer 11, p type impurity generally adopts B2H6 (diborane), N type impurity generally adopts PH3 (phosphine), the resistivity of P-/N-layer 11 generally is controlled at 30-60 Ω * cm, and the thickness of P-/N-layer 11 generally is controlled at 40-80 μ m.After forming P/N type substrate 10, form N+/P+ layer 20, a P+/N+ layer 30, fairlead and front metal electrode 50 again, form behind the front metal electrode 50 again with the 2nd P+/N+ layer 12 attenuate at the back side some, generally the thickness with the 2nd P+/N+ layer 12 at the back side keeps 180-250 μ m, does back metal electrode 60 at last again.
As shown in figure 12, step S101 is used to form N+/P+ layer 20, and it mainly comprises the steps:
S201 carries out oxidation at the top surface of P/N type substrate 10 and forms oxide mask 40.
S202 carries out the part photoetching is positioned at P/N type substrate 10 top surface central areas with formation photoetching window to the formed oxide mask 40 of step S201.
S203, the photoetching window that forms to step S202 by mix and knot to form N+/P+ layer 20.
With reference to figure 13A～Figure 13 I, can begin to make diode 100 from P/N type substrate 10, idiographic flow comprises the steps:
One, forms P/N type substrate 10, as shown in FIG. 13A, the 2nd P+/N+ layer 12, the two P+/N+ layer 12 that P/N type substrate 10 comprises P-/N-layer 11 and is positioned at P-N-layer 11 basal surface are to contact the high-doped zone that forms for forming good ohmic with back metal electrode 60.The concrete mode that forms P/N type substrate 10 is above having done detailed description, so do not repeat them here.
Two, the top surface at P/N type substrate 10 carries out oxidation formation oxide mask 40.Oxidizing temperature T=1050-1100 ℃, oxidization time t=20-40min adopts wet-oxygen oxidation, and oxidated layer thickness approximately
Form structure shown in Figure 13 B whereby.
Three, the oxide mask among Figure 13 B 40 is carried out the part photoetching and be positioned at the photoetching window of P/N type substrate 10 top surface central areas, form structure shown in the 13C whereby with formation.Adopt negative glue photoetching, the thick about 1.5 μ m of photoresist.
Four, in Figure 13 C the pairing P/N type of photoetching window substrate 10 by mix and knot to form N+/P+ layer 20.Concrete technological parameter: ion implantation energy: 60kev; Implantation concentration: 5E14-1E15cm-3; Knot temperature: T=1200-1250 ℃; Knot time: t=200-400min, N2 atmosphere; Knot junction depth: 12-25 μ m, R mouth=50-150 Ω/mouth.Carry out oxidation after forming N+/P+ layer 20, carry out oxidation with top surface and form oxide mask 40 again at P/N type substrate 10 and N+/P+ layer 20.Form structure shown in Figure 13 D whereby.
Five, on oxide mask 40, carry out photoetching to form the photoetching window with N+/P+ layer 20 corresponding zone.Adopt negative glue photoetching, the thick about 1.5 μ m of photoresist.Form structure shown in Figure 13 E whereby.
Six, mix and knot by the P-/N-layer 11 of photoetching window among Figure 13 E, to form respectively and P/N type substrate 10 and N+/P+ layer 20 a P+/N+ layer 30 of adjacency respectively to N+/P+ layer 20 and P/N type substrate 10.Concrete technological parameter: emitter region pre-expansion: 950-1050 ℃, R mouth=4-15 Ω/mouth; Knot temperature: T=1100-1200 ℃; Knot time: t=30-150min, N2 atmosphere; Knot junction depth: 3-10 μ m, R mouth=3-12 Ω/mouth.Simultaneously, the top surface at a N+/P+ layer 20 and a P+/N+ layer 30 carries out oxidation.Form structure shown in Figure 13 F whereby.
Seven, fairlead photoetching is at the top surface formation fairlead of N+/P+ layer 30.Adopt negative glue photoetching, the thick about 1.5 μ m of photoresist.Form structure shown in Figure 13 G whereby.
Eight, in oxide mask 40 top surfaces and enterprising row metalization of fairlead and metallization photoetching.Adopt the method for front metal evaporation aluminium during metallization, vacuum degree is higher than 6.0E-4pa, aluminum layer thickness: 3-6 μ m.Adopt negative glue photoetching, the thick about 1.5 μ m of photoresist during the metallization photoetching.Form structure shown in Figure 13 H whereby.
Nine, the basal surface at the 2nd P+/N+ layer 12 of P/N type substrate 10 metallizes, with final formation diode 100.Adopt the back metal evaporation during metallization, vacuum degree is higher than 6.0E-4pa; Metal is Ti/Ni/Ag or Cr/Ni/Ag; Metal layer thickness is respectively: 500-3000/2000-5000/5000-
Form structure shown in Figure 13 I whereby.
In sum, a kind of diode of the present invention comprises P/N type substrate, described P/N type top surface central area forms the N+/P+ layer, the top surface of described P/N type substrate and N+/P+ layer top surface subregion form a P+/N+ layer, and a described P+/N+ layer and described P/N type substrate and described N+/P+ layer be adjacency respectively, and a described P+/N+ layer and N+/P+ layer top surface form oxide mask; Form fairlead on the described oxide mask, described fairlead and the corresponding setting of described N+/P+ layer.The present invention forms a P+/N+ layer by top surface and the N+/P+ layer top surface subregion at P/N type substrate, than the general-purpose diode diffusion of manying one deck P+/N+ layer, and with P/N type substrate and N+/P+ layer adjacency respectively, form (P+, P-, N+) diode and (P+, P-, P+, N+) structure of diode parallel connection or (P+, N-, N+) diode and (P+, N+, N-, N+) structure of diode parallel connection, increased the area of diode pn knot, improved the dynamic parameter (as reverse recovery time) of diode, be applicable in the switching circuit between power switch transistor base stage and emitter oppositely and connect the structure of diode more, it can improve the stability and the reliability of switching circuit work.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. diode, the N+/P+ layer that it comprises P/N type substrate and is formed at described P/N type top surface central area is characterized in that described diode also comprises:
Be formed at the top surface of described P/N type substrate and a P+/N+ layer of described N+/P+ layer top surface subregion, a described P+/N+ layer and described P/N type substrate and described N+/P+ layer be adjacency respectively;
Be formed at the oxide mask of a described P+/N+ layer and described N+/P+ layer top surface;
And being formed at fairlead on the described oxide mask, described fairlead is corresponding with described N+/P+ layer.
2. diode according to claim 1 is characterized in that, the 2nd P+/N+ layer that described P/N type substrate comprises the P-/N-layer that is connected with described N+/P+ layer and is positioned at described P-N-layer basal surface; And described P/N type substrate forms by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.
3. diode according to claim 1 is characterized in that, described diode also comprises: the back metal electrode that is formed at the front metal electrode of described fairlead and described oxide mask top surface and is formed at described P/N type substrate basal surface.
4. diode according to claim 1 is characterized in that, described N+/P+ layer is formed at described P/N type top surface central area by doping and knot, and described P/N type substrate is the groove shape that extend the top surface central area downwards.
5. diode according to claim 1 is characterized in that, described diode is the BE diode that is used between power switch transistor BE knot.
6. a diode making process is characterized in that, may further comprise the steps:
A, form the N+/P+ layer in the top surface central area of P/N type substrate;
B, carry out oxidation at the top surface of described P/N type substrate and described N+/P+ layer and form oxide mask;
C, on described oxide mask, carry out photoetching to form the photoetching window with the corresponding zone of described N+/P+ layer;
D, by described photoetching window to described N+/P+ layer mix and knot to form and a described P/N type substrate and described N+/P+ layer P+/N+ layer of adjacency respectively;
E, fairlead photoetching form and the corresponding fairlead of described N+/P+ layer.
7. diode making process according to claim 6 is characterized in that, also comprise before the described step e: the top surface at a described N+/P+ layer and a described P+/N+ layer carries out oxidation;
Also comprise after the described step e: forming the front metal electrode, and metallize to form the back metal electrode at the basal surface of described P/N type substrate in described oxide mask top surface and the enterprising row metalization of described fairlead and metallization photoetching.
8. diode according to claim 6 is characterized in that, the 2nd P+/N+ layer that described P/N type substrate comprises the P-/N-layer that is connected with described N+/P+ layer and is positioned at described P-N-layer basal surface; And described P/N type substrate forms by the diffusion of single-chip substrate, single-chip diffusion or epitaxial wafer mode.
9. manufacture method according to claim 6 is characterized in that, described steps A comprises:
A1, carry out oxidation at the top surface of described P/N type substrate and form oxide mask;
A2, described steps A 1 formed oxide mask is carried out the part photoetching is positioned at described P/N type top surface central area with formation photoetching window;
A3, the photoetching window that forms to described steps A 2 by mix and knot to form described N+/P+ layer.
10. manufacture method according to claim 9 is characterized in that, described N+/P+ layer is formed in the groove that extends downwards described P/N type top surface central area by doping and knot.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110444477A (en) * | 2019-08-21 | 2019-11-12 | 扬州杰利半导体有限公司 | A kind of processing technology of planar diode |
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