CN101911035B - 通过存储器地址映射使处理器与外部设备相接口的桥电路 - Google Patents

通过存储器地址映射使处理器与外部设备相接口的桥电路 Download PDF

Info

Publication number
CN101911035B
CN101911035B CN200880123203.2A CN200880123203A CN101911035B CN 101911035 B CN101911035 B CN 101911035B CN 200880123203 A CN200880123203 A CN 200880123203A CN 101911035 B CN101911035 B CN 101911035B
Authority
CN
China
Prior art keywords
memory
interface
address
control module
bridge circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200880123203.2A
Other languages
English (en)
Chinese (zh)
Other versions
CN101911035A (zh
Inventor
松本宗久
九野信一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
Original Assignee
Mawier International Trade Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mawier International Trade Co Ltd filed Critical Mawier International Trade Co Ltd
Publication of CN101911035A publication Critical patent/CN101911035A/zh
Application granted granted Critical
Publication of CN101911035B publication Critical patent/CN101911035B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
CN200880123203.2A 2007-12-26 2008-12-23 通过存储器地址映射使处理器与外部设备相接口的桥电路 Active CN101911035B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1667007P 2007-12-26 2007-12-26
US61/016,670 2007-12-26
US12/333,854 US7870323B2 (en) 2007-12-26 2008-12-12 Bridge circuit for interfacing processor to main memory and peripherals
US12/333,854 2008-12-12
PCT/IB2008/003613 WO2009081271A1 (en) 2007-12-26 2008-12-23 Bridge circuit interfacing a processor to external devices via memory address mapping

Publications (2)

Publication Number Publication Date
CN101911035A CN101911035A (zh) 2010-12-08
CN101911035B true CN101911035B (zh) 2014-02-19

Family

ID=40799980

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880123203.2A Active CN101911035B (zh) 2007-12-26 2008-12-23 通过存储器地址映射使处理器与外部设备相接口的桥电路

Country Status (6)

Country Link
US (1) US7870323B2 (https=)
EP (1) EP2225653A1 (https=)
JP (1) JP4972212B2 (https=)
CN (1) CN101911035B (https=)
TW (1) TWI451262B (https=)
WO (1) WO2009081271A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11048410B2 (en) 2011-08-24 2021-06-29 Rambus Inc. Distributed procedure execution and file systems on a memory interface
WO2013028859A1 (en) 2011-08-24 2013-02-28 Rambus Inc. Methods and systems for mapping a peripheral function onto a legacy memory interface
US9098209B2 (en) 2011-08-24 2015-08-04 Rambus Inc. Communication via a memory interface
JP5876017B2 (ja) * 2013-08-30 2016-03-02 株式会社ソニー・コンピュータエンタテインメント 周辺機器制御装置および情報処理装置
JP6924026B2 (ja) * 2016-12-19 2021-08-25 シナプティクス インコーポレイテッド 半導体装置、ヒューマンインターフェース装置及び電子機器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005338900A (ja) * 2004-05-24 2005-12-08 Matsushita Electric Ind Co Ltd バスブリッジ回路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822550A (en) * 1994-12-22 1998-10-13 Texas Instruments Incorporated Split data path fast at-bus on chip circuits systems and methods
US5857117A (en) * 1995-12-22 1999-01-05 Intel Corporation Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus
JP3061106B2 (ja) * 1996-02-28 2000-07-10 日本電気株式会社 バスブリッジおよびそれを備えた計算機システム
US6275888B1 (en) * 1997-11-19 2001-08-14 Micron Technology, Inc. Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers
US6145029A (en) * 1998-03-13 2000-11-07 Compaq Computer Corporation Computer system with enhanced docking support
US6101566A (en) * 1998-03-13 2000-08-08 Compaq Computer Corporation Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20030191730A1 (en) * 2002-04-05 2003-10-09 Compaq Information Technologies Group, L.P. Unobtrusive rule-based computer usage enhancement system
US20050177829A1 (en) * 2003-10-10 2005-08-11 Vipul Vishwanath Method of applying constraints against discovered attributes in provisioning computers
US7293153B2 (en) * 2003-10-14 2007-11-06 Freescale Semiconductor, Inc. Method and system for direct access to a non-memory mapped device memory
JP2007200169A (ja) * 2006-01-30 2007-08-09 Hitachi Ltd ストレージシステム及び記憶制御方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005338900A (ja) * 2004-05-24 2005-12-08 Matsushita Electric Ind Co Ltd バスブリッジ回路

Also Published As

Publication number Publication date
TW200935239A (en) 2009-08-16
TWI451262B (zh) 2014-09-01
EP2225653A1 (en) 2010-09-08
US7870323B2 (en) 2011-01-11
CN101911035A (zh) 2010-12-08
JP2011508329A (ja) 2011-03-10
US20090172238A1 (en) 2009-07-02
WO2009081271A1 (en) 2009-07-02
JP4972212B2 (ja) 2012-07-11

Similar Documents

Publication Publication Date Title
CN102063267B (zh) 包括用于使主机块大小与数据存储装置的物理块大小匹配的映射桥的数据存储系统
US7788427B1 (en) Flash memory interface for disk drive
CN101266829B (zh) 存储卡、包含存储卡的存储系统及存储卡的操作方法
TWI838563B (zh) 串列記憶體設備i/o模式選擇
CN109407966B (zh) 数据存储装置及其操作方法
JP2013214284A (ja) 読み取りデータ・ストローブ信号を含む低減ピン・カウント（ｒｐｃ）メモリ・バス・インターフェースのための装置及び方法
CN101911035B (zh) 通过存储器地址映射使处理器与外部设备相接口的桥电路
US20120066422A1 (en) Method and system for transferring high-speed data within a portable device
CN100492334C (zh) 串行周边接口装置
CN115113799A (zh) 主机命令的执行方法及装置
CN104102600A (zh) 存储器控制器
US7945812B1 (en) System and method for error correction
WO2018113026A1 (zh) 接口兼容电路
US9037842B2 (en) Booting in systems having devices coupled in a chained configuration
CN107863120B (zh) 数据存储装置及其操作方法
US20110072168A1 (en) Data transfer system with different operating modes
US7949838B1 (en) System and method for managing a memory storage device
US8161214B2 (en) System and method for data transfer using ATA interface
US7921243B1 (en) System and method for a DDR SDRAM controller
US20050198425A1 (en) Combined optical storage and flash card reader using single ide or sata port and method thereof
CN109840222B (zh) 存储器系统及其操作方法
CN115543887B (zh) 一种pci总线与axi4总线桥接方法
US20100318723A1 (en) Memory controller, nonvolatile memory device, and nonvolatile memory system
CN111124960A (zh) 一种基于高速pci-e接口硬盘连接机构
US7146440B1 (en) DMA acknowledge signal for an IDE device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20200427

Address after: Singapore City

Patentee after: Marvell Asia Pte. Ltd.

Address before: Ford street, Grand Cayman, Cayman Islands

Patentee before: Kaiwei international Co.

Effective date of registration: 20200427

Address after: Ford street, Grand Cayman, Cayman Islands

Patentee after: Kaiwei international Co.

Address before: Hamilton, Bermuda

Patentee before: Marvell International Ltd.

Effective date of registration: 20200427

Address after: Hamilton, Bermuda

Patentee after: Marvell International Ltd.

Address before: Babado J San Michael

Patentee before: MARVELL WORLD TRADE Ltd.

TR01 Transfer of patent right